JPS59114826A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59114826A
JPS59114826A JP22454682A JP22454682A JPS59114826A JP S59114826 A JPS59114826 A JP S59114826A JP 22454682 A JP22454682 A JP 22454682A JP 22454682 A JP22454682 A JP 22454682A JP S59114826 A JPS59114826 A JP S59114826A
Authority
JP
Japan
Prior art keywords
film
conductive film
mask
metallic
metallic film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22454682A
Other languages
Japanese (ja)
Inventor
Tatsuo Matsumura
達雄 松村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22454682A priority Critical patent/JPS59114826A/en
Publication of JPS59114826A publication Critical patent/JPS59114826A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Abstract

PURPOSE:To facilitate reduction of width of patterns of electrodes and so forth, especially submicronization of that by a method wherein a second conductive film 2 having larger directivity than a first conductive film 1 is formed on the first conductive film, after which the exposed area of the first conductive film is selectively removed using the second conductive film as a mask. CONSTITUTION:An SiO2 film 4 is etched using a resist film 5 as a mask and further N type operation layer 2 is etched. Next, a first metallic film 6 form a Schottky contact for N type operation layer 2 is formed on the surface of said layer 2 under the resist film 5 and the opening of the film 5. A second metallic film 7 of low resistance and being suitable for forming electrodes is formed on the first metallic film 6 by making method of large directivity. After the resist film 5 is stripped to be removed, the exposed area of the first metallic film 6 is removed using the second metallic film 7 as a mask. Thus the gate electrode composed of the first metallic film 6 and the second metallic film 7 is formed. After that, the SiO2 film 4 is removed and a protective insulating film 8 consisting of SiO2 or the like is newly formed and a necessary wiring 9 is arranged.

Description

【発明の詳細な説明】 (a)  発明の技術分野 本発明は半導体装置の製造方法、特にパターン幅を1〔
μm〕程度以下とするに適する成極等の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, to a method for manufacturing a semiconductor device, in particular a pattern width of 1 [
The present invention relates to a manufacturing method, such as polarization, suitable for achieving a polarization of less than 1 μm.

(b)  技術の背景 マイクロ波用手導体装置として、ガリウム・砒素化合物
(GaAs)を半導体材料とす不シロットキバリア形電
界効果トランジスタ(以下GaAs MESFETと略
称する)が一般に使用されている。これはGaAs化合
物半導体のキャリアの移動度がシリコン(Si)等に比
較して遥に大きく、更にショットキバリア形電界効果ト
ランジスタは構造及び製造工程が他の半導体素子に比較
して簡単であってゲート長の微細化に適するために、該
GaAsMESFETによって優れた高周波特性が得ら
れることによる。
(b) Background of the Technology As a microwave conductor device, an incillary field effect transistor (hereinafter abbreviated as GaAs MESFET), which is made of gallium-arsenide compound (GaAs) as a semiconductor material, is generally used. This is because the carrier mobility of GaAs compound semiconductors is much higher than that of silicon (Si), etc., and also because Schottky barrier field effect transistors have a simpler structure and manufacturing process than other semiconductor devices. This is because the GaAs MESFET provides excellent high frequency characteristics because it is suitable for miniaturization of length.

すなわち、GaAs MES FETにおいてはゲート
長を短縮することによって、遮断周波数及び最大発振周
波数をゲート長にほぼ逆比例して高めることができる。
That is, in a GaAs MES FET, by shortening the gate length, the cutoff frequency and maximum oscillation frequency can be increased in approximately inverse proportion to the gate length.

また最小雑音指数もほぼ遮断周波数に逆比例し、周波数
に比例することが知られている。他方バイポーラトラン
ジスタについては、最小雑音指数は周波数の2乗に比例
して増大するために、GaAs MES FETはマイ
クロ波帯において低雑音増幅素子としてもバイポーラト
ランジスタより優れている。
It is also known that the minimum noise figure is approximately inversely proportional to the cutoff frequency and proportional to the frequency. On the other hand, for bipolar transistors, the minimum noise figure increases in proportion to the square of the frequency, so GaAs MES FETs are also superior to bipolar transistors as low-noise amplification elements in the microwave band.

(c)従来技術と問題点 以上のような特長を有するGaAs MES FETの
優れた高周波特性を最大限に実現するために、そのゲー
ト長のサブミクロン領域への短縮の努力が重ねられてい
る。
(c) Problems with the Prior Art In order to maximize the excellent high frequency characteristics of GaAs MES FETs, which have the above-mentioned features, efforts are being made to shorten the gate length to the submicron region.

一般に超微細加工と呼ばれるこの技術は、レジストをパ
ターニングする技術と、パターニングされたマスクに忠
実(半導体基体上に電極、半導体領域等を形成するエツ
チング等の技術とが複合されたものであることは周昶の
とおシであって、超微細加工用のレジスト材料及び使用
方法、電子ビーム露光等のリングラフィ法、ドライプロ
セスによるエツチング技術などの各分野において開発が
強力に進められている。
This technology, which is generally called ultra-fine processing, is a combination of resist patterning technology and etching technology that faithfully forms electrodes, semiconductor regions, etc. on the semiconductor substrate using the patterned mask. As a result of Shusho's efforts, development is progressing strongly in various fields such as resist materials and methods of use for ultrafine processing, phosphorography methods such as electron beam exposure, and etching techniques using dry processes.

しかしながらこれらの技術を工業的に実施するためには
、例えば半導体基体面の平面性など解決を要する問題点
が多く、マスクにおけるゲート長として0.5〔μm〕
を得ても、半導体菓子のゲート長として0.8〔μm〕
を半導体基板全面に実現することは光を利用する従来方
法によっては極めて困難である。
However, in order to implement these technologies industrially, there are many problems that need to be solved, such as the flatness of the semiconductor substrate surface, and the gate length in the mask is 0.5 [μm].
Even if obtained, the gate length of semiconductor confectionery is 0.8 [μm]
It is extremely difficult to realize this over the entire surface of a semiconductor substrate using conventional methods that utilize light.

ゲート長短縮の手段として、従来一般にGaAsMES
 FETのゲート材料として用いられているアルミニウ
ム(A t)に代えて、例えばモリブデン(Mo)−金
(Au)等を用いて2層以上の金属が積層された構成と
し、最上層の金属をマスクとして下層金属をサイドエツ
チングする製造方法が提案されている。しかしながらこ
の方法においては、エツチング前の制御が困難であって
、ゲート長従ってFETの特性の変動が甚だ大きくなる
Conventionally, GaAsMES has been commonly used as a means of shortening gate length.
Instead of aluminum (At), which is used as a gate material for FETs, two or more metal layers are stacked using, for example, molybdenum (Mo)-gold (Au), and the top layer metal is masked. A manufacturing method in which the underlying metal is side-etched has been proposed. However, in this method, control before etching is difficult, and fluctuations in gate length and therefore FET characteristics become extremely large.

以上の如き現状から、GaAs MES FETのゲー
ト電極長などのパターンについてのサブミクロン化を直
ちに実施することができる製造方法が要望されている。
Under the current situation as described above, there is a demand for a manufacturing method that can immediately implement submicronization of patterns such as the gate electrode length of GaAs MES FETs.

(d)  発明の目的 本発明は半導体装置の電極等のパターン幅の短縮、特に
サブミクロン化を容易に実施することができる製造方法
を提供することを目的とする。
(d) Purpose of the Invention An object of the present invention is to provide a manufacturing method that can easily reduce the pattern width of electrodes, etc. of a semiconductor device, and in particular can easily realize submicron pattern width.

(e)  発明の構成 本発明の前記目的は、半導体基体上に第1−の皮膜と、
該第1の皮膜に接する第2の皮膜とを形成し、該第2の
皮膜に所要の開口を配設して該第2の皮膜をマスクとし
て前記第1の皮膜を選択的に除去し、しかる後前記半導
体基体表出面上に第1の導体皮膜を形成し、次いで該第
1の導体皮膜より大なる指向性をもって該第1の導体皮
膜上に第2の導体皮膜を形成し、少なくとも前記第2の
皮膜を除去した後に前記第2の導体皮膜をマスクとして
前記第1の導体皮膜の表出部分を選択的に除去する工程
を有する半導体装置の製造方法によって達成される。
(e) Structure of the Invention The object of the present invention is to provide a first film on a semiconductor substrate;
forming a second film in contact with the first film, providing a required opening in the second film and selectively removing the first film using the second film as a mask; Thereafter, a first conductive film is formed on the exposed surface of the semiconductor substrate, and then a second conductive film is formed on the first conductive film with greater directivity than the first conductive film, and at least the This is achieved by a method for manufacturing a semiconductor device, which includes the step of selectively removing exposed portions of the first conductor film using the second conductor film as a mask after removing the second conductor film.

(f)  発明の実施例 以下本発明を実施例によシ図面を参照して具体的に説明
する。第1図乃至第5図はGaAaMETFETにかか
る本発明の実施例を示す断面図である○ 第1図参照 半絶縁性GaAs半導体基板l上に設けられたn型動作
層2上に例えば金・ゲルマニウム(AuGe)/金(A
u)を用いてソース・ドレイン電極3.3′を設ける。
(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings. 1 to 5 are cross-sectional views showing an embodiment of the present invention related to a GaAa METFET. See FIG. (AuGe)/Gold (A
Source/drain electrodes 3.3' are provided using u).

次いで例えば二酸化シリ弓ン(Si02)からなる絶縁
皮膜4を厚さ0.5〔μm〕程度に形成してこの半導体
基体表面を被覆する。
Next, an insulating film 4 made of, for example, silicon dioxide (Si02) is formed to a thickness of about 0.5 [μm] to cover the surface of this semiconductor substrate.

第2図参照 5in2膜4上にレジスト膜5を厚さ例えば0.7〔μ
m〕程度に設けて、ゲート電極パターンの開口を例えば
ゲート長方向の幅を1〔μm〕としてリングラフィ法に
よって形成する。
Refer to FIG. 2. A resist film 5 is coated on the 5in2 film 4 to a thickness of, for example, 0.7 [μ].
m], and the opening of the gate electrode pattern is formed by phosphorography with a width of 1 [μm] in the gate length direction, for example.

次いで前記レジスト膜5をマスクとしてSiO2膜4を
例えば弗酸(HF)と弗化アンモニウム(NH,F)と
の混合溶液によりエツチングする。更にn型動作層2を
例えば弗酸(HF)と過酸化水素水(H2O,)との稀
釈混合液によってエツチングする。
Next, using the resist film 5 as a mask, the SiO2 film 4 is etched using a mixed solution of, for example, hydrofluoric acid (HF) and ammonium fluoride (NH, F). Furthermore, the n-type active layer 2 is etched using, for example, a diluted mixture of hydrofluoric acid (HF) and hydrogen peroxide (H2O).

このような動作層2の選択的な除去によるソース−ドレ
イン電流IDSの制御がしばしば行なわれる。
The source-drain current IDS is often controlled by such selective removal of the active layer 2.

第3図参照 例えばスパッタリング法の如く指向性の少ない製造方法
によって、例えばタングステン・シリサイド(WHS 
i s )の如く、n型動作層2に対してショットキ接
触を形成する第1の金属皮膜6を、レジスト膜5及びレ
ジスト膜5の開口部乍のn型動作層20表面上に形成す
る。
See Figure 3. For example, tungsten silicide (WHS) can be produced using a less directional manufacturing method such as sputtering.
A first metal film 6 that forms a Schottky contact with the n-type active layer 2 is formed on the resist film 5 and the surface of the n-type active layer 20 between the openings of the resist film 5, as shown in FIG.

第1の金属皮膜6をスパッタリング法の如く・指向性の
少ない方法によって形成することによって、これはレジ
スト膜5のエツチング断面上にも、基板面に平行な面と
ほぼ同程度の厚さに堆積する。
By forming the first metal film 6 using a less directional method such as a sputtering method, it is deposited on the etched cross section of the resist film 5 to approximately the same thickness as on the surface parallel to the substrate surface. do.

本実施例においてはこの厚さを約0.2〔μm〕として
いる。
In this embodiment, this thickness is approximately 0.2 [μm].

次いで例えば真仝蒸眉法の如く指向性の大きい製造方法
によって、例えば金(Au)の如く低抵抗で電極形成に
適する第2の金属皮膜7を第1の金属皮膜6上に形成す
る。この第2の金属皮膜7は、その底の部分の幅がレジ
スト膜5上に堆積した第1の金属皮膜6の開口間隔程度
となる。すなわち本実施例においてはその幅は約0.6
〔μm〕となる。
Next, a second metal film 7 made of, for example, gold (Au), which has low resistance and is suitable for forming an electrode, is formed on the first metal film 6 by a highly directional manufacturing method such as a true steaming method. The width of the second metal film 7 at its bottom is approximately equal to the opening interval of the first metal film 6 deposited on the resist film 5. That is, in this example, the width is approximately 0.6
[μm].

第4図参照 レジスト膜5を剥離除去した後に、例えば四弗化炭素(
CF4)に酸素(02)を混合したガスを用いるプラズ
マエツチング法によって、第2の金属皮膜7をマスクと
して第1の金属皮膜6の表出部分を除去する。これによ
って第1の金属皮膜6と第2の金属皮W7とよシなるゲ
ート電極が形成される。そのゲート長は本実施例におい
ては、約0.6〔μm〕が実現される。
After peeling and removing the resist film 5 (see FIG. 4), for example, carbon tetrafluoride (
The exposed portion of the first metal film 6 is removed using the second metal film 7 as a mask by a plasma etching method using a gas containing CF4) and oxygen (02). As a result, a gate electrode consisting of the first metal film 6 and the second metal film W7 is formed. In this embodiment, the gate length is approximately 0.6 [μm].

第5図参照 前記SiO2膜4を除去し、改めて8102等による保
護絶縁膜8を設け、所要の配線9を配設する。
Refer to FIG. 5. The SiO2 film 4 is removed, a protective insulating film 8 made of 8102 or the like is provided again, and necessary wiring 9 is provided.

以上説明した実施例は、ゲート電極形成部のn型動作層
2の厚さを薄くしたいわゆるリセス形のFETであるが
、プレーナ形のFETにおいても、前記実施例の5iC
h膜4の如きスペーサ層を所要の厚さとすることによっ
て、同様に本発明を実施することができる。
The embodiment described above is a so-called recess-type FET in which the thickness of the n-type active layer 2 in the gate electrode forming part is reduced, but the 5iC
The present invention can be implemented in a similar manner by setting a spacer layer such as the h-film 4 to a required thickness.

(g)  発明の詳細 な説明した如く本発明によれば、例えばFETのゲート
aの如くパターン幅を1〔μm〕程度以下とする半導体
装置の電極等を工業的に容易に実現することが可能とな
シ、高周波特性、高速屁スイッチング特性の優れた半導
体装置を再現性よ< il制御して製造することが可能
とガる。
(g) As described in detail, according to the present invention, it is possible to industrially easily realize electrodes of semiconductor devices having a pattern width of about 1 [μm] or less, such as the gate a of an FET, for example. In addition, it is possible to manufacture semiconductor devices with excellent high-frequency characteristics and high-speed switching characteristics by controlling reproducibility.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第5図はGaAs MES FETに75−
 ;i−る本発明の実施例を示す断面図である0図にお
いて、1はGaAs基板、2はnm動イ’F I’@ 
。 3.3′はソース・ドレイン電極、4は5jCh膜、 
5はレジスト膜、6は第1の金属皮膜、7(ま第2の金
属皮膜、8は保護絶縁膜、9は配線を示す。 易 l Z 瑯2 図 第3 図 第4 ロ
Figures 1 to 5 show GaAs MES FETs with 75-
; In Figure 0, which is a cross-sectional view showing an embodiment of the present invention, 1 is a GaAs substrate, 2 is a nanometer dynamic i'F I'@
. 3.3' is the source/drain electrode, 4 is the 5jCh film,
5 is a resist film, 6 is a first metal film, 7 is a second metal film, 8 is a protective insulating film, and 9 is a wiring.

Claims (1)

【特許請求の範囲】[Claims] 半導体基体上に第1の皮膜と、該第1の皮膜に接する第
2の皮膜とを形成し、該第2の皮膜に所要の開口を配設
して該第2の皮膜をマスクとして前記第1の皮膜を選択
的に除去し、しかる後前記半導体基体表出面上に第1の
導体皮膜を形成し、次いで該第1の導体皮膜より大なる
指向性をもって該第1の導体皮膜上に第2の導体皮膜を
形成し、少なくとも前記第2の皮膜を除去した後に前記
第2の導体皮膜をマスクとして前記第1の導体皮膜の表
出部分を選択的に除去する工程を有することを特徴とす
る半導体装置の製造方法。
A first film and a second film in contact with the first film are formed on the semiconductor substrate, a required opening is provided in the second film, and the second film is used as a mask to form the second film. A first conductive film is selectively removed, a first conductive film is then formed on the exposed surface of the semiconductor substrate, and a second conductive film is formed on the first conductive film with greater directivity than the first conductive film. the second conductive film is formed, and after removing at least the second conductive film, the exposed portion of the first conductive film is selectively removed using the second conductive film as a mask. A method for manufacturing a semiconductor device.
JP22454682A 1982-12-21 1982-12-21 Manufacture of semiconductor device Pending JPS59114826A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22454682A JPS59114826A (en) 1982-12-21 1982-12-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22454682A JPS59114826A (en) 1982-12-21 1982-12-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59114826A true JPS59114826A (en) 1984-07-03

Family

ID=16815483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22454682A Pending JPS59114826A (en) 1982-12-21 1982-12-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59114826A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489469A (en) * 1987-09-30 1989-04-03 Mitsubishi Electric Corp Field-effect transistor and manufacture thereof
JPH0249426A (en) * 1988-08-11 1990-02-19 Oki Electric Ind Co Ltd Pattern formation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489469A (en) * 1987-09-30 1989-04-03 Mitsubishi Electric Corp Field-effect transistor and manufacture thereof
JPH0249426A (en) * 1988-08-11 1990-02-19 Oki Electric Ind Co Ltd Pattern formation

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