JPS5898979A - Manufacture of fet - Google Patents

Abstract

PURPOSE:To form an FET at a high speed with low noise by self-aligning a gate electrode and source/drain by utilizing selectivity of the chemical reaction of a polysilicon film with an SiO2 film obtained by selectively oxidizing the polysilicon film. CONSTITUTION:Si ions are implanted to a GaAs substrate 1', thereby forming a channel layer 4', and a Si3N4 film 13, a polysilicon film 14, an Si3N4 film 15 and an SiO2 film 16 are then sequentially covered. With source/drain forming masks used the source/drain of the films 16, 15 are removed. With these two films 15, 16 as masks a polysilicon film 14 is selectively oxidized, and an oxidized film 17 is then etched. Subsequently, Si ions 12 are implanted, it is then annealed, and source/drain regions are then formed. Thereafter, the parts corresponding to the source/drain electrodes of the films 17, 14 are removed, and electrodes 7, 8 are covered. Then, the films 13, 14, 15, 16 are removed.

Description

[Detailed Description of the Invention] The present invention provides a high-speed, highly integrated FET that is superior to compound semiconductors.
It relates to the manufacturing process, and uses polysilicon and its selective oxidation to form self-alignment between the gate electrode and source/drain regions.

The FET has a semiconductor substrate 1, as shown in the cross-sectional view in FIG.
Source 2 is formed by implanting impurity ions into the low resistance region.
and a drain 3, and a channel 4 which is a conductive region therebetween, and controls the current 9 flowing between the source electrode 7 and the drain electrode 8 by the depletion layer thickness 6 generated by the voltage applied to the gate electrode 5. This makes it possible to use a transistor element that enables signal control.

In order to operate this device at high speed, the channel length 10 and the distance between the gate electrode 5 and the source/drain/
1' must be narrowed. However, if the gate electrode 5 and the source/drain region 2.3 come into electrical contact, malfunction will occur, so it is necessary to align them with high precision.

On the other hand, in FFs and Ts using GJIAa, conventionally, ions are implanted using the gate electrode as a mask to form the source/drain, and the gate electrode and the source/drain are self-aligned to achieve high precision between the two. The alignment is being performed. In this process, as shown in FIG. 2(a), first, channel ions are implanted into the substrate 1' to form a channel region 4', and then a gate electrode 5' is formed.
'Gold coated.

After that, as shown in FIG. 2(b), this gate electrode 5 is
Ion implantation 12 for source/drain using ' as a mask
The lath/drain lj regions 2' and 3' are formed by annealing at a temperature higher than goor. Therefore, since the gate electrode is exposed to high temperatures of 5ooc or more, the Cr/Ti/ALI film JPTi/Pt/
Au films and the like react with GaAS and cannot be used in this process.

For this reason, a Ti/W film is used as a gate electrode material, but in this case (υ electron beam evaporation Yasbatter equipment is required, productivity is low and it is expensive), (2) gate resistance is high, and the device There are disadvantages such as increased noise.

The purpose of the present invention is to eliminate the above-mentioned drawbacks in the Selfaline process for manufacturing FETs using compound semiconductors,
An object of the present invention is to provide a high-speed and low-noise FET manufacturing method.

In order to achieve the above object, the present invention utilizes the selectivity of the chemical reaction between the polysilicon film and the StO film obtained by selectively oxidizing the polysilicon film to form self-aligned gate electrode and source/drain lines. It's about doing. That is, by depositing polysilicon on the entire surface of the substrate and covering the gate electrode with ST, N, or photoresist material,
After performing ion implantation for the source/drain and further annealing the source/drain, the polysilicon in the source/drain portion is selectively oxidized. Thereafter, a gate electrode is formed by a lift method in which only Si, N, and polysilicon from the gate portion are removed.

In this manner, the gate electrode could be formed after source/drain annealing in the cell 7 alignment process. This will be explained in detail below using examples.

(Embodiment) An embodiment of the present invention is shown in Fig. 3. In this embodiment, first, as shown in Fig. 3(a), a GaAs substrate 1'
After forming a channel layer 4' by implanting Si ions, st, N, film 13 is about 50 nm thick, po IJ Si IJ core film 14 is about @ Q Q nm, 3idJ, film 15
about 100 ” ”%SiO*M 16 t 500
nm% each is sequentially deposited.

Next, using a mask for forming the source/drain, a photolithography process is performed to form the
The source/drain portions of the Si duck films 16 and 8i and the N4 film 15 are removed. Then, using these two films 15 and 16 as masks, the polysilicon film 14 is selectively oxidized by plasma oxidation, and then etched by plasma etching until the oxide layer 17 has a thickness of about 5 Q nm. In this oxidation process, the polysilicon in the gate area is also
7' is oxidized to become n s s o. Also, st, N
The 4 film 14 serves to prevent oxidation from progressing to the GaAS substrate 1' during this oxidation process.

After thinning the sIo film in the source/drain region in this manner, Si ion implantation 12 for forming the source/drain is performed, and further annealing is performed to form the source/drain region. The acceleration voltage of Si ions is about 150 KeV, and the implantation depth Fi into the GaAS substrate 1' is 3000 m.

After forming the source/drain, portions of the SIO film 17 and the St, N film 14 corresponding to the source/drain electrodes are removed by plasma etching, and source/drain electrodes 7.8 are deposited. (C).

This electrode is made of Au-Ge/Ni/Au (7) with a thickness of 1 mm.
The total film thickness is approximately 3001 m.

After this electrode is deposited, the deposited film on the gate electrode part is 13°14.1
5.16 is removed. This is done in the next step 11. first,
A photoresist film 18 is deposited on the entire surface of the substrate (see Fig. 3).
C]). Since the photoresist film is deposited thicker on the concave portions than on the convex portions, the upper surface of the gate portion is thinner than the source/drain portions, as shown in FIG. 3(C). When ion etching is applied to the entire surface of the substrate in a closed state, the result shown in Figure 3(d) is
As shown in FIG.
It is also possible to form an FET of the insulating film-semiconductor type, and instead of the 8i3N film 13, a 8iC film, a TiO film or a W, 0.0% TiO film can be used. A similar effect was obtained by using a stable rim film such as a membrane.

In addition to QaA8, the substrates include I"GaAS,
Even if compound semiconductors such as InGaASP, GaA8P, I''P, etc. were used, it could be applied without any difference.

As explained above, according to the present invention, even though the gate electrode and source/drain are self-lined, the gate electrode can be deposited after annealing the source/drain part. Since the gate electrode is not exposed to high temperatures, electrode materials for which conventional processes have been established can be used, and there is less reaction with the substrate, making it possible to form a stable element.

In addition, since the Selfa line basically uses polysilicon and its selective oxidation, which has been established in the production of silicon FETs, and selectivity to the chemical reaction of the film, the yield rate is low. You can build a process with high quality.

[Brief explanation of the drawing]

Figure 1 is a conceptual diagram of an FET, Figure 2 is a process diagram of a GaASFET using the conventional self-line process, and Figure 3 is a GaAS FE according to an embodiment of the present invention.
It is an explanatory diagram of the T manufacturing process. 1 ・(3a As substrate, 2, 3.2', 3'-"
:/-s/drain region, 4.4'...channel, 5
．． 5'...Gate electrode, 10...Channel length, 11
．． 11'... Distance between gate electrode source/dray/@ region, 14... Polysilicon film, 17... Selective oxidation film, 19.19'... Vapor deposited film for gate electrode and a film deposited on parts other than the gate electrode, 20
...Photoresist film for removing 19' by ion etching.

Claims (1)

[Claims] 1. A process of depositing polysilicon on the surface of a compound semiconductor substrate, a process of forming an insulating film on the polysilicon film, a process of removing a region of the insulating film corresponding to the source/drain electrode, and a process of depositing the above-mentioned source /After selectively oxidizing the polysilicon film corresponding to the drain region, thinning the oxide film to a predetermined thickness, and implanting ions to form the source/drain through the oxide film, the gate A method for manufacturing an FET, characterized in that a self-line between the gate electrode and the source/drain is performed by removing polysilicon from the electrode portion and depositing a metal film for the gate electrode on that portion.