JPS61214482A - Manufacture of schottky-barrier type field-effect transistor - Google Patents

Abstract

PURPOSE:To save the cost of masks while simplifying processes by forming insulating films consisting of two layers to a section, to which a gate electrode must be shaped, on a semiconductor substrate and forming each electrode without photoengraving by using an ion implantation technique, evaporation and a lift-off technique. CONSTITUTION:A semiconductor substrate 1 with an operating layer 2 is employed, an SiO2 film 7 is applied onto the whole surface, an SiN film 8 is applied, and insulating films 8, 7 are etched while using a photo-resist film 6 as a mask through a photoengraving technique. An N<+> region 2b as a low resistor is shaped through an ion implantation technique. The N<+> region 2b is activated, the first layer insulating film 7 is undercut while employing the insulating film 8 as a mask, and a metal having an ohmic contact is applied to form a source electrode 3 and a drain electrode 5. The first layer insulating film 7 is removed through etching, and a metal for a gate electrode is evaporated, and lifted off, thus forming the gate electrode 4.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a Schottky barrier field effect transistor with improved performance and productivity.

Below are the G commonly used in the microwave frequency band.
This will be explained using aAsF'ET1 as an example.

[Conventional technology]

FIG. 2 is a plan view showing the electrode arrangement of a conventional GaAs FET, and FIG. 3 is a sectional view taken along line A-A.

In these figures, 1 is a semi-insulating substrate, 2 is an active layer formed on this semi-insulating substrate 1, 3 is a source electrode having a bonding pad 3aY, and 4 is a bonding pad 4a.
! Motsugu)? lE pole, 5 is the bonding pad 5aY
This is the drain electrode.

A source electrode 3, a gate electrode 4, and a drain electrode 5 are formed on the active layer 2, and undesirable portions of the active layer 2a are removed. The source electrode 3 and the domain electrode 5 then form an ohmic contact with this active layer 2, and the gate electrode 4 forms a Schottky junction with the active layer 2. Also l,
is the gate length and wl is the gate width.

Next, we will discuss the conventional manufacturing method of this GaAsFET in the fourth section.
This will be explained with reference to Figures (a) to (h).

First, as shown in FIG. 4(a), an active layer 2'Ik is formed on a semi-insulating substrate 1 by epitaxial growth.

After applying a photonist film 6'ik on this active layer 2, as shown in the 41st iV (b) K, the photonist film 6' in the portion where the source electrode and the domain electrode are to be formed is formed by photolithography. Remove.

Next, as shown in Fig. 4(c) K, a metal forming an ohmic contact (for example, an AuGe alloy for GaAs) is used.
is deposited by vacuum evaporation method.

Next, as shown in FIG. 4(d)K, after removing the l/cyst film 6, alloying is performed to form the source electrode 3 and dog-in contact m5t- of ohmic contact. Next, as shown in FIG. 4(e), only the portions necessary for the operation of the GaAaFET are covered with a photoresist film 6, and as shown in FIG. 4(f), the other portions are removed by etching. , e) L/cyst film 6Y: Peel off. Next, as shown in Figure 4 (I),
, in order to form a gate electrode, cover with a photoresist film 6 except for the necessary portion 41.

Next, as shown in Figure 4 (h) K, by vacuum evaporation method,
A gate metal such as AI is deposited and a photoresist film 6 is formed.
is peeled off, and the manufacturing process of the GaAsFET is completed.

[Problem that the invention seeks to solve]

The performance of this GaAs FET is determined by the gate length 1. It is known that this is dominated by the effect of parasitic resistance between the source electrode 3 and the drain electrode 5. [
Therefore, it is effective to shorten the gate length by 49'lk and reduce the parasitic resistance in order to improve the performance of GaAsFETs.However, in the conventional manufacturing method, due to dimensional accuracy constraints during photolithography, the gate length is reduced to 1°. If the length is shortened, there is a drawback that productivity deteriorates. Furthermore, even if a method is adopted to reduce the distance between the source electrode 3 and the domain electrode 5 in order to reduce the parasitic resistance, overlapping the gate electrode 4 during photolithography will be extremely difficult, resulting in production problems. It was a problem.

This invention has been made to solve these problems, and is a method for manufacturing GaAsFETs using so-called self-seven line technology, without forming electrode patterns by photolithography as in conventional manufacturing methods. It provides:

[Means for solving problems]

The method for manufacturing a GaAsFET according to the present invention is to first form a two-layer insulating film on a portion of a semiconductor substrate where a gate electrode is to be formed, and then photolithography each electrode using ion implantation technology, vapor deposition, and lift-off technology. It is something that is formed without doing anything.

[Effect]

In this invention, the photolithography technique is applied only when forming the insulating film, and thereafter, the insulating film is manufactured by the self-fading technique using the insulating film for positioning. ·and,
Since the gate electrode has an underlying insulating film cut by 77 degrees, a short gate length can be easily formed. Further, since low resistance regions are formed in the source and drain portions by ion implantation, parasitic resistance is reduced.

〔Example〕

FIG. 1 C&) to (I) are G
FIG. 3 is a cross-sectional view showing the manufacturing process of aAsFET.

In FIG. 1 C&), a semiconductor substrate having an active layer 2 formed on a semi-insulating substrate 1 is used as in the conventional case, and a film such as 5i02 is deposited on the entire surface as the first layer insulating film 7.
Further, a second layer insulating film (for example, S
An iN film 81 is deposited on the second layer insulating film. Next, the first
As shown in Figure (b), a photoresist film 6 is applied and removed by photolithography to the photoresist film 61 other than the part where the gate electrode is to be formed, and the remaining photoresist film 6 is used as a mask to form the second layer and First layer insulating film 8.7
etching. Next, as shown in FIG. 1(a), after removing the photoresist film 6, by ion implantation technology,
An n medium region 2b'Y having low resistance is formed.

Subsequently, after activating the n+ region 2b', as shown in FIG.
d) As shown in K, after undercutting the first layer insulating film yt using the second layer insulating film 8 as a mask, a metal having ohmic contact is deposited as in the conventional method, and the source electrode 3 and the tunnel electrode 5 are form. Next, as shown in FIG. 1(e), the second layer insulating film 8 is removed (1, after alloying treatment j!lt' is performed to form an ohmic contact, the entire surface is covered with the l/rest film 6). to flatten the surface. Next, as shown in FIG. 1(f)K, the first photoresist film 6 is removed by dry etching.
Etching is performed until the surface of the layer insulating film 70 is exposed.

After that, the first layer insulating film 7t is removed by etching, and after the gate electrode metal is vapor deposited, the gate electrode 4 is formed by lift-off, and the manufacturing process of the GaAsFET is completed.
The state shown in FIG. 1(p) is reached.

In the GaAa FET manufactured as described above, the first . Since the gate electrode is formed in the second two layers, the lower insulating film is undercut, and the gate electrode is formed in the remaining part, the gate length is short. can be easily realized, and each process uses self-sufficient 7-line technology, eliminating the need for conventional photolithography.

In the above embodiment, an FET using GaAs has been described, but the same effect can be obtained with other semiconductors.

〔Effect of the invention〕

As explained above, in this invention, first, a two-layer insulating film is left only in the area where the gate electrode is to be formed, and after ion implantation is performed using this as a mask, the lower insulating film is undercut, and the source and tunnel insulating films are implanted. Form the electrode with cellufadiene, and finally change to a single-layer insulating film to form the electrode. As a result, the parasitic resistance between the source and drain electrodes is small, and the gate length is 1. High performance GaAs with short
FETV can be manufactured with high productivity. Additionally, the cost of the mask because it does not require photolithography.

There are effects such as cost reduction due to process simplification.

[Brief explanation of drawings]

Figures 1 (a) to (I) are cross-sectional views of the manufacturing process showing one embodiment of the present invention, Figure 2 is a plan view showing the electrode arrangement 1 of a conventional GaAsFET, and Figure 3 is A of 2-A. A cross-sectional view taken along line -A and FIG. 4 are process diagrams showing a conventional method for manufacturing a GaAaFET. In the figure, 1 is a semi-insulating substrate, 2 is an active layer, 3 is a source electrode, 4 is a gate electrode, and 5 is a tunnel electrode. 6 is a photoresist film, T is a first layer insulating film, and 8 is a second layer insulating film. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] forming a first layer insulating film and a second layer insulating film on a semiconductor substrate having a semi-insulating substrate and an active layer formed thereon; A step of removing the second layer insulating film, a step of forming a low resistance region in the removed portion by ion implantation technology, and undercutting the remaining first layer insulating film using the second layer insulating film as a mask. a step of depositing source and drain electrode metals thereon and forming source and drain electrodes by a lift-off technique;
removing the remaining first and second layer insulating films and coating the entire surface with a photoresist film; and removing the first layer insulating film after removing the photoresist film up to the first layer insulating film. A method for manufacturing a shot-barrier field effect transistor, comprising the steps of: using that portion as a gate formation region, depositing a gate metal, and forming a gate electrode by lift-off.