JPS6167273A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6167273A JPS6167273A JP18811384A JP18811384A JPS6167273A JP S6167273 A JPS6167273 A JP S6167273A JP 18811384 A JP18811384 A JP 18811384A JP 18811384 A JP18811384 A JP 18811384A JP S6167273 A JPS6167273 A JP S6167273A
- Authority
- JP
- Japan
- Prior art keywords
- film
- become
- metal
- source
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910000927 Ge alloy Inorganic materials 0.000 abstract description 2
- 229910001020 Au alloy Inorganic materials 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 230000001105 regulatory effect Effects 0.000 abstract 1
- 229910017401 Au—Ge Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 241000218645 Cedrus Species 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229930194542 Keto Natural products 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 125000000468 ketone group Chemical group 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置特にＧａＡｓＦＥＴの製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, particularly a GaAsFET.
（従来例の構成とその問題点）
従来ＧａＡｓＦＥＴ （砒化ガリウム電界効果トランジ
スタ）は超高周波用など尾用いられるトランジスタであ
るが、高周波特性を良好にするためできるだけダート長
を短かくし、ソース、ダート間の寄生抵抗を小さくして
いる。従来の製造方法の一例を説明すると、第１図（、
）に示すように、たとえばクロムをドープした半絶縁性
ＧａＡｓ基板１の上に活性層２を形成し、その上に第１
図（ｂ）に示すようにアルミニウムなどの電極材料を蒸
着して膜３をつくシ、さらにフォトレジストを塗布した
のちツクターニングしてダート部にレノスト膜４を作る
。レジスト膜４をマスクとしてアルミニウム膜３をエツ
チングし、しかもこのエツチングはレノスト膜４の下部
のアルミニウム膜３が第１図（Ｃ）に示すようにサイド
エツチングにより十分アンダーカットされるように長時
間性なう。この第１図（Ｃ）の状態でＡｕ−Ｇｅ合金お
よびＡｕの蒸着を行なって第１図（ｄ）Ｋ示すように膜
５を作る。つぎにリフトオフを行なってレジスト膜４お
よびその上のＡｕ−Ｇｅ、Ａｕ膜５を除去し、さらに残
っているＡｕ−Ｇｅ、Ａｕ膜５を・Ｐターニングして外
形を整え第１図（ｅ）の状態にする。膜６および７はソ
ース電極およびドレイン電極、膜３はケ゛−ト電極とな
シ、ケ゛−ト電極３と、ソース電極６、ドレイン電極７
の間の間隙ｇが上記のサイドエッチングにより形成され
る。第１図（ｅ）の状態の電極部平面図が第１図（ｆ）
である。(Conventional configuration and its problems) Conventional GaAsFETs (gallium arsenide field effect transistors) are transistors used for ultra-high frequencies, but in order to improve high frequency characteristics, the dart length is shortened as much as possible, and the distance between the source and the dart is This reduces parasitic resistance. An example of a conventional manufacturing method is shown in Figure 1 (
), for example, an active layer 2 is formed on a semi-insulating GaAs substrate 1 doped with chromium, and a first layer is formed on the active layer 2.
As shown in Figure (b), a film 3 is formed by vapor depositing an electrode material such as aluminum, and then a photoresist is applied and then turned to form a renost film 4 on the dirt portion. The aluminum film 3 is etched using the resist film 4 as a mask, and this etching is carried out for a long time so that the aluminum film 3 under the Lenost film 4 is sufficiently undercut by side etching as shown in FIG. 1(C). Now. In the state shown in FIG. 1(C), an Au--Ge alloy and Au are vapor-deposited to form a film 5 as shown in FIG. 1(d)K. Next, lift-off is performed to remove the resist film 4 and the Au-Ge and Au films 5 thereon, and the remaining Au-Ge and Au films 5 are subjected to P turning to adjust the outer shape as shown in Fig. 1(e). state. Films 6 and 7 are source electrodes and drain electrodes, film 3 is a gate electrode, gate electrode 3, source electrode 6, and drain electrode 7.
A gap g between them is formed by the above-mentioned side etching. Figure 1(f) is a plan view of the electrode section in the state shown in Figure 1(e).
It is.
しかし上記のような方法では、ＦＥＴ０高周波特性を最
も支配するダート長Ｌｇが、アルミニウム膜３のサイド
エッチ量で左右されるため、１μｍ以下のデート長を安
定に再現性よく形成するのは困難である。さらに、アル
ミニウム膜３のサイドエツチングを化学的に行なった場
合、反応の不均一性のため、デート電極の輪郭は理想的
な直線とはならず、微小な凹凸を含んだものとなって、
高周波特性が劣化する問題点を有していた。さらにアル
ミニウム膜３のアンダーカット量はアルミニウム膜３の
膜厚程度になるため、アルミニウム膜３を十分厚くする
とｒ−ト長の再現性が乏しくなる。However, with the method described above, it is difficult to stably form a date length of 1 μm or less with good reproducibility because the dart length Lg, which most dominates the FET0 high-frequency characteristics, is influenced by the amount of side etching of the aluminum film 3. be. Furthermore, when the side etching of the aluminum film 3 is carried out chemically, due to the non-uniformity of the reaction, the outline of the date electrode does not become an ideal straight line, but contains minute irregularities.
This had the problem of deteriorating high frequency characteristics. Furthermore, since the amount of undercut of the aluminum film 3 is approximately the same as the thickness of the aluminum film 3, if the aluminum film 3 is made sufficiently thick, the reproducibility of the r-t length will be poor.
したがって、ケ゛−ト抵抗を十分小さくできず、良好な
高周波特性が得られないという問題点も有していた。Therefore, there is a problem in that the gate resistance cannot be made sufficiently small and good high frequency characteristics cannot be obtained.
（発明の目的）
本発明の目的は、従来の欠点を解消し、ケ°−ト長およ
びダート・ソース間隙は小さくし、かつデート抵抗の十
分小さいＦＥＴを再現性よく製造することのできる半導
体装置の製造方法を提供することである。(Object of the Invention) An object of the present invention is to eliminate the drawbacks of the conventional semiconductor device, to reduce the gate length and dart-source gap, and to manufacture an FET with sufficiently small date resistance with good reproducibility. An object of the present invention is to provide a manufacturing method.
（発明の構成）
本発明の半導体装置の製造方法は、基板上にオーミック
となる金属からなる第１の膜を形成し、この上に、−ｅ
ターニングされたフォトレジストの第２の膜を形成し、
この第２の膜をマスクとして、第１の膜をエツチングし
、かつサイドエツチングにより、アンダーカットし、つ
ぎにショットキー障壁となる金属からなる第３の膜を形
成し、第２の膜を除去するりフトオフ工程により、前記
第３の膜を）Ｊ？ターニングするものである。(Structure of the Invention) In the method for manufacturing a semiconductor device of the present invention, a first film made of an ohmic metal is formed on a substrate, and -e
forming a second film of turned photoresist;
Using this second film as a mask, the first film is etched and side-etched to undercut, then a third film made of metal that will become a Schottky barrier is formed, and the second film is removed. By a slip-off process, the third film is removed by) J? It is a turning thing.
（実施例の説明） 本発明の一実施例を第２図に基づいて説明する。(Explanation of Examples) An embodiment of the present invention will be described based on FIG. 2.
第２図（、）に示すようにＧａＡｓ基板１上に活性層２
を形成し、この上に第２図（ｂ）Ｋ示すようにオーミッ
クとなるような金属、たとえばＡｕ−Ｇｅ合金およびＡ
ｕの蒸着を行なって膜５を作る。、さらにフォトレジス
トを塗布したのち・９ターニングして、ソース、ドレイ
ン部にレノスト膜４を作る。As shown in FIG. 2(,), an active layer 2 is formed on a GaAs substrate 1.
As shown in FIG. 2(b)K, ohmic metal such as Au-Ge alloy and A
A film 5 is formed by vapor deposition of u. Then, after coating a photoresist, nine turns are performed to form a renost film 4 on the source and drain portions.
この膜４をマスクとして、Ａｕ−Ｇｅ、 Ａｕ膜５をエ
ツチングし、しかもこのエツチングは膜４の下部のＡｕ
−Ｇｅ、 Ａｕ膜５が第２図（ｃ）に示すようにサイド
エツチングにより充分アンダーカットされるよう時間を
調節する。この第２図（ｅ）の状態でショットキー障壁
となる金属、たとえばアルミニウムの蒸着を行なって第
２図（ｄ）に示すように膜３を作る。Using this film 4 as a mask, the Au-Ge and Au films 5 are etched.
- The time is adjusted so that the Ge, Au film 5 is sufficiently undercut by side etching as shown in FIG. 2(c). In the state shown in FIG. 2(e), a metal, such as aluminum, which will become a Schottky barrier is vapor-deposited to form a film 3 as shown in FIG. 2(d).
つぎにリフトオフを行なってレノスト膜４およびその上
のアルミニウム膜３を除去し；さらにＡｕ−Ｇｅ、Ａｕ
膜５をパターニングして外形を整え第２図（ｅ）の状態
にする。膜６および膜７はソース電極およびドレイン電
極、膜３はケ９−ト電極となシ、ケ９−ト電極３とソー
ス、ドレイン電極６°、７との間隙ｇは上記サイドエツ
チングにより正確にあけられる。第２図（ｅ）の状態の
電極部平面図が第２図（ｆ）である。Next, lift-off is performed to remove the Renost film 4 and the aluminum film 3 thereon;
The film 5 is patterned to adjust its outer shape and become as shown in FIG. 2(e). The films 6 and 7 are source and drain electrodes, and the film 3 is a keto electrode.The gaps g between the gate electrode 3 and the source and drain electrodes 6° and 7 are precisely formed by the side etching described above. It can be opened. FIG. 2(f) is a plan view of the electrode section in the state shown in FIG. 2(e).
以上のように本実施例によれば、アンダーカットをオー
ミックとなる金属膜５に施すため、ｙ −ト長りはレジ
スト膜４のパターンがそのまま転写されるため、ｒ−ト
長の再現性は極めて良好となる。したがってレノストを
電子ビームによシ露光して、０．５μｍ以下の極めて微
細なパターンを作成し、デート長０．５μｍ以下のＦＥ
Ｔでも再現性よく製造することができる。さらに、本発
明では、アルミニウム膜３の厚さは、仕上シダート長に
、影響しないため、十分に厚くしゲート抵抗を小さく、
すぐれた高周波特性が得られる。またダート電極の輪郭
もきれいな直線となシ、一層高周波特性を良くすること
ができる。さらにダート電極とソース電極との間隙は０
．３ないし０．６μｍ程度となり、ソース寄生抵抗が小
さく、すぐれた高周波特性が得られる。As described above, according to this embodiment, since the undercut is applied to the ohmic metal film 5, the pattern of the resist film 4 is directly transferred to the y-t length, so the reproducibility of the r-t length is It becomes extremely good. Therefore, Rennost is exposed to an electron beam to create an extremely fine pattern of 0.5 μm or less, and an FE with a date length of 0.5 μm or less is created.
It can be manufactured with good reproducibility even with T. Furthermore, in the present invention, since the thickness of the aluminum film 3 does not affect the finished cedar length, it is made sufficiently thick to reduce the gate resistance.
Excellent high frequency characteristics can be obtained. Furthermore, if the contour of the dart electrode is a clean straight line, the high frequency characteristics can be further improved. Furthermore, the gap between the dirt electrode and the source electrode is 0.
．． The thickness is approximately 3 to 0.6 μm, and the source parasitic resistance is small and excellent high frequency characteristics can be obtained.
（発明の効果）
本発明の半導体装置の製造方法は、オーミ、りとなる金
属膜にアンダーカットを施し、ショットキー障壁となる
金属膜にはレジストによるリフトオフを行なうため、０
５μｍＪｌ下のケ゛−ト長が再現性よく製造でき、その
実用的効果は大である。(Effects of the Invention) The method for manufacturing a semiconductor device of the present invention undercuts the metal film that will serve as an ohm and ridge, and performs lift-off using a resist on the metal film that will serve as a Schottky barrier.
Cathet lengths of less than 5 μmJl can be manufactured with good reproducibility, and the practical effect is great.
第１図（ａ）ないし第１図（、）は従来のＧａＡｓＦＥ
Ｔの製造工程を説明する断面図、第１図（ｆ）は同電極
平面図、第２図（ａ）ないし第２図（、）は本発明によ
る半導体装置の製造工程を説明する断面図、第２図（ｆ
）は同電極平面図である。
１・・・基板、２・・・活性層、３，５・・・金属膜、
４・・・レジスト膜、６，７・・・電極。
第１図 第２図Figure 1(a) to Figure 1(,) are conventional GaAsFE
1(f) is a plan view of the same electrode; FIGS. 2(a) to 2(a) are sectional views explaining the manufacturing process of the semiconductor device according to the present invention; Figure 2 (f
) is a plan view of the same electrode. 1... Substrate, 2... Active layer, 3, 5... Metal film,
4... Resist film, 6, 7... Electrode. Figure 1 Figure 2
Claims (1)
フトオフ用の第２の膜を順次形成し、該第２の膜をパタ
ーニングし、このパターニングした第２の膜をマスクと
して、前記第１の膜をエッチングし、かつサイドエッチ
ングによりアンダーカットし、つぎにショットキー障壁
となる金属からなる第３の膜を金属蒸着して作り、かつ
前記第２の膜を除去するリフトオフ工程により、前記第
３の膜をパターニングすることを特徴とする半導体装置
の製造方法。A first film made of an ohmic metal and a second film for lift-off are sequentially formed on the substrate, the second film is patterned, and the patterned second film is used as a mask to form the first film. The film is etched and undercut by side etching, and then a third film made of a metal that becomes a Schottky barrier is formed by metal vapor deposition, and the third film is removed by a lift-off process in which the second film is removed. 1. A method for manufacturing a semiconductor device, comprising patterning a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18811384A JPS6167273A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18811384A JPS6167273A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6167273A true JPS6167273A (en) | 1986-04-07 |
Family
ID=16217927
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18811384A Pending JPS6167273A (en) | 1984-09-10 | 1984-09-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6167273A (en) |
-
1984
- 1984-09-10 JP JP18811384A patent/JPS6167273A/en active Pending
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