JPH04171831A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the title semiconductor device maintain the specific electrode shapes even after the heat treatment having excellent electrical characteristics by a method wherein both the second source electrode and the second drain electrode contain Mo layers. CONSTITUTION:After the lamination of a GaAs channel layer 21 on a semiinsulating GaAs substrate 20, the first source electrode 23 and the first drain electrode 24 at the wide electrode interval of exceeding 5mum are formed. Next, after coating the whole surface with an electron ray resist 25, the channel layer 21 on a gate electrode part 26 is exposed by successively drawing with the electron rays. Successively, the recess-etching step is performed so that the current value running between the first source electrode 23 and the first drain electrode 24 may be specified. Later, e.g. Al is evaporated as a gate electrode metal 27 and then the Al in the needless region is removed together with the electron ray resist to form a gate electrode 27. Later, the second source electrode 28 and the second drain electrode 29 at the electrode interval of 1-3mum are formed. At this time, both electrodes contain Mo layers while AuGe layer, Ni layer, Mo layer and Au layer are successively laminated. Finally, the whole body is heat-treated at 430 deg.C for one minute so as to bring it into ohmic contact.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for manufacturing an SHF band field effect transistor made of a compound semiconductor.

<Prior Art> Compound semiconductor elements, such as field effect transistors (hereinafter abbreviated as FETs) using GaAs, are more suitable for high frequency operation than FETs using Si, and therefore their development is progressing.

The cross-sectional structure of a conventional FET is shown in FIG. Semi-insulating GaA
3. First, a GaAs channel layer 2 with a carrier concentration of the order of 1017 F-3 is laminated on the surface of the substrate 1, and after removing the region outside the active region 3 of this GaAs channel layer 2 by etching, a source electrode 4 and a drain electrode 5 are formed. and a gate electrode (Schottky electrode) 6.

The cutoff frequency fT, which is an index of high frequency characteristics of the FET, can be expressed as: (2) 2πL where the gate length is the gate length and the carrier saturation velocity is V. According to the above equation, the shorter the gate length, the higher the cutoff frequency fT and the better the high frequency characteristics.

When writing a gate with a diameter of less than 0.5 μm, it is difficult to use photolithography, so electron beam exposure is used.

An example of a conventional FET manufacturing process using the electron beam exposure method is shown in FIG. 3 and will be described.

■ GaAs channel layer 2 on semi-insulating GaAs substrate 1
is laminated, and then the outside of the active area 3 is removed by etching. Next, the first source electrode 4 and the first drain electrode 5 are formed using a lift-off method.
), Au (~1,0OOA) are sequentially laminated. After electrode formation, heat treatment is performed to obtain ohmic contact. (
FIG. 3(1)) ■ Next, an electron beam resist 7 is applied.

At this time, if the distance 8 between the first source electrode and the first drain electrode is as narrow as 2 μm, the electron beam resist cannot be applied with uniform thickness and with good reproducibility due to the difference in electrode end height. As a countermeasure, the electrode spacing 8 is widened to about 20 μm, and the electron beam resist 7 is applied uniformly and with good reproducibility. After applying the electron beam resist 7, the gate electrode portion 9 is exposed by electron beam drawing to expose the GaAs channel layer 2 of the gate electrode portion (FIG. 3).
2)) Next, recess etching is performed by wet etching or dry etching, and gate electrode metal 6 is deposited. The gate electrode metal 6 is made of, for example, AI and is deposited to a thickness of 2000 Å. (Fig. 3 (3)) ■ Then, in order to reduce the source resistance 10 and drain resistance 11 of the channel layer 2, a second source electrode 12 is further added.
, forming the second drain electrode 13. The second source electrode 12 and the second drain electrode 13 are made of, for example, AuGe (~
1,0OOA), Ni (~200A) Au (+, 0OOA)
A) are sequentially laminated. After electrode formation, heat treatment is performed. (Figures 3 and above are from patent application No. 2-1480 filed by the same applicant.
This was proposed in No. 16 "Method for Manufacturing Semiconductor Devices" (filed on June 6, 1990).

<Problems to be Solved by the Invention> By the way, in the method proposed above, heat treatment is required to reduce the resistance, especially during the process of forming the second source electrode 12 and the second drain electrode 13. However, this Au
In electrodes made of Ge, Ni, and Au, alloying reactions occur unevenly during the heat treatment process, and the electrode metals aggregate, making it impossible to maintain a desired electrode shape. 'Furthermore, there are disadvantages in that the surface flatness is poor and contact resistance is not sufficiently small.

SUMMARY OF THE INVENTION In view of the above points, an object of the present invention is to provide an improved method for manufacturing a semiconductor device.

In order to form a good electrode without agglomeration after heat treatment, in the present invention, after laminating a ■-V group compound semiconductor active layer on a semiconductor substrate, a wide electrode of 5 μm or more is formed. a step of forming a first source electrode and a drain electrode of 1@1 with a distance therebetween; applying an electron beam resist to the semiconductor substrate, and using an electron beam exposure method to form a [[-V group compound semiconductor a step of exposing the surface; a step of etching the exposed surface of the compound semiconductor; a step of depositing a Schottky metal on the semiconductor substrate and removing unnecessary portions of the Schottky metal by a lift-off method to form a gate electrode; The method includes a step of forming a second source electrode and a second drain electrode having a short electrode interval of 1 to 3 μm and stacking an AuGe layer, a Ni layer, a Mo layer, and an Au layer in this order.

<Function> In the above manufacturing method, Mo has a high melting point and is thermally stable, so even in the heat treatment process after electrode formation,
A desired electrode shape can be maintained and good electrical characteristics can be obtained without causing an alloy reaction with the underlying metal.

<Example> Hereinafter, the method for manufacturing a semiconductor device of the present invention will be described with reference to an example.

FIGS. 1 (1) to (4) show a method of manufacturing an FET according to an embodiment.

(2) The entire GaAs channel layer 21 is formed on the semi-insulating GaAs substrate 20, and then the outside of the active region 22 is removed by etching. Next, a lift-off method is used to form a first source electrode 23 and a first drain electrode 24 with an electrode spacing of about 20 μm. Both electrodes 23 and 24 are made of, for example, qILuGe (~1,000A), Ni (~200A)
, A u (~1,0OOA) are sequentially laminated. After forming the electrode, heat treatment is performed at, for example, 390° C. to bring the compound semiconductor and the electrode metal into ohmic contact. (FIG. 1 (1)) ■ Next, after applying the electron beam resist 25, electron beam drawing development is performed sequentially to expose the channel layer 21 of the gate electrode portion 26. (FIG. 2 (2)) , 1st
Recess etching is performed so that the current value flowing between the source electrode 23 and the second drain electrode 24 becomes a predetermined value. After that, the gate electrode metal is made of, for example, Al with a thickness of 2
Deposit 00OA. After vapor deposition, the electron beam resist is peeled off.

At this time, At in the unnecessary region is removed together with the electron beam resist, leaving the gate electrode 27. (Fig. 1 (3)) ■ The second source electrode 28 and the second drain electrode 29 are connected with an electrode spacing of 2 μm.
Form as m. Both electrodes contain MoNtk, e.g. A
uGe layer (~1,0OOA), Ni layer (~200A),
A Mo layer (~l, 000A) and an Au layer (~500A) are sequentially laminated. Next, a heat treatment is performed at, for example, 430° C. for 1 minute to obtain an ohmink contact.

Second source electrode 28, second drain electrode 291/i
: Since it contains an IdMo layer, the predetermined electrode shape is maintained even after heat treatment, and good electrical properties are also obtained.

<Effects of the Invention> As described above, according to the present invention, it is possible to obtain an ohmic electrode that prevents agglomeration of electrode metal, has a flat surface, maintains a desired electrode shape, and has low contact resistance.

This manufacturing method can also be applied to HEMTs in addition to the FETs shown in the examples.

[Brief explanation of the drawing]

Fig. 1 t1) to (4) are process diagrams showing one embodiment of the present invention, Fig. 2 is a sectional view showing a structural example of the prior art, and Fig. 3 [+] to (4) are process diagrams of the prior art. It is a diagram. 20... Semi-insulating GaAs substrate, 21... GaAs
Channel layer, 23...first source electrode, 24...
・First drain electrode, 25...Electron beam resist, 2
6... Gate electrode part, 27... Gate electrode, 28.
...Second source electrode, 29...Second drain electrode. Agent Patent attorney Ume 1) Katsu (and 2 others)-----
--'-1\ 2.3 zu4 =--20 1=-20 Fig. 1 - C-\ Fig. 2 Do-J~--\ 1\1 Fig. 3

Claims (1)

[Claims] (1) After laminating a III-V compound semiconductor layer on a semiconductor substrate, forming a first source electrode and a first drain electrode having a wide electrode interval of 5 μm or more, and applying an electron beam to the semiconductor substrate. a step of applying a resist and exposing the surface of the III-V group compound semiconductor of the gate electrode portion using an electron beam exposure method; a step of etching the exposed compound semiconductor surface by a predetermined amount; and a step of etching the etched compound semiconductor by a predetermined amount. a step of depositing a Schottky metal on the surface and removing unnecessary portions of the Schottky metal by a lift-off method to form a gate electrode; As short as 3μm and made of AuG
A method for manufacturing a semiconductor device, comprising the step of forming a second source electrode and a second drain electrode in which an e layer, a Ni layer, a Mo layer, and an Au layer are laminated in this order.