CN102468151A - Method for making metal gate electrode - Google Patents
Method for making metal gate electrode Download PDFInfo
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- CN102468151A CN102468151A CN2010105536977A CN201010553697A CN102468151A CN 102468151 A CN102468151 A CN 102468151A CN 2010105536977 A CN2010105536977 A CN 2010105536977A CN 201010553697 A CN201010553697 A CN 201010553697A CN 102468151 A CN102468151 A CN 102468151A
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- grid
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Abstract
The invention provides a method for making a metal gate electrode, comprising the following steps: providing a semiconductor substrate on which a dielectric layer is formed and forming a pseudo gate on the surface of the dielectric layer; forming an epitaxial layer on the surface of the pseudo gate using the selective epitaxial process; forming an epitaxial protrusion of the epitaxial layer at the top edge of the pseudo gate, which has an extroversive side surface; forming an insulating side wall on the side surface of the epitaxial layer; injecting ions into the semiconductor substrates at tow sides of the pseudo gate to form a source electrode and a drain electrode; forming an interlayer medium layer on the surface of the semiconductor structure and flattening the surface of the interlayer medium layer till the epitaxial layer at the top of the pseudo gate is exposed; removing the pseudo gate and the epitaxial layer on the surface thereof to form a gate electrode opening; and filling the gate electrode opening to form a metal gate electrode. With the method, the problem of generating voids during filling and forming the metal gate electrode is effectively avoided.
Description
Technical field
The present invention relates to technical field of semiconductors, more specifically, the present invention relates to a kind of manufacture method of metal gate electrode.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic size of MOS transistor is also more and more littler.Constantly dwindle under the situation in the MOS transistor characteristic size, in order to reduce the parasitic capacitance of MOS transistor grid, improve device speed, the gate stack structure of high K gate dielectric layer and metal gate electrode is introduced in the MOS transistor.
For the metal material of avoiding metal gate electrode to other effect on structure of transistor, the gate stack structure of said metal gate electrode and high K gate dielectric layer adopts grid to substitute (replacement gate) technology usually and makes.For example the patent No. is the Chinese patent of ZL01139315.7, promptly provides a kind of and has utilized pseudo-grid to carry out the method that grid substitutes the making metal gates.In this technology, before source-drain area injects, at first form the dummy grid that constitutes by polysilicon in gate electrode position to be formed, said dummy grid is used for autoregistration and forms PROCESS FOR TREATMENT such as source-drain area.And after forming source-drain area, can remove said dummy grid and form gate openings in the position of dummy grid, afterwards, in said gate openings, fill high K gate dielectric layer and metal gate electrode more successively.Because metal gate electrode is made after source-drain area injects completion again, this makes that the quantity of subsequent technique is able to reduce, and has avoided metal material to be inappropriate for the problem of carrying out high-temperature process.
Yet, adopt above-mentioned grid alternative techniques to make MOS transistor and still exist challenge.Along with further dwindling of grid length, this problem is more serious.As shown in Figure 1, in the manufacture craft of existing metal gate electrode, because the length of grid is less, the opening depth-to-width ratio of manufacturing grid is bigger, therefore, gate material is being deposited to comparatively difficulty of gate openings.The deposition rate at gate openings top place is always greater than the bottom, and causes the gate material of top blocked up, is easy to seal gate openings, and forms the cavity in the bottom (dotted line circle indicating area among Fig. 1).And above-mentioned cavity will influence the electrical property of gate electrode.Therefore be necessary to provide a kind of new metal gate electrode manufacture method, to avoid the problem in above-mentioned generation cavity.
Summary of the invention
The problem that the present invention solves provides a kind of manufacture method of metal gate electrode, has avoided in metal gate electrode, occurring the cavity.
For addressing the above problem, the invention provides a kind of manufacture method of metal gate electrode, comprising:
Semiconductor substrate is provided, forms dielectric layer, form pseudo-grid on the surface of said dielectric layer at said semiconductor substrate surface;
Adopt selective epitaxial process to form epitaxial loayer on pseudo-grid surface; Said epitaxial loayer forms the extension projection at pseudo-grid top place, and the side surface with flare;
Side surface at said epitaxial loayer forms insulative sidewall;
In the Semiconductor substrate of pseudo-grid both sides, carry out ion and inject formation source, drain electrode;
Surface at above-mentioned semiconductor structure forms interlayer dielectric layer, and the surface of the said interlayer dielectric layer of planarization, until the epitaxial loayer that exposes pseudo-grid top;
Remove the epitaxial loayer on said pseudo-grid and surface thereof, form gate openings;
Fill said gate openings and form metal gate electrode.
Optional, the material of said pseudo-grid is a polysilicon, grid length does
Highly do
Said selective epitaxial process comprises: utilize SiH
2Cl
2And H
2Mist generates elemental silicon in pseudo-grid surface reaction.The reaction condition of said selective epitaxial process comprises: the scope of environmental stress is 1Torr～80Torr, and temperature range is 700 ℃～900 ℃, feeds SiH
2Cl
2The scope of the gas flow of gas is 50sccm～150sccm, H
2The gas flow scope of gas is 100sccm～300sccm.The flare angle on said epitaxial layer side surface is 1 ° to 5 °.Said epitaxial loayer is
at the extension width at pseudo-grid top place
Optional, the material of said insulative sidewall can be silicon nitride, silica or its composite construction.Adopt the selectivity dry etching to remove the epitaxial loayer on pseudo-grid and surface thereof.
Optional, before filling said gate openings formation metal gate electrode, also be included in the gate openings bottom and form high K gate dielectric layer.Said high K gate dielectric layer comprises HfO
2, HFSiO, HfON, La
2O
3, LaAlO, Al
2O
3, ZrO
2, ZrSiO, TiO
2Or Y
2O
3Said high K gate dielectric layer adopts chemical vapor deposition or atom layer deposition process to form.The thickness of said high K gate dielectric layer is less than
Optional, the material of said metal gate electrode is TiN, Ti, TaN or Al, W.Said metal gate electrode adopts physical vapour deposition (PVD) to form.
Compared with prior art; The present invention has the following advantages: form the epitaxial loayer with flare side on pseudo-grid surface; Behind the epitaxial loayer on feasible pseudo-grid of removal and surface thereof, in interlayer dielectric layer, form the groove of opening greatly, effectively avoided filling to form the problem that metal gate electrode produces the cavity.
Description of drawings
Fig. 1 is the sketch map that existing metal gate electrode manufacture method produces cavity blemish.
Fig. 2 is the schematic flow sheet of metal gate electrode manufacture method of the present invention.
Fig. 3 to Figure 11 is the generalized section of metal gate electrode manufacture method of the present invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part, because the opening depth-to-width ratio of manufacturing grid is bigger, when existing metal gate electrode manufacture method is filled metal material formation gate electrode in said opening, occur the cavity easily, thereby influence the performance of gate electrode.
To the problems referred to above; Inventor of the present invention provides a kind of manufacture method of metal gate electrode; Be utilized in pseudo-grid surface and form epitaxial loayer with flare side; Make the gate openings of follow-up formation have bigger A/F at the top, its top transition is comparatively mild, can effectively improve the situation that occurs the cavity when in gate openings, filling metal material.
With reference to figure 2, show the flow process of the manufacture method of metal gate electrode of the present invention, basic step comprises:
Execution in step S101 provides Semiconductor substrate, forms dielectric layer at said semiconductor substrate surface, on dielectric layer, forms pseudo-grid then.Said dielectric layer can be protected Semiconductor substrate, can also be as gate dielectric layer, but thickness should be not blocked up in order to avoid influence and follow-uply Semiconductor substrate is carried out ion inject with formation source, drain electrode; Said pseudo-grid are used to form gate openings, and material can be polysilicon.
Execution in step S102 adopts selective epitaxial process to form epitaxial loayer on pseudo-grid surface; Said epitaxial loayer forms the extension projection at pseudo-grid top place, and the side surface with flare.Because Semiconductor substrate is covered by dielectric layer, therefore when carrying out the epitaxial growth of silicon, said epitaxial loayer only can optionally be formed at the surface of pseudo-grid.Common pseudo-grid top is easier to haptoreaction gas fully; And the extension speed at sharp-pointed place is very fast relatively; Therefore; Other parts are thicker relatively at the thickness at pseudo-grid top place for said epitaxial loayer, the side surface that can form the extension projection and have flare, and relating to parameters such as the height of flare angle and pseudo-grid, extension speed, time.Can adjust through selecting the concrete epitaxy technique parameter and the height of pseudo-grid.
Execution in step S103 is at the side surface formation insulative sidewall of said epitaxial loayer.Said insulative sidewall can be silicon nitride, silica or its composite construction, and has good tack with epitaxial loayer.
Execution in step S104 carries out ion and injects formation source, drain electrode in the Semiconductor substrate of pseudo-grid both sides.As the MOS device fabrication of routine, in the semiconductor substrate surface zone,, carry out the ion implantation technology of respective type respectively according to predefined MOS type of device.
Execution in step S105, at the surface coverage formation interlayer dielectric layer of above-mentioned semiconductor structure, and the surface of the said interlayer dielectric layer of planarization is until the epitaxial loayer that exposes pseudo-grid top.Said planarization can be adopted cmp, and with epitaxial loayer as stopping layer.
Execution in step S106, the epitaxial loayer of removing said pseudo-grid and surface thereof forms gate openings.Can select the corresponding technology of removing according to the material difference of pseudo-grid and epitaxial loayer and interlayer dielectric layer, for example adopt optionally dry etching.Remaining space in the interlayer dielectric layer behind pseudo-grid of removal and the surperficial epitaxial loayer thereof is just as gate openings, and dielectric layer will be exposed in the bottom of said gate openings.
Execution in step S107 fills said gate openings and forms metal gate electrode.Because gate openings is to obtain through the epitaxial loayer of removing pseudo-grid and surface thereof; And said epitaxial loayer forms the extension projection at pseudo-grid top place, and the side surface with flare, and therefore the top width of said gate openings is greater than bottom width; And its top transition is comparatively mild; When filling the formation metal gate electrode, deposition rate is comparatively even, can effectively improve the defective that produces the cavity.Usually after filling metal material, also should comprise the step that the metal material of gate openings is overflowed in the planarization removal.
In addition, as optional scheme, before filling metal material, can also be earlier in the bottom of gate openings, the surface deposition high-k dielectric material of dielectric layer is as the high K gate dielectric layer of metal gate electrode, to improve the performance of gate dielectric layer.
Set forth characteristic of the present invention and advantage below in conjunction with concrete embodiment, Fig. 3 to Figure 11 shows each production phase of an embodiment of metal gate electrode manufacture method of the present invention.
As shown in Figure 3, Semiconductor substrate 100 is provided, said Semiconductor substrate 100 can be monocrystalline substrate or silicon-on-insulator, definition has the zone that forms each MOS transistor on said Semiconductor substrate 100.And each MOS transistor is interregional isolates through the insulation of shallow trench isolation STI.Be simplified illustration, the embodiment of the invention is only with the examples shown that is made as of nmos pass transistor, and said Semiconductor substrate 100 is a P type substrate.Surface in said Semiconductor substrate 100 forms dielectric layer 101, and the material of said dielectric layer 101 can be silica, can protect Semiconductor substrate 100 on the one hand, on the other hand can also be as gate dielectric layer.But its thickness should be not blocked up, in order to avoid influence follow-up ion implantation technology of carrying out, and with formation source, drain electrode.
As shown in Figure 4, on dielectric layer 101, form pseudo-grid layer, its material can be polysilicon, deposit thickness has determined the height of pseudo-grid.The pseudo-grid layer of etched portions forms pseudo-grid 102 in the pre-position on dielectric layer 101 surfaces.In the present embodiment, the grid of said pseudo-grid 102 are long highly to be
for
As shown in Figure 5, adopt selective epitaxial process to form epitaxial loayer 103 on the surface of pseudo-grid 102.Said epitaxy technique can be: utilize SiH
2Cl
2And H
2Mist, reaction generates elemental silicon.Wherein, because Semiconductor substrate 100 surfaces have dielectric layer 101 protections, therefore above-mentioned reaction only can form elemental silicon on pseudo-grid 102 surfaces of polysilicon material, thereby realizes selective epitaxial growth.
Can know that according to aforementioned principles relative other parts of thickness are thicker at the top place of pseudo-grid 102 for said epitaxial loayer 103, the side surface that can form the extension projection and have flare.Wherein, the height of pseudo-grid 102, extension speed, time all can influence above-mentioned flare angle.Concrete, pseudo-grid 101 surfaces extension speed everywhere there are differences, and the extension speed ratio at top bottom is fast, then the reaction time long more, above-mentioned epitaxial loayer 103 is big more at the extension width at pseudo-grid 101 tops, the flare of side surface is also obvious more.
In the present embodiment, the reaction condition of said selective epitaxial process comprises: the scope of environmental stress is 1Torr～80Torr, and temperature range is 700 ℃～900 ℃, feeds SiH
2Cl
2The scope of the gas flow of gas is 50sccm～150sccm, H
2The gas flow scope of gas is 100sccm～300sccm.The scope of the flare angle [alpha] on said epitaxial layer side surface is 1 ° to 6 °.According to geometrical relationship; There is following relational expression w ≈ htg α in epitaxial loayer 103 at the extension width w at pseudo-grid 102 top places and the height h of pseudo-grid 101, and the scope of said extension width w is
As shown in Figure 6, form insulative sidewall 104 in the side of epitaxial loayer 103.The material of said insulative sidewall 104 can be silica, silicon nitride or its composite construction, has good tack with the epitaxial loayer of silicon material, can adopt conventional sidewall technology to form.
As shown in Figure 7, in the Semiconductor substrate 100 of pseudo-grid 102 both sides, carry out ion and inject formation source, drain electrode.Wherein, in respective regions, carry out the ion implantation technology of different doping types according to the type of MOS transistor.Concrete, make photoresist mask definition source, drain region earlier, in pseudo-grid 101 both sides, carry out N type ion then and inject, form source, the drain electrode of nmos pass transistor; Repeat above-mentioned steps again, carry out P type ion and inject, form the transistorized source of PMOS, drain electrode.
As shown in Figure 8, at semiconductor structure surface coverage shown in Figure 7 deposition interlayer dielectric layer 105, the surface of the said interlayer dielectric layer 105 of planarization then, its thickness of attenuate is until the epitaxial loayer 103 that exposes pseudo-grid 102 tops.In the present embodiment, the material of said interlayer dielectric layer 105 is chosen as silica or silicon nitride, adopts the said interlayer dielectric layer 105 of cmp attenuate, and stops layer with the epitaxial loayer at pseudo-grid 102 tops 103 as grinding.
As shown in Figure 9, the epitaxial loayer 103 of removing pseudo-grid 102 and surface thereof forms gate openings.
Concrete; Because the material of pseudo-grid 102 and epitaxial loayer 103 is elemental silicon described in the present embodiment; And the material of interlayer dielectric layer 105 is silica or silicon nitride, therefore can directly utilize interlayer dielectric layer 105 as hard mask, adopts optionally dry etching; Remove the epitaxial loayer 103 on pseudo-grid 102 and surface thereof, until exposing dielectric layer 101.
After the epitaxial loayer 103 on said pseudo-grid 102 and surface thereof is removed, just in interlayer dielectric layer 105, formed gate openings, the shape of said gate openings is the shape of the epitaxial loayer 103 on former pseudo-grid 102 and surface thereof.Because epitaxial loayer 103 forms the extension projection at pseudo-grid 101 top places, and the side surface with flare, therefore the top width of said gate openings is greater than bottom width, and the transition of open top edge is comparatively mild.
Shown in figure 10, as optional scheme, in the bottom of gate openings, the surface of dielectric layer 101 forms high K gate dielectric layer 106.Concrete, can adopt deposition process to form said high K gate dielectric layer 106, for example chemical vapor deposition or atom layer deposition process with better step covering power; Said high K gate dielectric layer 106 can comprise HfO
2, HFSiO, HfON, La
2O
3, LaAlO, Al
2O
3, ZrO
2, ZrSiO, TiO
2Or Y
2O
3The thickness of said high K gate dielectric layer 106 is less than 60 dusts, and preferred, the thickness of said high K gate dielectric layer 106 is 5 dust to 40 dusts.Above-mentioned high K gate dielectric layer 106 can improve the electrical property of dielectric layer.
Shown in figure 11, in said gate openings, fill metal material, form metal gate electrode 107.Said metal gate electrode 107 fills up gate openings.
Concrete, adopt physical vapor deposition process to form said metal gate electrode 107, can adopt TiN, Ti, TaN or metal materials such as Al, W.
Because the top width of said gate openings is greater than bottom width, and the transition of top place is comparatively mild, therefore when carrying out physical vapour deposition (PVD), everywhere deposition rate is comparatively even in the gate openings.The metal material of top place deposition can not cause the cavity in the bottom by the shutoff opening because thickness is blocked up,, thus the yield of metal gate electrode improved.
In addition, also need adopt the surface of the said interlayer dielectric layer 105 of chemical mechanical milling tech planarization, remove and to overflow the metal material of gate openings, make the top of said metal gate electrode 107 and the surperficial flush of interlayer dielectric layer 105.So far, metal gate electrode of the present invention just completes.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (14)
1. the manufacture method of a metal gate electrode is characterized in that, comprising:
Semiconductor substrate is provided, forms dielectric layer, form pseudo-grid on the surface of said dielectric layer at said semiconductor substrate surface;
Adopt selective epitaxial process to form epitaxial loayer on pseudo-grid surface; Said epitaxial loayer forms the extension projection at pseudo-grid top place, and the side surface with flare;
Side surface at said epitaxial loayer forms insulative sidewall;
In the Semiconductor substrate of pseudo-grid both sides, carry out ion and inject formation source, drain electrode;
Surface at above-mentioned semiconductor structure forms interlayer dielectric layer, and the surface of the said interlayer dielectric layer of planarization, until the epitaxial loayer that exposes pseudo-grid top;
The epitaxial loayer of removing said pseudo-grid and surface thereof forms gate openings;
Fill said gate openings and form metal gate electrode.
2. manufacture method as claimed in claim 1; It is characterized in that; The material of said pseudo-grid is a polysilicon, and grid are long highly to be
for
3. manufacture method as claimed in claim 2 is characterized in that said selective epitaxial process comprises: utilize SiH
2Cl
2And H
2Mist generates elemental silicon in pseudo-grid surface reaction.
4. manufacture method as claimed in claim 3 is characterized in that, the reaction condition of said selective epitaxial process comprises: the scope of environmental stress is 1Torr～80Torr, and temperature range is 700 ℃～900 ℃, feeds SiH
2Cl
2The scope of the gas flow of gas is 50sccm～150sccm, H
2The gas flow scope of gas is 100sccm～300sccm.
5. manufacture method as claimed in claim 2 is characterized in that, the flare angle on said epitaxial layer side surface is 1 ° to 5 °.
6. manufacture method as claimed in claim 5; It is characterized in that said epitaxial loayer is
at the extension width at pseudo-grid top place
7. manufacture method as claimed in claim 1 is characterized in that, the material of said insulative sidewall can be silicon nitride, silica or its composite construction.
8. manufacture method as claimed in claim 3 is characterized in that, adopts the selectivity dry etching to remove the epitaxial loayer on pseudo-grid and surface thereof.
9. manufacture method as claimed in claim 1 is characterized in that, before filling said gate openings formation metal gate electrode, also is included in the gate openings bottom and forms high K gate dielectric layer.
10. manufacture method as claimed in claim 9 is characterized in that, said high K gate dielectric layer comprises HfO
2, HFSiO, HfON, La
2O
3, LaAlO, Al
2O
3, ZrO
2, ZrSiO, TiO
2Or Y
2O
3
11. manufacture method as claimed in claim 10 is characterized in that, said high K gate dielectric layer adopts chemical vapor deposition or atom layer deposition process to form.
12. manufacture method as claimed in claim 10; It is characterized in that the thickness of said high K gate dielectric layer is less than
13. manufacture method as claimed in claim 1 is characterized in that, the material of said metal gate electrode is TiN, Ti, TaN or Al, W.
14. manufacture method as claimed in claim 13 is characterized in that, said metal gate electrode adopts physical vapour deposition (PVD) to form.
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|---|---|---|---|
| CN201010553697.7A CN102468151B (en) | 2010-11-19 | 2010-11-19 | Method for making metal gate electrode |
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|---|---|---|---|
| CN201010553697.7A CN102468151B (en) | 2010-11-19 | 2010-11-19 | Method for making metal gate electrode |
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| CN102468151B CN102468151B (en) | 2014-07-02 |
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ID=46071634
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531455A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02165639A (en) * | 1988-12-20 | 1990-06-26 | New Japan Radio Co Ltd | Manufacture of semiconductor element |
| JP2000031291A (en) * | 1998-07-13 | 2000-01-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
-
2010
- 2010-11-19 CN CN201010553697.7A patent/CN102468151B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02165639A (en) * | 1988-12-20 | 1990-06-26 | New Japan Radio Co Ltd | Manufacture of semiconductor element |
| JP2000031291A (en) * | 1998-07-13 | 2000-01-28 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103531455A (en) * | 2012-07-03 | 2014-01-22 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
| CN103531455B (en) * | 2012-07-03 | 2017-06-06 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
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|---|---|
| CN102468151B (en) | 2014-07-02 |
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