JPH0282523A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0282523A JPH0282523A JP63235512A JP23551288A JPH0282523A JP H0282523 A JPH0282523 A JP H0282523A JP 63235512 A JP63235512 A JP 63235512A JP 23551288 A JP23551288 A JP 23551288A JP H0282523 A JPH0282523 A JP H0282523A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist
- layer
- ion implantation
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 33
- 238000005468 ion implantation Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229920005591 polysilicon Polymers 0.000 abstract description 8
- 239000010408 film Substances 0.000 abstract 11
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 7
- 230000000903 blocking effect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に相補形電界
効果トランジスタ(以下CMO8と称する)の拡散層を
イオン注入法により形成する方法ににおいて、イオン注
入を阻止する膜に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming a diffusion layer of a complementary field effect transistor (hereinafter referred to as CMO8) by an ion implantation method. The present invention relates to a membrane that blocks ion implantation.
従来、この種の0MO8の2種類の導電型の拡散層をイ
オン注入法で形成する場合には、イオン注入しない領域
を第3図のように蒸着又はスパッタリングしたアルミ膜
によって履い、イオン注入阻止膜とするか、又は、第4
図のように、フォトレジスト膜によって履い、阻止膜と
するかのいずれかの製造方法であった。Conventionally, when forming this type of diffusion layer of two conductivity types (0MO8) by ion implantation, the region where ions are not implanted is covered with a vapor-deposited or sputtered aluminum film as shown in Figure 3, and an ion implantation blocking film is used. or the fourth
As shown in the figure, one of the manufacturing methods was to use a photoresist film as a blocking film.
上述した従来の製造方法においては、以下に述べるよう
な欠点がある。まず、第3図の述く、ゲート電極となる
ポリシリコンをフォトレジスト工程、エツチング工程を
通して、バターニング後に、ポリシリコン膜表面に数百
人の薄い酸化膜を熱酸化でつけ、その後に、蒸着又はス
パッタリングによりアルミ膜を基板表面全面につけて、
不純物イオン注入(この場合は7″As”)を行ないた
い部分のアルミ膜をフォトレジスト工程、エツチング工
程を行なって除去し、不純物イオン注入を行ないたくな
い部分にアルミ膜を残す。(第3図)このとき、ゲート
ポリシリコンは4000〜6000人の厚さがあり、そ
の側面は切立っている。このような段差があると、現在
のアルミ成膜方法(蒸着又はスパッタリング)ではその
段差部のカバレッヂが悪くなり、部分的に非常にアルミ
が薄くなってしまう事がある。条件が悪くなると、はと
んどアルミがなく 、” A s+の重い原子のイオン
注入でも阻止できず、イオン注入したくない部分に22
N+拡散層ができてしまうという欠点がある。The conventional manufacturing method described above has the following drawbacks. First, as shown in Figure 3, the polysilicon that will become the gate electrode is subjected to a photoresist process and an etching process, and after buttering, several hundred thin oxide films are applied to the surface of the polysilicon film by thermal oxidation, and then vapor deposition is performed. Or, by applying an aluminum film to the entire surface of the substrate by sputtering,
A photoresist process and an etching process are performed to remove the aluminum film in the portion where impurity ion implantation (in this case, 7"As") is to be performed, and the aluminum film is left in the portion where impurity ion implantation is not desired. (FIG. 3) At this time, the gate polysilicon has a thickness of 4000 to 6000 mm, and its sides are steep. When such a step exists, current aluminum film forming methods (evaporation or sputtering) have poor coverage of the step, and the aluminum may become extremely thin in some areas. When the conditions worsen, there is almost no aluminum, and even the ion implantation of heavy A s+ atoms cannot be prevented, and 22
There is a drawback that an N+ diffusion layer is formed.
又、もう一つの従来技術としては、第4図に示すように
、23フオトレジストを、イオン注入したくない領域に
残す方法がある。この場合には、イオン注入したフォト
レジスト膜がそのイオン注入不純物の種類(例えば、”
As”)によっては、イオン注入後の剥離性が悪いとい
う欠点があった。Another conventional technique, as shown in FIG. 4, is a method in which 23 photoresist is left in areas where ions are not desired to be implanted. In this case, the type of ion implanted impurity (for example, "
Depending on the type of As''), there is a drawback that the peelability after ion implantation is poor.
〔課題を解決するための手段〕
本発明の半導体装置の製造方法は、0MO3の2つの導
電型の不純物のイオン注入により、P+N+の2つの拡
散層を形成する製造方法において、拡散層形成の為のイ
オン注入の少なくともどちらか片方で、イオン注入した
くない領域を履うフォトレジスト膜を下層にしアルミニ
ウム膜を上層とした2重膜を有している。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention is a method for forming two diffusion layers of P+N+ by ion implantation of impurities of two conductivity types of 0MO3. For at least one of the ion implantations, the double film has a photoresist film as a lower layer and an aluminum film as an upper layer, covering the region where ions are not desired to be implanted.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図(a)〜(c)は本発明の一実施例の縦断面図で
ある゛。FIGS. 1(a) to 1(c) are longitudinal cross-sectional views of one embodiment of the present invention.
第1図(a)は、P−基板5にNウェル3を形成し、選
択酸化によって厚い酸化膜部分4を形成後、4000〜
6000人の厚さのポリシリコン層を形成してフォトレ
ジスト工程、エツチング工程を通して、ゲート電極及び
配線となるポリシリコン部分6をバターニングし、熱酸
化で薄い酸化膜を形成後に、ポジ・フォトレジスト膜2
を1.5〜2.0μの厚さに塗布し、その後に0.5〜
1.1μの厚さのアルミニウム膜1を形成した直後の縦
断面図である。このように、フォトレジスト層(ポジ)
2を下層にする事で、フォトレジストの表面は、はとん
ど平坦に近い状態になり、下地の凹凸に左右されない状
態となっている。従って、フォトレジスト2の上層にア
ルミ層1を形成してもアルミ層はほぼ一様の厚さにする
事ができる。その後、第1図(b)に示すように、アル
ミ層1の上層にフォトレジスト(ポジ)7を塗布して、
イオン注入したい領域を露光して、現像し、フォトレジ
ストを除去する。しかる後に、第1図(c)に示す述く
、フォトレジスト7をマスクとしてアルミ膜1をエツチ
ングし、その後に全面露光して現像するか、もしくは、
プラズマ処理して、フォトレジスト膜7とイオン注入し
たい領域のフォトレジスト膜2をアルミ膜lをマスクと
して除去し、残ったアルミ膜lとフォトレジスト膜2と
の2重膜を例えば”As+をイオン注入する際の阻止膜
とする。イオン注入は一様の厚さのアルミ膜1で阻止す
る為に、フォトレジスト膜2にはイオン注入されず、ア
ルミ膜1及びフォトレジスト膜2の剥離性も十分で問題
なく、イオン注入の阻止性と剥離性の双方が両立する。In FIG. 1(a), an N-well 3 is formed on a P-substrate 5, and a thick oxide film portion 4 is formed by selective oxidation.
A polysilicon layer with a thickness of 6,000 nm is formed, a photoresist process and an etching process are performed, the polysilicon part 6 that will become the gate electrode and wiring is buttered, a thin oxide film is formed by thermal oxidation, and then a positive photoresist is formed. membrane 2
Apply to a thickness of 1.5 to 2.0μ, then apply 0.5 to 2.0μ thick.
FIG. 2 is a longitudinal cross-sectional view immediately after forming an aluminum film 1 with a thickness of 1.1 μm. In this way, the photoresist layer (positive)
By using No. 2 as the lower layer, the surface of the photoresist becomes nearly flat, and is not affected by the unevenness of the underlying layer. Therefore, even if the aluminum layer 1 is formed on the photoresist 2, the aluminum layer can have a substantially uniform thickness. Thereafter, as shown in FIG. 1(b), a photoresist (positive) 7 is applied to the upper layer of the aluminum layer 1.
The area desired for ion implantation is exposed, developed, and the photoresist is removed. Thereafter, as shown in FIG. 1(c), the aluminum film 1 is etched using the photoresist 7 as a mask, and then the entire surface is exposed and developed, or
Plasma treatment is performed to remove the photoresist film 7 and the photoresist film 2 in the area where ions are to be implanted using the aluminum film 1 as a mask, and the remaining double film of the aluminum film 1 and the photoresist film 2 is ionized with, for example, As+. Used as a blocking film during implantation.Since ion implantation is blocked by the aluminum film 1 with a uniform thickness, ions are not implanted into the photoresist film 2, and the peelability of the aluminum film 1 and photoresist film 2 is also reduced. It is sufficient and there is no problem, and both the ion implantation blocking property and the peeling property are compatible.
第2図(a)〜(c)は、本発明の他の実施例の縦断面
図である。この場合には、まず、フォトレジスト(ポジ
)11を塗布した後にフォトレジスト(ネガ)10を、
その上層に塗布する(第2図(a))。その後に、イオ
ン注入したい領域を露光して現像し、フォトレジスト(
ネガ)10を所定の領域だけ残し、その後にアルミ膜1
2を蒸着又はスパッタリングによって、形成し、(第2
図(b))リフト・オフ法によって、残っていたフォト
レジスト(ネガ)10と、その上層にあるアルミ膜のみ
をひきはがし、その後に、全面露光して、現像する事に
より、アルミ膜12の残っていない領域のフォトレジス
ト(ポジ)11を除去し、(第3図(C))、その後に
所定の不純物をイオン注入する(例えば”A s ”)
。この場合も、下地の凹凸に左右されず平坦となったフ
ォトレジスト(ポジ)膜11の上にアルミ膜12を形成
している為にアルミ膜12は一様の厚さとなっており、
イオン注入を阻止し、阻止性と後の剥離性の両方を確保
している。FIGS. 2(a) to 2(c) are longitudinal cross-sectional views of other embodiments of the present invention. In this case, first, photoresist (positive) 11 is applied, and then photoresist (negative) 10 is applied.
The upper layer is coated (FIG. 2(a)). After that, the area where you want to implant ions is exposed and developed, and the photoresist (
Negative) 10 is left only in a predetermined area, and then aluminum film 1 is applied.
2 by vapor deposition or sputtering, (second
Figure (b)) By using the lift-off method, only the remaining photoresist (negative) 10 and the aluminum film on top of it are peeled off, and then the entire surface is exposed and developed to remove the aluminum film 12. The photoresist (positive) 11 in the remaining area is removed (FIG. 3(C)), and then a predetermined impurity is ion-implanted (for example, "A s ").
. In this case as well, since the aluminum film 12 is formed on the photoresist (positive) film 11 which is flat regardless of the unevenness of the base, the aluminum film 12 has a uniform thickness.
It blocks ion implantation and ensures both blocking properties and later peelability.
以上説明したように、本発明は、0MO8の2つの導電
型の不純物のイオン注入により、P+N+の2つの拡散
層を形成する製造方法において、拡散層形成の為のイオ
ン注入時に、イオン注入したくない領域を、下層をフォ
トレジスト膜、上層をアルミ膜とする2重膜とする事に
より、フォトレジスト膜によって下地の凹凸によらず、
その表面を平坦にし、段差部におけるアルミ膜の膜厚バ
ラツキをなくして、イオン注入時の阻止能力をアルミ膜
で十分に確保し、且つ、イオン注入後の剥離性も下層の
フォトレジスト膜はイオン注入されているので、十分確
保する事ができるという効果がある。As explained above, the present invention provides a manufacturing method for forming two diffusion layers of P+N+ by ion implantation of two conductivity type impurities of 0MO8. By using a double film with a photoresist film on the bottom layer and an aluminum film on the top layer, the photoresist film can be used to cover areas where there is no surface area, regardless of the unevenness of the underlying surface.
By flattening the surface and eliminating variations in the thickness of the aluminum film at the stepped portions, the aluminum film has sufficient blocking ability during ion implantation. Since it is injected, it has the effect of being able to secure a sufficient amount.
遣方法の一実施例の縦断面図、第2図(a)〜(c)は
、本発明の他の実施例の縦断面図、第3図は従来の製造
方法の一例で、アルミ膜を使用した場合の縦断面図、第
4図は同じ〈従来の製造方法の一例でフォトレジスト膜
を使用した場合の縦断面図である。2(a) to (c) are longitudinal sectional views of another embodiment of the present invention, and FIG. 3 is an example of a conventional manufacturing method, in which an aluminum film is FIG. 4 is a vertical cross-sectional view of the case in which a photoresist film is used in an example of the conventional manufacturing method.
1.12.20・・・・・・アルミ、2,7,11,2
3・・・・・・フォトレジスト(ポジ)、3,13・・
・・・・Nウェル、4,16・・・・・・厚い酸化膜、
5,15・川・・P−基板、6,14・・・・・・ポリ
シリコン、8.17・・団・薄い酸化膜、9,18,2
1,25・・川・N+拡散層、24・・・・・・変質し
たフォトレジスト。1.12.20...aluminum, 2,7,11,2
3...Photoresist (positive), 3,13...
...N well, 4,16... Thick oxide film,
5,15...P-substrate, 6,14...Polysilicon, 8.17...Group-thin oxide film, 9,18,2
1, 25... River/N+ diffusion layer, 24... Altered photoresist.
代理人 弁理士 内 原 晋Agent: Patent Attorney Susumu Uchihara
第1図(a)〜(c)は、本発明の半導体装置の製第2
図(b)
第1図CC)
第2図(すFIGS. 1(a) to 1(c) show the manufacturing process of the semiconductor device of the present invention.
Figure (b) Figure 1 CC) Figure 2 (S
Claims (1)
である第2の導電型の島状領域を形成し、それぞれの導
電型の不純物のイオン注入により、前記島状領域に第1
の導電型の拡散層を形成し、且つ前記基板上には第2の
導電型の拡散層を形成する半導体装置の製造方法におい
て、前記二つの導電型の拡散層を形成する為のイオン注
入時の少なくとも一方において、イオン注入したくない
領域を、フォトレジスト膜を下層にしたアルミニウム膜
を上層とした2重膜で履う事を特徴とする半導体装置の
製造方法。An island-like region of a second conductivity type, which is an opposite conductivity type to the first conductivity type, is formed on a substrate of a first conductivity type, and the island-like region is 1st to
In the method for manufacturing a semiconductor device, in which a diffusion layer of a conductivity type is formed and a diffusion layer of a second conductivity type is formed on the substrate, during ion implantation to form the diffusion layers of the two conductivity types. 1. A method for manufacturing a semiconductor device, characterized in that in at least one of the steps, a region where ion implantation is not desired is covered with a double film having a photoresist film as a lower layer and an aluminum film as an upper layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63235512A JPH0282523A (en) | 1988-09-19 | 1988-09-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63235512A JPH0282523A (en) | 1988-09-19 | 1988-09-19 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0282523A true JPH0282523A (en) | 1990-03-23 |
Family
ID=16987088
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63235512A Pending JPH0282523A (en) | 1988-09-19 | 1988-09-19 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0282523A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04176119A (en) * | 1990-11-08 | 1992-06-23 | Nec Yamagata Ltd | Manufacture of semiconductor device and ion implantation mask material therefor |
-
1988
- 1988-09-19 JP JP63235512A patent/JPH0282523A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04176119A (en) * | 1990-11-08 | 1992-06-23 | Nec Yamagata Ltd | Manufacture of semiconductor device and ion implantation mask material therefor |
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