JPS61116833A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61116833A
JPS61116833A JP23893384A JP23893384A JPS61116833A JP S61116833 A JPS61116833 A JP S61116833A JP 23893384 A JP23893384 A JP 23893384A JP 23893384 A JP23893384 A JP 23893384A JP S61116833 A JPS61116833 A JP S61116833A
Authority
JP
Japan
Prior art keywords
film
resist
ion implantation
metal film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23893384A
Other languages
Japanese (ja)
Inventor
Mitsutaka Morimoto
光孝 森本
Eiji Nagasawa
長澤 英二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23893384A priority Critical patent/JPS61116833A/en
Publication of JPS61116833A publication Critical patent/JPS61116833A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation

Abstract

PURPOSE:To obtain a mask just suitable for high concentration ion implantation by laminating metal films having sufficient ion implantation rejecting performance on unexposed positive photo resist. CONSTITUTION:An oxide separation film 102, a gate oxide film 103, an Mo gate electrode 104 are provided on an Si substrate and the surface is then rotatably coated with a positive photoresist 105 and is then baked. Next, Mo 106 is deposited under the condition that the resist 105 is not sensed in such a thickness that implanted ion almost stays within the Mo film. Next, with the positive photo resist 107 used as the mask, Mo is easily etched using reduced H2O2 solution without giving any influence on the base resist 105. Any damage is not given to Mo 104 even after the exposure and development. After forming high concentration ion implantation layer 108, the resist 105 is removed by dissolving it and then Mo is lifted off. The resist 105 is covered with Mo and it does not change in property and can easily be exfoliated with an ordinary organic solvent.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、更に詳しくは高
濃度イオン注入マスクの製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high concentration ion implantation mask.

〔従来の技術〕[Conventional technology]

イオン注入法は従来の熱拡散法に代わって半導体装置製
造工程における不純物導入法として主流になシつつある
。VLS Iを構成する基本素子であるMO8電界効果
トランジスタ(以下、MOSFETと略す)のソースあ
るいはドレイン電極等の高濃度の不純物層形成に用いる
場合はその代表例である。中でも低消費電力特性で最近
急速に利用範囲を拡大している。
Ion implantation is becoming a mainstream method for introducing impurities in semiconductor device manufacturing processes, replacing the conventional thermal diffusion method. A typical example is when it is used to form a highly concentrated impurity layer such as a source or drain electrode of an MO8 field effect transistor (hereinafter abbreviated as MOSFET), which is a basic element constituting a VLSI. Among them, the range of use has been rapidly expanding recently due to its low power consumption characteristics.

相補量MO8(以下、0MO8と略す) FETのソー
ス・ドレイン形成にイオン注入を用いる場合は、Nチャ
ネル型、Pチャネル型の2種類のMOSFETについて
各々導電型の異なる2種類の不純物を別途に注入する必
要が生ずる。このことは2回の高濃度イオン注入時には
、NチャネルとPチャネルとを区別するための注入マス
クが必要なことを意味する。
Complementary amount MO8 (hereinafter abbreviated as 0MO8) When using ion implantation to form the source and drain of an FET, two types of impurities with different conductivity types are separately implanted for two types of MOSFETs, N-channel type and P-channel type. The need arises. This means that an implantation mask is required to distinguish between N-channel and P-channel when performing two high-concentration ion implantations.

イオン注入のマスクとして最も簡便々のはイオン注入し
ようとする位置に開孔を設けたホトレジスト膜をそのま
ま利用することである。しかしながう、MOSFETの
ソース・ドレイン形成には少くとも1015イオン/C
m2程度以上の高ドース′量が通常必要であシ、この様
な場合、ホトレジスト表面層では過度のイオン衝撃によ
シ軽い水素原子等が弾き出されて炭素原子や注入された
原子等重い原子が残ったと考えられる変質層が形成され
る。この様な変質したホトレジスト膜は通常の露光現像
工程を経たホトレジスト膜とは異なシ一般的な有機溶剤
による方法では全く剥離できない。現在、変質したホト
レジスト膜の剥離には強酸中での煮沸処理や長時間の酸
素プラズマ処理、あるいはそれらの組み合わせが一般的
に用いられている。これらの剥離方法は従来の多結晶シ
リコンをダート電極とする場合には比較的問題の少ない
ものであった0〔発明が解決しようとする問題点〕 しかし、昨今のf−ト電極等の低抵抗化の動きに従って
高融点金属をf−)電極材料として導入)   しよう
とすると次の様な問題が発生する。すなわち、強酸中で
の煮沸処理では高融点金属が変形・変質あるいは溶解し
てしまう可能性がある。また酸素プラズマ処理では高融
点金属が酸化されたシ、MOS %性に影響を与えるダ
メージ導入の可能性がある。
The simplest way to use a mask for ion implantation is to use a photoresist film with openings formed at the positions where ions are to be implanted. However, for long MOSFET source/drain formation, at least 1015 ions/C
A high dose of approximately m2 or more is usually required, and in such cases, light hydrogen atoms, etc., are ejected from the photoresist surface layer due to excessive ion bombardment, and heavy atoms, such as carbon atoms and implanted atoms, are An altered layer that is thought to remain is formed. Unlike a photoresist film that has undergone a normal exposure and development process, such a photoresist film cannot be removed at all by a method using a common organic solvent. Currently, boiling treatment in a strong acid, long-term oxygen plasma treatment, or a combination thereof is generally used to peel off a photoresist film that has deteriorated in quality. These peeling methods have relatively few problems when conventional polycrystalline silicon is used as dart electrodes (problems to be solved by the invention). If high-melting point metals are introduced as f-) electrode materials in accordance with the trend of That is, when boiling in a strong acid, there is a possibility that the high melting point metal will be deformed, altered, or dissolved. In addition, in the oxygen plasma treatment, there is a possibility that the high melting point metal is oxidized, which may cause damage that affects the MOS ratio.

本発明の目的は高濃度イオン注入時のマスクとして満た
すべき特性、すなわち形成並びに剥離が容易で、かつ剥
離時に下地膜(特に金属膜)に損傷を与えることがなく
、注入時には十分な注入阻止能を有する高濃度イオン注
入マスクの製造方法を提供することKある。
The purpose of the present invention is to meet the characteristics required for a mask for high-concentration ion implantation, that is, to be easy to form and peel off, not to damage the base film (particularly metal film) during peeling, and to have sufficient implantation blocking ability during implantation. An object of the present invention is to provide a method for manufacturing a high concentration ion implantation mask having the following steps.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、半導体基板表面にボッ型ホトレジスト膜を塗
布する工程と、該レソスト膜が感光しない雰囲気におい
て該レソスト膜上に後に実施されるイオン注入条件では
イオンが殆ど貫通しない膜厚の金属膜を被着する工程と
、該金属膜の任意の領域をホトレジスト工程と金属膜エ
ッチングにより除去する工程と、当該金属膜をマスクと
する露光・現像工程によ)前記ボッ型ホトレジスト膜の
うち前記金属膜のエッチングにより除去された領域下を
選択的に除去する工程とを行うことを特徴とする半導体
装置の製造方法である。
The present invention involves a step of applying a bottom-type photoresist film on the surface of a semiconductor substrate, and a metal film having a thickness that hardly allows ions to penetrate under ion implantation conditions that are performed later on the resist film in an atmosphere where the resist film is not exposed to light. (a step of depositing the metal film, a step of removing an arbitrary region of the metal film by a photoresist step and a metal film etching step, and an exposure/development step using the metal film as a mask) This method of manufacturing a semiconductor device is characterized by performing a step of selectively removing a region below a region removed by etching.

〔実施例〕〔Example〕

以下に、本発明の実施例について図面を参照して詳細に
説明する。第1図は本発明の1実施例を工程順に示す断
面図である。jg1図(&)において、シリコン基板1
01に素子間分離のための厚いシリコン酸化膜102を
形成したのち、ダート絶縁膜103を被着し更にゲート
電極となるモリブデン等の高融点金属膜104を成形し
たものに、ポジ型ホトレノスト膜105を回転塗布し溶
媒を除去するためのベーキングを行った後、当該ポジ型
ホトレジスト膜を感光させることが無い蒸着条件で、例
えばモリブデンやチタン等の金属膜106を被着する0
なお、金属膜厚は高濃度イオン注入の加速電圧、ドーズ
量に従って変わるもので、注入イオンが殆ど当該金属膜
内に留まる様に選ぶ。また蒸着方法もポジ型ホトレジス
ト膜が感光することが無ければス・母ツタ法、電子ビー
ム法、抵抗加熱法等のいずれを用いても榊わない。次に
@1図(b)において、第2のホトレノスト膜107を
塗布し、後に高濃度イオン注入を施す領域に開孔を設け
lこのち当該第2のレジス) M 107をマスクに金
属膜106をエツチングする。金属エツチングはモリブ
デンの場合には冷遇酸化水素系のもの、チタンの場合は
希フッ酸を用いて、それぞれ容易にしかも下地のポジ型
ホトレジス) g 105に全く影響を与えず実施でき
る。第1図(、)は全面富士現像を行って前記金属膜1
06の開孔下のボッ型ホトレジスト膜105を除去した
状態を示す。この時前記第2のホトレジス) M 10
7をysy型に選んでおけば、金属J[106上に残留
していた第2のホトレノスト膜107も同時に除去され
る。この工程は通常の露光・現像工程であり下地の高融
点金属104には何の損傷も与えない。第1図(d)に
おいて、ソース・ドレイン電極形成のため高濃度の不純
物層108をイオン注入で形去る。ポジ型ホトレジスト
膜は金属膜で被覆された状態で高濃度イオン注入を行な
うので全く変質せず一般的な有機溶剤で容易に剥離可能
である。
Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a sectional view showing one embodiment of the present invention in the order of steps. In the jg1 diagram (&), silicon substrate 1
After forming a thick silicon oxide film 102 for isolation between elements on 01, a dirt insulating film 103 is deposited, and a high melting point metal film 104 such as molybdenum, which will become a gate electrode, is formed, and then a positive photorenost film 105 is formed. After spin coating and baking to remove the solvent, a metal film 106 of molybdenum, titanium, etc. is deposited under vapor deposition conditions that do not expose the positive photoresist film to light.
The thickness of the metal film varies depending on the acceleration voltage and dose of high-concentration ion implantation, and is selected so that most of the implanted ions remain within the metal film. Further, as for the vapor deposition method, if the positive type photoresist film is not exposed to light, it will not be possible to use any of the vapor deposition methods, such as the starburst method, the electron beam method, and the resistance heating method. Next, in Figure 1 (b), a second photorenost film 107 is applied, and an opening is formed in the region where high concentration ions will be implanted later. etching. Metal etching can be easily carried out using cold hydrogen oxide based etching for molybdenum and dilute hydrofluoric acid for titanium without affecting the underlying positive photoresist at all. Figure 1 (,) shows the metal film 1 after the entire surface was subjected to Fuji development.
This figure shows the state in which the bottom-shaped photoresist film 105 under the opening 06 has been removed. At this time, the second photoresist) M 10
If 7 is selected as the ysy type, the second photorenost film 107 remaining on the metal J[106 is also removed at the same time. This process is a normal exposure and development process and does not cause any damage to the underlying high melting point metal 104. In FIG. 1(d), the highly concentrated impurity layer 108 is removed by ion implantation to form source and drain electrodes. Since the positive type photoresist film is covered with a metal film and is implanted with high concentration ions, it does not change in quality at all and can be easily peeled off with a general organic solvent.

〔発明の効果〕〔Effect of the invention〕

以上、実施例の記述からも明らかな様に、本発明では未
露光のポジ型ホトレノスト上に十分なイオン注入阻止能
を持つ金属膜を重ねてこれを注入マスクとするのでホト
レゾスト単層の場合と異なシ高濃度イオン注入時のイオ
ン衝撃によるホトレジスト層の変質に伴なうレジスト剥
離に関する問題を回避できる。また、この2層構造を持
つ注入マスクにパターン形成する工程は通常の露光・現
像並びに有機溶剤によるレノスト剥離工程であシ、下地
に存在する金属膜等の性状に何ら悪影響を及ぼすことな
く行うことができる。
As is clear from the description of the examples above, in the present invention, a metal film having sufficient ion implantation blocking ability is layered on unexposed positive photoresist and this is used as an implantation mask, so it is different from the case of a single layer of photoresist. It is possible to avoid the problem of resist peeling caused by deterioration of the photoresist layer due to ion bombardment during high-concentration ion implantation. In addition, the process of forming a pattern on the injection mask having a two-layer structure can be carried out using normal exposure, development, and rennost peeling processes using an organic solvent, and can be performed without any adverse effect on the properties of the underlying metal film, etc. I can do it.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(、)〜(d)は本発明による製造工程を工程順
に示す断頁図である。 101・・・シリコン基板、102・・・シリコン酸化
膜、103・・・r−)絶縁膜、104・・・ダート金
属、105・・・タ  ポジ型ホトレジスト、106・
・・金属膜、107・・・ホトレジスト、108・・・
不純物層。 第1図
FIGS. 1(a) to (d) are cross-sectional views showing the manufacturing process according to the present invention in order of process. 101...Silicon substrate, 102...Silicon oxide film, 103...r-) insulating film, 104...Dart metal, 105...Taposi type photoresist, 106...
...Metal film, 107...Photoresist, 108...
impurity layer. Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板表面にポジ型ホトレジスト膜を塗布す
る工程と、該レジスト膜が感光しない雰囲気において該
レジスト膜上に後に実施されるイオン注入条件ではイオ
ンが殆ど貫通しない膜厚の金属膜を被着する工程と、該
金属膜の任意の領域をホトレジスト工程と金属膜エッチ
ングにより除去する工程と、当該金属膜をマスクとする
露光現像工程により前記ポジ型ホトレジスト膜のうち前
記金属膜のエッチングにより除去された領域下を選択的
に除去する工程とを行うことを特徴とする半導体装置の
製造方法。
(1) The step of coating a positive photoresist film on the surface of a semiconductor substrate, and the subsequent ion implantation on the resist film in an atmosphere where the resist film is not exposed to light, are coated with a metal film having a thickness that hardly allows ions to penetrate. a step of removing an arbitrary region of the metal film by a photoresist process and a metal film etching process; and a process of etching and removing the metal film of the positive photoresist film by an exposure and development process using the metal film as a mask. 1. A method for manufacturing a semiconductor device, comprising: selectively removing a portion under the removed region.
JP23893384A 1984-11-13 1984-11-13 Manufacture of semiconductor device Pending JPS61116833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23893384A JPS61116833A (en) 1984-11-13 1984-11-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23893384A JPS61116833A (en) 1984-11-13 1984-11-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61116833A true JPS61116833A (en) 1986-06-04

Family

ID=17037433

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23893384A Pending JPS61116833A (en) 1984-11-13 1984-11-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61116833A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0649198A1 (en) * 1993-10-18 1995-04-19 Koninklijke Philips Electronics N.V. Method of manufacturing a radiation-emitting semiconductor diode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0649198A1 (en) * 1993-10-18 1995-04-19 Koninklijke Philips Electronics N.V. Method of manufacturing a radiation-emitting semiconductor diode
BE1007661A3 (en) * 1993-10-18 1995-09-05 Philips Electronics Nv A method of manufacturing a radiation-emitting semiconductor diode.
US5541139A (en) * 1993-10-18 1996-07-30 U.S. Philips Corporation Method of manufacturing a radiation-emitting semiconductor diode

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