JPS63312632A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63312632A JPS63312632A JP62149342A JP14934287A JPS63312632A JP S63312632 A JPS63312632 A JP S63312632A JP 62149342 A JP62149342 A JP 62149342A JP 14934287 A JP14934287 A JP 14934287A JP S63312632 A JPS63312632 A JP S63312632A
- Authority
- JP
- Japan
- Prior art keywords
- film
- resist
- mask
- ion
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 2
- 150000002500 ions Chemical class 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 10
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000000206 photolithography Methods 0.000 abstract description 3
- 238000001039 wet etching Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 230000001681 protective effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 238000002513 implantation Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000001947 vapour-phase growth Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に関し、特に、イオン
注入方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an ion implantation method.
半導体基板中へ不純物を導入するためには、多くの場合
、イオン注入技術が用いられている。ボロン（Ｂ）やリ
ン（ト）等の特定元素を導入する場所を制限するために
は、基板表面にレジストを塗布した後、リングラフイー
技術を用いて必要なレジストは残し、不要なレジストは
除去する。Ion implantation technology is often used to introduce impurities into semiconductor substrates. In order to limit the locations where specific elements such as boron (B) and phosphorus (T) are introduced, after applying resist to the substrate surface, use phosphor-free technology to leave the necessary resist and remove unnecessary resist. Remove.
従来の技術では、残されたレジストをイオン注入のマス
クとして用い、レジストの残っていない場所だけに所望
の不純物を導入する場合がある。In conventional techniques, the remaining resist is sometimes used as a mask for ion implantation, and desired impurities are introduced only into areas where the resist does not remain.
上述した従来のイオン注入方法では、レジストを選択的
不純物導入のマスクとして用いているが、注入エネルギ
ービーム電流値、注入元素等の注入条件によっては、注
入中に基板の温度が上昇してしまい、高分子化合物であ
るレジストの耐熱性の限界を越え、その結果レジストの
パターン形状が変化したり、あるいはレジストが変質す
る事にょって、イオン注入後にレジストを除去できなく
なる、という問題がある。In the conventional ion implantation method described above, a resist is used as a mask for selective impurity introduction, but depending on the implantation conditions such as the implantation energy beam current value and the implanted element, the temperature of the substrate may rise during implantation. There is a problem in that the heat resistance limit of the resist, which is a polymer compound, is exceeded, and as a result, the pattern shape of the resist changes or the resist deteriorates, making it impossible to remove the resist after ion implantation.
本発明によれば、半導体基板の一主面に第１の無機膜を
形成する工程と、この第１の無機膜とはエッチフグ耐性
の異なる第２の無機膜を第１の無機ご上に選択的に形成
する工程と、その後この第２の無ｅ、膜をマスクとして
、半導体基板にイオン注入する工程とを有する半導体装
置の製造方法が得られる。According to the present invention, a step of forming a first inorganic film on one main surface of a semiconductor substrate, and selecting a second inorganic film having different etch resistance from the first inorganic film over the first inorganic film. A method for manufacturing a semiconductor device is obtained, which includes a step of forming a semiconductor substrate, and then a step of implanting ions into a semiconductor substrate using the second ion-free film as a mask.
この第１の無機膜は、厚さ５００Ａ程度の多結晶シリコ
ン膜、非晶質シリコン膜又は窒化けい素膜でおり、第２
の無機膜はイオン注入時に注入されるイオンを阻止する
のに充分な厚さを有する二液化けい素膜である。This first inorganic film is a polycrystalline silicon film, amorphous silicon film, or silicon nitride film with a thickness of about 500A, and the second
The inorganic film is a two-component silicon film having a thickness sufficient to block the ions implanted during ion implantation.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は、本発明の一実施例の縦断面図である。FIG. 1 is a longitudinal sectional view of an embodiment of the present invention.
以下、工程順に説明する。The steps will be explained below in order.
ｎ型シリコン基板１０１の表面に、素子分離領域１０２
とゲート酸化膜１０３を形成する。（第１図（ａ））。An element isolation region 102 is formed on the surface of the n-type silicon substrate 101.
Then, a gate oxide film 103 is formed. (Figure 1(a)).
次に、基板異面全体に厚さ２００Ａ程度の多結晶シリコ
ン膜１０４を気相成長法で形成し、その上に厚さ１μ程
度ノ酸化膜（ＣＶＩ）−８ｉｏｚ ）１０５を、気相成
長法で形成した後、フォトリソグラフィーに用いるレジ
スト１０６を塗布し、適切な熱処理を施す。（第１図（
ｂ））。Next, a polycrystalline silicon film 104 with a thickness of about 200 A is formed on the entire different surface of the substrate by a vapor phase growth method, and on top of that a polycrystalline silicon film 104 with a thickness of about 1 μm (CVI-8ioz) 105 is formed by a vapor phase growth method. After forming, a resist 106 used for photolithography is applied and an appropriate heat treatment is performed. (Figure 1 (
b)).
次に、フォトリングラフイーによりて、不要な箇所のレ
ジストを除去する。（第１図（Ｃ））。Next, unnecessary portions of the resist are removed using photolithography. (Figure 1 (C)).
次に、残されたレジスト１０６ ｔ−マスクに用いて、
このレジスト１０６下部以外の１６出している酸化膜１
０５を、反応性イオンエツチング１０７によって加工す
る。多結晶シリコン膜１０４は、この工程における表面
保護膜になる（第１図（ｄ））。Next, using the remaining resist 106 t-mask,
Oxide film 1 that is exposed at 16 areas other than the bottom of this resist 106
05 is processed by reactive ion etching 107. The polycrystalline silicon film 104 becomes a surface protection film in this step (FIG. 1(d)).
次に、レジスト１０６を除去した後、酸化膜１０５をマ
スクとして、ボロンなどの所望のイオン注入を行う（第
１図（ｅ））。Next, after removing the resist 106, desired ions such as boron are implanted using the oxide film 105 as a mask (FIG. 1(e)).
イオン注入終了後、酸化膜１０５、多結晶シリコン膜１
０４をウェットエツチング技術を用いてこの順に除去す
る（１４１図（ｆ））。After ion implantation, oxide film 105, polycrystalline silicon film 1
04 is removed in this order using a wet etching technique (FIG. 141(f)).
上記一実施例では多結晶シリコン膜１０４と酸化膜１０
５との２層構造を用いて説明したが、この多結晶シリコ
ン膜１０４の代わりに厚さ２００Ａ程度の窒化ケイ素（
ＳＩＮｘ） ′ｎＩ＆を気相成長法で形成しても同様の
効果を得ることができる。In the above embodiment, the polycrystalline silicon film 104 and the oxide film 10
Although the explanation has been made using a two-layer structure with 5 and 5, silicon nitride (with a thickness of about 200A) is used instead of this polycrystalline silicon film 104.
A similar effect can be obtained by forming SINx)'nI& by a vapor phase growth method.
以上説明したように、本発明はイオン注入用のマスクに
気相成長で形成した多結晶シリコン薄膜と酸化膜の２層
構造から成り、レジストは完全に除去された状態でイオ
ン注入を行なう７ξめ、レジストから放出されるガスに
よる。注入機の汚染やレジストの変質といった問題を解
決できる効果がある。As explained above, the present invention consists of a two-layer structure of a polycrystalline silicon thin film and an oxide film formed by vapor phase growth on a mask for ion implantation, and the ion implantation is performed with the resist completely removed. , due to gases released from the resist. It is effective in solving problems such as contamination of the injection machine and deterioration of the resist.
また、０ＭＯ８技術で最近注目されているレテログレー
ドウエＡ／ （ｒｅｔｒｏｇｒａｄｅ ｗｅｌｌ）
構造をハ
実現するために必要なべｅ■級のイオン注入を行なう場
合等に、有機レジストのように変質することがないため
、ゲート電極老形成し先後に、本発明のマスクを用いれ
はウェル注入、しきいｆａｔ制御用不純物注入そしてソ
ース・ドレイ／注入を連続して行なう事が可能になり、
工程短縮に効果がある。In addition, retrograde well A/ (retrograde well), which has recently been attracting attention with its 0MO8 technology.
When performing E-class ion implantation, which is necessary to realize a new structure, the mask of the present invention can be used to perform well implantation after the gate electrode has been formed, because it does not change in quality like an organic resist. , threshold fat control impurity implantation, and source/drain/implantation can be performed continuously.
Effective in shortening the process.
第１図（ａ）〜（ｆ）は、本発明の一実施例の縦断面図
、である。
】０１・・・・・・ｎ型シリコン基板、１０２・・・・
・・素子分離領域％ １０３・・・・・・ゲート酸化膜
、１０４・・・・・・多結晶シリコン、１０５・・・・
・・酸化膜、１０６・・・・・・レジスト、１０７・・
・・・・反応性イオンエツチング、１０８・・・・・・
ボロンイオン注入、１０９・・・・・・Ｐ型領域。
代理人 −ｆＰ理士 内 京 訝牛Ｉ Ｖ
第１ 図FIGS. 1(a) to 1(f) are longitudinal sectional views of an embodiment of the present invention. ]01...N-type silicon substrate, 102...
...Element isolation region% 103...Gate oxide film, 104...Polycrystalline silicon, 105...
...Oxide film, 106...Resist, 107...
...Reactive ion etching, 108...
Boron ion implantation, 109...P type region. Agent -fP Physician Uchikyo Kyougyu I V Figure 1
Claims (2)
程と、該第１の無機膜とはエッチング耐性の異なる第２
の無機膜を前記第１の無機膜上に選択的に形成する工程
と、その後前記第２の無機膜をマスクとして、前記半導
体基板にイオン注入する工程とを有することを特徴とす
る半導体装置の製造方法。(1) A step of forming a first inorganic film on one main surface of a semiconductor substrate, and a second inorganic film having different etching resistance from the first inorganic film.
selectively forming an inorganic film on the first inorganic film, and then implanting ions into the semiconductor substrate using the second inorganic film as a mask. Production method.
リコン膜又は窒化ケイ素膜であり、前記第２の無機膜は
酸化シリコン膜である特許請求の範囲第１項記載の半導
体装置の製造方法。(2) The semiconductor device according to claim 1, wherein the first inorganic film is a polycrystalline silicon film, an amorphous silicon film, or a silicon nitride film, and the second inorganic film is a silicon oxide film. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62149342A JPS63312632A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62149342A JPS63312632A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63312632A true JPS63312632A (en) | 1988-12-21 |
Family
ID=15473016
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62149342A Pending JPS63312632A (en) | 1987-06-15 | 1987-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63312632A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001003191A1 (en) * | 1999-07-02 | 2001-01-11 | Mitsubishi Materials Silicon Corporation | Soi substrate, method of manufacture thereof, and semiconductor device using soi substrate |
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| US20130137254A1 (en) * | 2011-11-24 | 2013-05-30 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor device |
-
1987
- 1987-06-15 JP JP62149342A patent/JPS63312632A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001003191A1 (en) * | 1999-07-02 | 2001-01-11 | Mitsubishi Materials Silicon Corporation | Soi substrate, method of manufacture thereof, and semiconductor device using soi substrate |
| US6558990B1 (en) | 1999-07-02 | 2003-05-06 | Mitsubishi Materials Silicon Corporation | SOI substrate, method of manufacture thereof, and semiconductor device using SOI substrate |
| JP2002368147A (en) * | 2001-04-04 | 2002-12-20 | Internatl Business Mach Corp <Ibm> | Manufacturing method for semiconductor device having deep sub-collector region |
| US20130137254A1 (en) * | 2011-11-24 | 2013-05-30 | Sumitomo Electric Industries, Ltd. | Method for manufacturing semiconductor device |
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