KR0157855B1 - Method for forming gate of semiconductor device - Google Patents

Abstract

The present invention relates to a method for manufacturing a gate using RF sputtering etching of a semiconductor device, wherein polysilicon is first formed by sputtering RF sputtering in a sputtering system and then a polyside is formed in forming a polyside gate. It is effective in removing the blisters and improving the contact resistance and adhesion between polysilicon and polyside.

Description

Gate Forming Method of Semiconductor Device

(A)-(d) of FIG. 1 is a process diagram of gate fabrication of a conventional semiconductor device.

2 is a cross-sectional view of a conventional semiconductor device in which blisters occur on a surface thereof.

3A to 3D are gate forming process diagrams of a semiconductor device of the present invention.

4 is an explanatory view showing the principle of the RF sputter etching of the present invention.

* Explanation of symbols for main parts of the drawings

1 semiconductor substrate 2 gate oxide film

3: polysilicon 4: polyside

5: gate mask 6: source / drain regions

11: RF generator 12: RF matching controller

13: etching table 14: front plate

15 wafer 16: target

17: back plate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by forming a polycide gate using TaSi ₂ using RF sputtering etching, it is suitable for preventing blisters and improving reliability thereof. It relates to a gate forming method of a semiconductor device.

In general, in the semiconductor device, a gate includes a polygate using polysilicon doped with impurities, a polyside gate using a high melting point metal silicide, a metal gate using a metal material, and the like. Polyside gates contain silicon in high melting point metals such as tantalum (Ta), titanium (Ti), or tungsten (W), and their utilization is increasing in recent years due to their excellent resistance and conduction characteristics. Referring to (a) to (d) of Figure 1 as follows.

First, as shown in FIG. 1A, a gate oxide film 2 is grown on the semiconductor substrate 1, and then polysilicon 3 is deposited on the gate oxide film 2 to a predetermined thickness. For example, phosphorus (P) ions are implanted as P-type impurities.

At this time, P ₂ O ₄ generated by the reaction of phosphorus ions and oxygen in the air during the implantation of phosphorus ions is removed using deglaze (B: HF = 7: 1), and the surface of the polysilicon 3 is removed. The resulting natural oxide film is removed by HF clean (H: F = 100: 1).

Thereafter, TaSi ₂ is reacted on the polysilicon 3 by sputtering as in (b) of FIG. 1 to form polyside (4).

Thereafter, a photoresist is applied, exposed, and developed on the polyside 4 to form a gate mask 5 as shown in FIG. 1C, and the gate mask 5 as shown in FIG. ) And dry etching the polyside (4), the polysilicon (3) and the gate oxide film (2) to form a polyside gate, and after removing the gate mask again, the semiconductor substrate using the polyside gate as a mask (1) The source / drain region 6 is formed by implanting impurities into the upper region.

However, in the case of the polyside gate formed by the above method, as shown in FIG. 2, P-type impurities leak into the surface of the polyside gate, and a blister 7 is generated, and the polyside is peeled off in a subsequent process. There is a high possibility of quality, there is a problem that the reliability of the device is lowered, the contact resistance is increased because the interface adhesion between the polysilicon and the polyside is weak.

Accordingly, an object of the present invention, in order to solve the above problems, polysilicon is first formed by sputtering RF RF sputtering in the sputtering system to form a polyside when forming a polyside gate, the blister generated during the conventional polyside formation process The present invention provides a method for forming a gate of a semiconductor device capable of removing the phenomenon and improving contact resistance and adhesion between polysilicon and polyside.

In the method of forming a gate of the semiconductor device of the present invention for achieving the above object, the polysilicon is etched to a thickness of 50 Å or less by a dry etching process using RF sputtering after sequentially stacking a gate oxide film and polysilicon on a semiconductor substrate And forming a polyside on the etched polysilicon, and sequentially forming the gate by etching the polyside, the polysilicon, and the gate oxide layer.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

In the gate forming method of the semiconductor device of the present invention, first, as shown in FIG. 3A, a gate oxide film 2 is formed on a semiconductor substrate 1 in the same manner as the conventional art, and then a polysilicon layer is formed on the gate oxide film 2. Silicon 3 is formed to a predetermined thickness d, and phosphorus (p) ions are implanted into the polysilicon 3 as P-type impurities.

Thereafter, as shown in FIG. 2 (b), the polysilicon 3 has a thickness of 50 dB or less in the sputtering system of FIG. 4 under the condition that the output of the RF matching controller 12 is -1200 V and 30 sec. After etching by the sputtering etching method, the interface of the polysilicon 3 is cleaned and then a polyside (TaSi ₂ ) 4 is formed on the etched polysilicon 3, wherein the thickness of the polysilicon 3 (d ') has the highest dopant concentration in the polysilicon (3) during etching, so the doping effect is lost when over-etching, so the etching thickness should not exceed 50Å.

The principle of the RF sputter etching is as shown in Figure 4, the plasma (Ar +) state by the (+) electric field, wherein the RF generator 11, RF matching controller 12 through the etching table Etching occurs by accelerating the negative bias applied to (13) and striking the surface of the wafer 15, which is opposite to sputtering when the target 16 is negative. As such, this is called back sputtering, reverse sputtering, ion milding or RF sputtering etching.

Subsequently, as in FIG. 2C, photoresist is applied, exposed, and developed on the polyside 4 to form a gate mask 5 as in the prior art, and as shown in FIG. Applying a mask (5) to dry-etch the polyside (4), polysilicon (3) and the gate oxide film (2) to form a polyside gate, remove the gate mask again and then the polyside gate as a mask The source / drain regions 6 are formed by implanting impurities into the upper region of the semiconductor substrate 1.

That is, the gate process of the present invention is the same as in the prior art, but polysilicon is etched for 30 sec with RF bias (-1200 V) before polyside formation, which is polysilicon (3) deposition → P doping → deglaze → HF Clean → sputter etching (-1200V, 30sec) → TaSi ₂ deposition → reaction → gate mask → gate etching.

Therefore, the wafer 15 is loaded into a sputtering system and subjected to RF etching to form polysides. Therefore, the RF sputtering etching and the formation of polysides are continuously progressed in a high vacuum state so that they do not come into contact with oxygen in the air. No blisters will occur on the surface.

As described above, according to the present invention, by removing the blisters generated during the production of the polyside gate to prevent the polyside of the upper portion of the polysilicon peeled off in the subsequent process and to improve the adhesion between the polysilicon and the polyside of the upper portion The reliability of the device can be increased, and the electrical resistance can be improved by improving the contact resistance.

Claims (2)

Sequentially depositing a gate oxide film and polysilicon on a semiconductor substrate, and etching the polysilicon to a thickness of 50 kPa or less by a dry etching process using RF sputtering, forming a polyside on the polysilicon, and And forming a gate by sequentially etching the polyside, polysilicon and the gate oxide layer after gate patterning on a side thereof. The method of claim 1, wherein the dry etching process using RF sputtering is performed under process conditions in which a bias voltage is -1200 V and a time is 30 sec.