JPH05152328A - Manufacturing method of thin film transistor - Google Patents

Abstract

PURPOSE:To implant the thin film with impurities with low accelerating energy in the manufacturing process of selfalignment type thin film transistor. CONSTITUTION:Semiconductor thin films 2 are pattern-formed on the surface of an insulating substrate 1, a lower layer gate insulating film 3 about 200Angstrom thick comprising silicon oxide is deposited on the whole surface and then an upper layer gate insulating film 4 comprising silicon nitride about 1600Angstrom thick is deposited on the whole surface so as to pattern-form a gate electrode 5 on a specific position on the surface of the upper layer insulating film 4. Next, the upper layer gate insulating film 4 is etched away using the gate electrode 5 as a mask and then the semiconductor thin films 2 are implanted with impurities (a) by-an ion implanting device also using the gate electrode 5 as a mask. At this time, the lower layer gate insulating film 3 only about 200Angstrom thick is formed on the surface of the impurity implanted regions (source-drain regions 2b) so that when phosphorus ions are implanted as the impurities, the semiconductor thin films 2 may be implanted with the impurities with low accelerating energy of about 30KeV.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art When manufacturing a self-alignment type thin film transistor, a gate insulating film is formed on a semiconductor thin film made of polysilicon or the like, a gate electrode is formed on the gate insulating film, and the gate electrode is used as a mask for ion implantation. Impurities are implanted into the semiconductor thin film by an implanting device, whereby the central portion of the semiconductor thin film in the portion corresponding to the gate electrode is used as a channel region, and both sides thereof are source / drain regions formed of impurity regions.

[0003]

However, in such a conventional thin film transistor, since impurities are implanted through the gate insulating film formed on the semiconductor thin film, the gate insulating film has a film thickness of, for example, about 1000 Å. When the gate insulating film is relatively thick, the acceleration energy of ion implantation is high to locate the peak of the impurity concentration profile in the semiconductor thin film. There is a problem that the cost of the injection device becomes high and the device may be damaged. Since the withstand voltage is low when the gate insulating film is composed of a single layer of a silicon oxide film, the gate insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film or a silicon nitride film in order to increase the withstand voltage. In the case of a single-layer structure, in order to have a capacitance corresponding to that of a single layer of a silicon oxide film, the thickness of the gate insulating film needs to be increased to about 1.5 to 2 times. For example, when the gate insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film, the thickness of the silicon oxide film is about 200Å and the thickness of the silicon nitride film is 1600.
If the total is about 1800Å, the film thickness is 10
It is possible to have a capacitance corresponding to a single layer of a silicon oxide film of about 00Å. However, in this case, when the gate insulating film becomes thicker and phosphorus ions are implanted as impurities, the acceleration energy becomes considerably high, 200 keV or more, and the cost of the ion implanter becomes higher, and damage to the device is damaged. Will also grow. An object of the present invention is to provide a method of manufacturing a thin film transistor that can implant impurities with low acceleration energy.

[0004]

According to the present invention, a gate insulating film is formed on a semiconductor thin film, a gate electrode is formed on the gate insulating film, and the gate insulating film has a thickness The semiconductor thin film is removed by etching halfway in the direction, and in this state, impurities are implanted into the semiconductor thin film by an ion implantation device using the gate electrode as a mask.

[0005]

According to the present invention, the impurity is implanted into the semiconductor thin film by the ion implantation device using the gate electrode as a mask in a state where the gate insulating film is etched and removed partway in the thickness direction. Impurities are implanted in a state where the film thickness of the insulating film is thinner than the desired film thickness, and therefore the impurities can be implanted with low acceleration energy.

[0006]

1 to 3 show respective manufacturing steps of a self-alignment type thin film transistor according to an embodiment of the present invention. Therefore, a method of manufacturing a self-alignment type thin film transistor will be described with reference to these drawings in order.

First, as shown in FIG. 1, a semiconductor thin film 2 is patterned on an upper surface of an insulating substrate 1 made of glass or the like. That is, first, plasma C is applied to the entire upper surface of the insulating substrate 1.
An amorphous silicon film for forming the semiconductor thin film 2 by VD is deposited to a thickness of about 500 Å, and then the excimer laser is irradiated to crystallize the amorphous silicon film into a polysilicon film, which is then unnecessary by photolithography technology. By etching and removing the polysilicon film at a certain portion, the semiconductor thin film 2 is patterned only in the thin film transistor forming region. next,
A lower gate insulating film 3 made of silicon oxide is deposited on the entire surface by a sputtering device to a thickness of about 200 Å. Next, the upper gate insulating film 4 made of silicon nitride is deposited on the entire surface by plasma CVD to a thickness of about 1600 Å. Next, a gate electrode 5 made of aluminum is patterned in a thickness of about 5000Å on the upper surface of the upper gate insulating film 4 corresponding to the center of the semiconductor thin film 2 by a sputtering apparatus.

Next, as shown in FIG. 2, the upper gate insulating film 4 is etched and removed using the gate electrode 5 as a mask. In this state, the lower gate insulating film 3 remains on the entire surface of the insulating substrate 1 including the semiconductor thin film 2, and only the upper surface of the lower gate insulating film 3 corresponding to the central portion (channel region 2a) of the semiconductor thin film 2 is formed. The upper gate insulating film 4 remains,
The gate electrode 5 is formed on the upper surface of the remaining upper gate insulating film 4.
Remains as it is. Next, using the gate electrode 5 as a mask, impurities are implanted into the semiconductor thin film 2 by an ion implantation device to form source / drain regions 2b on both sides of the channel region 2a of the semiconductor thin film 2. In this case, the source / drain regions 2 on both sides of the channel region 2a of the semiconductor thin film 2
Since only the lower gate insulating film 3 having a film thickness of about 200 Å is formed on the upper surface of the portion to be b, if phosphorus ions are implanted as impurities, the implantation can be performed with a low acceleration energy of about 30 keV. The cost of the device can be reduced, and the damage given to the device can be reduced. Next, excimer laser is irradiated to activate the implanted impurities.

Next, as shown in FIG. 3, an interlayer insulating film 6 made of silicon nitride is deposited on the entire upper surface by plasma CVD to a thickness of about 3000 Å. In this case, since the interlayer insulating film 6 is formed on the upper surface of the lower gate insulating film 3 covering the surface of the semiconductor thin film 2, insulation of the gate insulating film composed of the lower gate insulating film 3 and the upper gate insulating film 4 is performed. It is possible to prevent the breakdown voltage from decreasing. next,
A contact hole 7 is formed in the interlayer insulating film 6 and the lower gate insulating film 3 in the portion corresponding to the source / drain region 2b. Next, a source / drain electrode 8 made of aluminum is patterned at a predetermined position on the contact hole 7 and the upper surface of the interlayer insulating film 6 by a sputtering device to a thickness of about 5000 Å to form the source / drain region 2b.
Connect with. Thus, a self-aligned thin film transistor is manufactured.

In the above embodiment, the lower gate insulating film 3 made of silicon oxide is formed on the upper surface of the semiconductor thin film 2, and the upper gate insulating film 4 made of silicon nitride is formed on the upper surface of the lower gate insulating film 3. , The upper gate insulating film 4
The upper gate insulating film 4 is etched and removed using the gate electrode 5 formed on the upper surface of the mask as a mask, and impurities are implanted in this state, but the present invention is not limited to this. For example, the upper gate insulating film 4 may be removed by etching halfway in the thickness direction, and impurities may be implanted in this state. Further, when the lower gate insulating film 3 is formed thicker, not only the upper gate insulating film 4 but also the lower gate insulating film 3 is etched and removed halfway in the thickness direction, and impurities are injected in this state. You may do so. Furthermore, when the gate insulating film is formed of a single layer of either a silicon oxide film or a silicon nitride film, the single layer is etched and removed halfway in its thickness direction, and impurities are implanted in this state. You may do it.

[0011]

As described above, according to the present invention, impurities are added to the semiconductor thin film by the ion implantation device using the gate electrode as a mask in a state where the gate insulating film is removed by etching to the middle of its thickness direction. Since the implantation is performed, the impurities are implanted with the thickness of the gate insulating film being thinner than the intended thickness, and therefore the impurities can be implanted with low acceleration energy, which in turn reduces the cost of the ion implantation apparatus. It is possible to reduce the damage and to reduce the damage given to the device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a state in which a semiconductor thin film, a lower gate insulating film, an upper gate insulating film, and a gate electrode are formed on an upper surface of an insulating substrate when manufacturing a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a state where impurities are implanted into the semiconductor thin film using the gate electrode as a mask after the upper gate insulating film is etched and removed using the gate electrode as a mask in manufacturing the same thin film transistor.

FIG. 3 is a cross-sectional view showing a state in which an interlayer insulating film, contact holes, and source / drain electrodes are formed in manufacturing the same thin film transistor.

[Explanation of symbols]

 1 Insulating Substrate 2 Semiconductor Thin Film 3 Lower Gate Insulating Film 4 Upper Gate Insulating Film 5 Gate Electrode

Claims (3)

[Claims] 1. A gate insulating film is formed on a semiconductor thin film,
A gate electrode is formed on the gate insulating film, and the gate insulating film is etched and removed halfway in the thickness direction using the gate electrode as a mask. A method of manufacturing a thin film transistor, which comprises implanting impurities into a semiconductor thin film. 2. The gate insulating film comprises a lower layer gate insulating film made of silicon oxide formed on the semiconductor thin film and an upper layer gate insulating film made of silicon nitride formed on the lower layer gate insulating film. 2. The method of manufacturing a thin film transistor according to claim 1, wherein impurities are implanted into the semiconductor thin film by an ion implanter using the gate electrode as a mask while the upper gate insulating film is removed by etching using the gate electrode as a mask. .. 3. The film thickness of the lower gate insulating film is 200Å
And the film thickness of the upper gate insulating film is 1600Å
3. The method of manufacturing a thin film transistor according to claim 2, wherein the degree is about the same.