JP2669399B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure and a manufacturing method of an insulated gate thin film transistor (hereinafter referred to as "TFT").

[0002]

2. Description of the Related Art A conventional insulated gate thin film transistor will be described with reference to FIGS. FIG. 2 shows the TF of the conventional example 1.
It shows a T-element cross-sectional structure. First, an insulating film (1) made of a silicon oxide film or the like on a silicon substrate (11)
A polycrystalline silicon film having a thickness of about 1000 Å is deposited on the upper surface by a CVD method, and a gate electrode (3) is formed by using a lithography technique and an etching technique. Further 300Å
A gate insulating film (4) made of silicon oxide and an amorphous silicon layer to be a TFT active region, source drain region, and wiring portion are deposited in a continuous manner by a lithographic technique and an etching technique. Pattern the amorphous silicon layer. After that, the activation region (8) is masked by the lithography technique, and the source / drain region (7) of the TFT and the wiring portion (not shown) are formed by the ion implantation technique.

Next, FIG. 3 shows a TF for a liquid crystal type device of Conventional Example 2.
1 shows a sectional structure of a T element (Japanese Patent Laid-Open No. 3-15).
9175). First, a recess is formed on a glass substrate (12) on an insulating film (1) made of silicon oxide by a lithography technique and an etching technique. Further, while leaving the photoresist film used here, a conductor such as Cr is attached to a thickness of about 2000 Å by a sputtering method while leaving the gate electrode (3) and a selection electrode (not shown).
To form A plurality of the selection electrodes are arranged in parallel, and the gate electrode (3) is integrated so as to project from the selection electrode.

Further, a gate insulating film (4) made of silicon nitride having a thickness of 3000Å and a source / drain region (7) made of an amorphous silicon layer having a thickness of about 2000Å are successively deposited. Then, by removing the photoresist film used for forming the recess, the gate insulating film and the source / drain layer deposited on the part other than the recess are removed. Further, the gate electrode (3), the gate insulating film (4), the activation layer and the source / drain layer (7) which form the TFT are masked by using a lithographic technique,
The gate insulating film, the activation layer, and the source / drain layer stacked in the other recesses are removed by etching. Then, an aluminum layer is formed by the sputtering method, and the display voltage supply line (9) and the connection electrode (10) are formed by the lithography technique and the etching technique. At the same time, the source / drain region (7) is etched to separate the source and drain regions.

[0005]

In the above-mentioned prior art example 1, since the gate electrode (3) and the source / drain region (7) shown in FIG. The source / drain region (7) may overlap with the gate electrode (3) or may have an offset due to misalignment and photoresist dimension variation. As a result, TF
There is a problem in that variations in the T channel length, increase in source / drain resistance, etc. are brought about and the characteristics of the TFT are greatly affected. Further, in the structure shown in FIG. 3 of the conventional example 2, since the activation layer (8) and the source / drain layer (7) are formed by different amorphous silicon layers, the manufacturing process becomes complicated. There was a drawback.

[0006]

According to the present invention, there is provided a gate electrode embedded in a recess provided in an insulating film on a substrate, a gate electrode embedded in the recess, and a gate insulating film and an amorphous film on the insulating film. A semiconductor device comprising: a silicon layer laminated on the amorphous silicon layer; and a mask layer embedded so as to cover the transistor activation region of the amorphous silicon layer. Further, according to the present invention, a recess is formed in an insulating film formed on a substrate, a gate electrode is formed in the recess, and then a gate insulating film and an amorphous silicon layer are laminated on the gate electrode of the recess and the insulating film. A mask layer is formed so as to cover a part of the amorphous silicon layer, ions are implanted into the amorphous silicon layer using the mask layer, and a source / drain is implanted and formed in a self-aligned manner. And a method for manufacturing a semiconductor device.

[0007]

According to the present invention, a gate electrode buried in a concave portion (in a groove) provided on an insulating film, a gate insulating film and an amorphous silicon layer are laminated thereon, and the transistor of the amorphous silicon layer is formed. A mask layer formed so as to be embedded so as to cover the activation layer,
The source / drain regions of the TFT are formed by self-alignment implantation using the mask layer, and the characteristics of the TFT can be stabilized, and the number of manufacturing steps can be reduced. .

[0008]

An embodiment of the present invention will be described with reference to the drawings. 1 (a) to 1 (c) are cross-sectional views for each manufacturing process flow of a TFT showing an embodiment of the present invention. First, FIG.
As shown in (a), a gate electrode (3) is formed on a silicon substrate (11) by an lithography technique and an etching technique on an insulating film (1) made of a silicon oxide or the like having a thickness of about 5000 Å formed by a CVD method. The recesses (grooves) (2) having the pattern of are formed. Furthermore, 100 by the CVD method
A polycrystal silicon film having a thickness of about 00Å is deposited and a gate electrode (3) having a thickness of about 1000Å is formed in the recess (2) by an etch back method.

Then, as shown in FIG.
The gate insulating film (4) made of silicon oxide having a thickness of about Å and the amorphous silicon layer (5) having a thickness of about 500 Å are formed on the concave portion (2) where the gate electrode (3) is formed and the insulating film ( 1) Stack on top of each other. Since the amorphous silicon layer (5) is used as a source / drain of TFT, an activation region and a wiring portion, its pattern is formed by using a lithography technique and an etching technique.

Then, as shown in FIG. 1C, silicon oxide or the like is buried by CVD and etchback so as to cover the activation region 8 with the mask layer 6 during the source / drain implantation. To do. Then, by using the mask layer (6), ion implantation is performed to form a source / drain region and a wiring region (not shown). In this manner, the TFT activation region and the source / drain region are formed at the same time, and then a mask is formed so as to be buried over the channel portion of the activation region that is recessed in the groove.
By implanting, the source offset region and the source drain region can be formed by implantation in a self-aligned manner. That is, the source / drain is formed integrally with the activation region into the source / drain region by ion implantation.

[0011]

As described above, according to the present invention,
Compared to the conventional one, the transistor activation region and the source / drain region are integrally molded with an amorphous layer, and the source / drain region is self-aligned with the gate electrode by using a buried mask layer. Since there is no misalignment between the source and the drain and the channel length of the TFT is constant, the TFT characteristics are stabilized. Further, since the source / drain layer is integrally formed with the activation region, it is not necessary to separately form the layer. Also, since the lithography step conventionally required for forming the source / drain can be eliminated, the number of manufacturing steps can be reduced. It plays.

[Brief description of the drawings]

FIG. 1 is a sectional view of a TFT device manufacturing flow according to an embodiment of the present invention.

FIG. 2 is a sectional view of a TFT device of Conventional Example 1.

FIG. 3 is a sectional view of a TFT element for a liquid crystal display device of Conventional Example 2.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Interlayer insulating film 2 Depression 3 Gate electrode 4 Gate insulating film 5 Amorphous silicon layer 6 Mask layer 7 Source / drain region 8 Active region 9 Display voltage supply line 10 Connection electrode 11 Silicon substrate

Claims (2)

(57) [Claims] A gate electrode embedded in a concave portion provided in an insulating film on a substrate; a gate insulating film and an amorphous silicon layer laminated on the gate electrode embedded in the concave portion and the insulating film; A semiconductor device comprising: a mask layer embedded so as to cover a transistor activation region of an amorphous silicon layer. 2. A recess is formed in an insulating film formed on a substrate, a gate electrode is formed in the recess, and then a gate insulating film and an amorphous silicon layer are laminated and formed on the gate electrode of the recess and the insulating film. Forming a mask layer so as to cover a part of the amorphous silicon layer, implanting ions into the amorphous silicon layer using the mask layer, and implanting a source / drain in a self-aligned manner. The method for manufacturing a semiconductor device according to claim 1.