JP3508291B2 - Thin film transistor and method for manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method for manufacturing the same, and more particularly to a thin film transistor excellent in deterioration resistance.

[0002]

2. Description of the Related Art As a conventional thin film transistor, a polycrystalline silicon thin film transistor (hereinafter referred to as p-SiT) having a structure as shown in FIG. 10 is used.
FT) is known. This p-Si TFT
Is formed on the insulating substrate 1 as shown in FIG.
Is formed, the polycrystalline silicon film 3 is patterned into a predetermined shape, and the gate electrode 5 is formed on the polycrystalline silicon film 3 via the gate insulating film 4. Further, a source region 3a and a drain region 3b into which n-type impurities are introduced are formed in the polycrystalline silicon film 3.
In the example shown in FIG. 10, the insulating film 6 is further deposited on the gate electrode 5, and the source region 3 is formed through the contact holes formed in the insulating film 6 and the gate insulating film 4, respectively.
a, a source electrode 7 and a drain electrode 8 connected to the drain region 3b are provided. Such p-SiTF
As shown in the equivalent circuit of FIG.
The characteristics when the gate voltage (VG) is applied to the gate electrode and the drain voltage (VD) is applied to the drain electrode 3b are shown in FIG. Note that FIG. 12 shows the gate voltage (VG)
5 is a graph showing the relationship between drain voltage (VD) and drain current (ID) when V is 5V and 10V.

However, in such a p-Si TFT,
As shown in FIG. 12, when the gate applied voltage is constant and the drain applied voltage is increased, a phenomenon occurs in which the drain current (ID) rapidly increases. The current that rapidly increases with such a phenomenon is called a kink current. In the graph of FIG. 12, when the gate voltage (VG) is 5V, the kink current is generated when the drain voltage (VD) is about 13V or more, and when the gate voltage (VG) is 10V, the drain voltage (VD) is about 14V or more. It can be seen that a kink current is generated at. When such a kink current is generated, the drain current becomes excessive, which causes a problem that the p-Si TFT deteriorates. The reason why the kink current is generated is that as the number of carriers flowing in continues to increase, it exceeds the forward potential barrier between the source region and the semiconductor layer (channel region), and the lateral bipolar transistor of the source-floating substrate-drain conducts. It is considered that this is because the current rapidly increases.

In order to prevent such a rapid increase in drain current, the LDD (Li
It is possible to adopt a ghtly Doped Drain) structure. In the p-Si TFT having this structure, the low-concentration impurity regions 3c and 3d are formed inside the source region 3a and the drain region 3b.
Are formed. However, such p-Si
The TFT has a problem that the drain current itself decreases as shown in the graph of FIG.

An object of the present invention is to provide a thin film transistor which can alleviate a sudden increase in drain current and which does not have a drastic decrease in drain current which deteriorates transistor performance, and a method for manufacturing the same.

[0006]

The invention according to claim 1 is
A semiconductor layer is formed on an insulating substrate, a gate electrode is formed on one surface of the semiconductor layer via a gate insulating film, and a source electrode and a drain electrode are formed on the semiconductor layer. The electrode is connected to the controlled rectifying element and is set so that a part of the drain current flows through the controlled rectifying element when the drain current sharply increases in comparison with the drain voltage applied to the drain electrode of the thin film transistor. It is characterized by

According to a second aspect of the present invention, the semiconductor layer of the thin film transistor is provided with source / drain regions containing impurities on both sides, and the controlled rectifying element is connected to the intrinsic semiconductor layer and both ends of the semiconductor layer. A drain electrode of the controlled rectifying device and a drain electrode of the thin film transistor are connected to each other. It has a feature.

According to a third aspect of the present invention, in the controlled rectifying device, a gate electrode connected to a gate electrode of a thin film transistor via a gate insulating film is formed on one surface of a semiconductor layer, and when a drain current rapidly increases. It is characterized in that (channel length) / (channel width) of the semiconductor layer of the controlled rectifying element or the semiconductor layer of the thin film transistor is set so that a part of the drain current flows through the controlled rectifying element.

According to a fourth aspect of the present invention, at least one of the thin film transistor semiconductor layer and the semiconductor layer of the controlled rectifying element is made of a polycrystalline silicon film.

[0010] According to a fifth aspect, a step of forming a first region and a semiconductor layer made of polycrystalline silicon Mala the second region on the insulating substrate, its on both sides of the semiconductor layer of the first region
Forming a source region and a drain region by ion implantation, and forming a source electrode and a drain electrode on one surface of the first region.
The drain electrode is formed, and the semiconductor of the second region is formed.
A cathode electrode connected to the source electrode is formed on one surface of the body layer.
A gate electrode and a gate are formed in the first region and the second region on the insulating substrate either before or after the step of forming the anode electrode connected to the pole and the drain electrode and the step of forming the semiconductor layer. A step of forming an insulating film, and forming a thin film transistor in the first region,
A characteristic is that a controlled rectifying element is formed in the second region .

[0011]

According to the invention described in claim 1, when a drain voltage is applied to the thin film transistor and the applied voltage is increased, a current flows through the control rectifying element at the time when the drain current suddenly increases in the thin film transistor (a kink current is generated). Is started, which has the effect of preventing an excessive drain current from flowing through the thin film transistor.

According to the second aspect of the present invention, a controlled rectifying element having a MOS structure is used, the semiconductor layer of which is an intrinsic semiconductor, and the semiconductor of the thin film transistor has source / drain regions containing impurities. Since the threshold value is higher and this element is connected in parallel to the thin film transistor, it is possible to set so that the current starts to flow to the controlled rectifying element at the time when the drain current rapidly increases (kink current occurs) in the thin film transistor. . Therefore, it is possible to prevent an excessive drain current from flowing through the thin film transistor.

According to another aspect of the invention, in the controlled rectifying element, since the gate electrode connected to the gate electrode of the thin film transistor is formed on one surface of the semiconductor layer via the gate insulating film, (Channel length) / (Channel width) of the semiconductor layer so that the gate voltage of the controlled rectifier does not have to be generated differently from each other, and an excessive drain current flows to the controlled rectifier when the drain current suddenly increases. ) Is set appropriately, the electrical characteristics of the thin film transistor are improved, and it is not necessary to enlarge the voltage generation circuit.

According to the fourth aspect of the present invention, since the semiconductor layer and the intrinsic semiconductor layer are made of a polycrystalline silicon film, it is possible to prevent deterioration of the p-SiTFT, which easily causes a kink current.

In a fifth aspect of the present invention, the control rectifying element connected in parallel with the polycrystalline silicon film deposited on the insulating substrate can be easily formed in the step of producing a thin film transistor simply by changing the patterning or the like of the polycrystalline silicon film. It will be possible to create.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the thin film transistor and the method of manufacturing the same according to the present invention will be described below with reference to the embodiments shown in the drawings. (Embodiment 1) FIG. 1 is a plan view showing Embodiment 1 of a thin film transistor according to the present invention, and FIG. 2 shows an equivalent circuit of the thin film transistor of this embodiment. FIG. 3 is A-A of FIG.
Sectional drawing, FIG. 4 is a BB sectional view of FIG. In the figure, Q1 is a thin film transistor, and a control rectifying element Q2 having a MOS structure is connected in parallel to this thin film transistor Q1 (see FIGS. 1 and 2). As shown in FIG. 3, the structure of the thin film transistor Q1 is such that a base insulating film 12 made of silicon dioxide is formed on a glass substrate 11 serving as an insulating substrate, and a polycrystalline silicon serving as a semiconductor layer is formed on the base insulating film 12. The film 13 is formed. A gate electrode 15 is formed on the polycrystalline silicon film 13 with a gate insulating film 14 interposed therebetween. Then, in the polycrystalline silicon film 13 located on both sides of the gate electrode 15,
For example, an n-type impurity such as phosphorus is introduced so that the source region 1
3A and drain region 13B are formed. The channel region of the polycrystalline silicon film 13 sandwiched between the source region 13A and the drain region 13B is intrinsic polycrystalline silicon. Further, in this embodiment, the upper insulating film 16 is deposited on the gate electrode 15. Source region 13
Contact holes 17 and 18 that open the gate insulating film 14 and the upper insulating film 16 are formed on the A and drain regions 13B, respectively. A source electrode 19a and a drain electrode 20a are formed through these contact holes 17 and 18. The characteristics of the thin film transistor Q1 itself are similar to those of the conventional one shown in FIG.

The control rectifying element Q2, as shown in FIG.
Glass substrate 1 on which the above-mentioned thin film transistor Q1 is formed
The base insulating film 12, the gate insulating film 14, the gate electrode 15, the upper insulating film 16 and the like are commonly used. The controlled rectifying element Q2 has a MOS structure with the intrinsic polycrystalline silicon film 21, the gate insulating film 14, and the gate electrode 15 formed on the base insulating film 12. A cathode electrode 19b and an anode electrode 20b are formed in the intrinsic polycrystalline silicon 21 on both sides of the gate electrode 15 via contact holes 22 and 23, respectively. As shown in FIG. 1, the cathode electrode 19b and the source electrode 19a of the thin film transistor Q1 are connected by a source line 25, and the source line 25 is grounded. In addition, the anode electrode 20b and the thin film transistor
A drain line 24 connects the drain electrode 20a of the transistor Q1.

FIG. 5 is a graph showing the characteristics of the controlled rectifying element Q2. In this controlled rectifying element Q2, since the impurity diffusion region is not formed in the intrinsic polycrystalline silicon film 21,
Compared with a normal MOS transistor, the drain voltage (V
D) becomes higher. In this embodiment, the gate voltage (VG) is set to 5
When V is applied, the anode electrode 20b and the cathode electrode 2
The current starts to flow between 0a and 0a when the anode voltage (drain voltage) is about 12V, and when the gate voltage is 10V, the anode voltage starts to flow from about 14V.

By connecting the control rectifying element Q2 having such characteristics to the thin film transistor Q1 in parallel, the characteristics of the thin film transistor Q1 become as shown in the graph of FIG. That is, in the graph of FIG. 6, the current indicated by the broken line is the conventional kink current, but in this embodiment, at the time when the kink current is about to occur, the current i2 is fed to the control rectifying element Q2 as shown in FIG. Since the current flows, the current flowing to the thin film transistor Q1 decreases as shown in FIG. 6, and only the current i1 flows. Therefore, it is possible to prevent an excessive drain current from flowing through the thin film transistor Q1 and prevent deterioration of the thin film transistor Q1. Further, at this time, the drain current does not significantly decrease, so that the performance of the thin film transistor does not deteriorate. Also,
By applying the thin film transistor of this embodiment to an ECB type liquid crystal display device, there is an advantage that current control is good and stable color display is possible.

(Embodiment 2) FIG. 7 is a sectional view of a controlled rectifying element Q2 used in Embodiment 2 of the present invention. The controlled rectifying element Q2 has a structure similar to that of the controlled rectifying element Q2 of the first embodiment shown in FIG. 4, except that the intrinsic polycrystalline silicon film 21 is provided with a source region 21a and a drain region 21b made of n-type impurities. Is different. The other configuration of this embodiment is the same as that of the first embodiment. Particularly, in this embodiment, the distance (channel length) between the source region 21a and the drain region 21b is set longer than the width (gate length) of the gate electrode 15. By properly changing the values of the channel length and the gate length in this way, the characteristics shown in FIG. 5 can be provided. Therefore, by connecting the controlled rectifying element Q2 of this embodiment in parallel with the thin film transistor Q1 as shown in FIG. 3, the thin film transistor Q1 having the characteristics as shown in FIG. 6 can be realized. Also in this embodiment, the same operation as in the first embodiment,
The effect can be obtained.

(Embodiment 3) FIGS. 8A, 8B and 9A, 9B are process sectional views showing an embodiment of a method of manufacturing a thin film transistor according to the present invention. Note that FIG.
9A to 9C show a portion corresponding to the CC cross section of FIG. 1 in the order of steps. First, in the present embodiment, FIG.
As shown in, a base insulating film 32 made of silicon dioxide is deposited on the surface of a glass substrate 31 as an insulating substrate, and an intrinsic polycrystalline silicon film 33 is formed on the entire surface. To form the intrinsic polycrystalline silicon film 33, an intrinsic amorphous silicon film is deposited on the base insulating film 32 by, for example, a plasma CVD method and then laser-annealed to polycrystallize it. Good. Then, as shown in FIG. 3A, after the photoresist 34 is patterned by the lithography technique, anisotropic etching is performed using the photoresist 34 as a mask to form a thin film transistor Q1 and a control rectifying element Q2 as semiconductor layers. The intrinsic polycrystalline silicon films 33A and 33B are patterned.

After patterning the intrinsic polycrystalline silicon films 33A and 33B, a gate insulating film 35 made of silicon dioxide is deposited on the entire surface by a CVD method, as shown in FIG. 8B. Although the gate insulating film 35 is deposited in this embodiment, the surface of the intrinsic polycrystalline silicon films 33A and 33B may be thermally oxidized to form a thermal oxide film. Next, a gate metal film 36 is deposited on the gate insulating film 35 to have a predetermined film thickness by, for example, a sputtering method. Then, after applying a photoresist 37 on the gate metal film 36, it is patterned into a shape to be a gate mask by a lithography technique.

Then, the gate metal film 36 is anisotropically etched using the photoresist 37 as a mask to form a gate electrode 36A. Note that this gate electrode 36A is formed so as to pass over the intrinsic polycrystalline silicon films 33A and 33B similarly to the gate electrode 15 shown in FIG. After that, a photoresist 37 is applied on the entire surface, and a photoresist 38 is applied by a lithography technique so that only the pattern region of the intrinsic polycrystalline silicon film 33A is exposed.
Pattern. Then, this photoresist 38
And phosphorus (P) is ion-implanted into the intrinsic polycrystalline silicon film 33A using the gate electrode 36A as a mask. By this ion implantation, in the intrinsic polycrystalline silicon film 33A,
A source region 33S and a drain region 33D that are self-aligned with the gate electrode 36A are formed. Thus, the thin film transistor Q1 using the intrinsic polycrystalline silicon film 33A can be formed. In addition, the intrinsic polycrystalline silicon film 33
B, the gate insulating film 35, and the gate electrode 36A form a controlled rectifying element Q2.

After that, the photoresist 38 is peeled off, and an upper insulating film 39 is deposited on the entire surface as shown in FIG. 9B, and then the source region 33S and the drain region 33D formed on the intrinsic polycrystalline silicon film 33A. Contact holes are opened in the gate insulating film 35 and the upper insulating film 39 on the regions of the intrinsic polycrystalline silicon film 33B on both sides of the gate electrode 36A. Then, the source line 40 is formed so as to connect the source region 33S of the thin film transistor Q1 and the intrinsic polycrystalline silicon film 33B of the cathode side region of the control rectifying element Q2 through the contact hole. At the same time, a drain line 41 is formed so as to connect the drain region 33D of the thin film transistor Q1 and the intrinsic polycrystalline silicon film 33B in the anode side region of the controlled rectifying element Q2 via a contact hole. In this way, FIG.
A thin film transistor having a structure as shown in (B) is completed.

According to this embodiment, the thin film transistor Q1
And the controlled rectifying element Q2 can be manufactured almost simultaneously using the common material, and there is an advantage that the manufacturing becomes easy. The thin-film transistor Q1 manufactured in this example has the controlled rectifying element Q2 connected in parallel as described in the first example, and therefore, even if the drain voltage is increased, the abrupt drain current caused by the kink current is increased. It is possible to prevent deterioration while maintaining the element performance without increasing.

The first to third embodiments have been described above.
The present invention is not limited to these, and various design changes accompanying the gist of the configuration are possible. For example, in each of the above embodiments, a polycrystalline silicon film is applied as the semiconductor layer, but an amorphous silicon film, an SOI (Silicon
The present invention may of course be applied to a thin film transistor using a recrystallized film having an on insulator structure. Further, in the above embodiment, the gate electrode of the thin film transistor and the gate electrode of the controlled rectifying element were connected and the same gate voltage V _G was applied, but the controlled rectifying element is turned on at the drain voltage V _D at which the kink current is generated. For example, the gate voltage V _G may be applied according to each element without connecting the gate electrodes. Further, the thin film transistor may be a bottom gate type or a type different from the controlled rectifying element. Although the channel length is set in the above-described embodiment, the (channel length) / (channel width) may be appropriately set by changing the channel width, and the excess drain current may be supplied to the controlled rectifying element.

[0027]

As is apparent from the above description, according to the present invention, it is possible to remove the kink current that causes deterioration without significantly reducing the drain current. Therefore, there is an effect that a thin film transistor having a good deterioration resistance characteristic is realized without deteriorating the device performance. Further, according to the present invention, there is an effect that the manufacturing can be easily performed without significantly increasing the number of steps.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing the first embodiment.

3 is a sectional view taken along line AA of FIG.

4 is a sectional view taken along line BB of FIG.

FIG. 5 is a graph showing the characteristics of the controlled rectifying device of Example 1.

FIG. 6 is a graph showing characteristics of the thin film transistor of the example.

FIG. 7 is a sectional view of a control element according to Example 2 of the present invention.

8A and 8B are process cross-sectional views of a third embodiment of the present invention.

9A and 9B are process sectional views of a third embodiment of the present invention.

FIG. 10 is a cross-sectional view of a conventional thin film transistor.

FIG. 11 is an equivalent circuit diagram of a conventional thin film transistor.

FIG. 12 is a graph showing characteristics of a conventional thin film transistor.

FIG. 13 is a sectional view showing another conventional example.

FIG. 14 is a graph showing characteristics of another conventional example.

[Explanation of symbols]

Q1 thin film transistor Q2 control rectifier 13 Polycrystalline silicon film 13A source electrode 13B drain electrode 15 Gate electrode 21 Intrinsic polycrystalline silicon film

Claims (5)

(57) [Claims] 1. A thin film transistor comprising a semiconductor layer formed on an insulating substrate, a gate electrode formed on one surface of the semiconductor layer via a gate insulating film, and a source electrode and a drain electrode formed on the semiconductor layer. When the drain electrode of the thin film transistor is connected to a controlled rectifying element, and when the drain current sharply increases as compared to the drain voltage applied to the drain electrode of the thin film transistor, a part of the drain current flows to the controlled rectifying element. A thin film transistor which is set to flow. 2. The semiconductor layer of the thin film transistor is provided with source / drain regions containing impurities on both sides, and the controlled rectifying element includes an intrinsic semiconductor layer and source / drain electrodes connected to both ends of the semiconductor layer. And a gate electrode provided on one surface of the semiconductor layer via a gate insulating film, and the drain electrode of the controlled rectifying element and the drain electrode of the thin film transistor are connected to each other. The thin film transistor described. 3. The controlled rectifying device comprises a gate electrode connected to a gate electrode of a thin film transistor via a gate insulating film on one surface of a semiconductor layer, and the controlled rectifying device is provided with the gate electrode when the drain current rapidly increases. (Channel length) / of the semiconductor layer of the controlled rectifying element or the semiconductor layer of the thin film transistor so that a part of drain current flows
(Channel width) is set, The thin-film transistor of Claim 1 characterized by the above-mentioned. 4. The thin film transistor according to claim 2, wherein at least one of the semiconductor layer of the thin film transistor and the semiconductor layer of the controlled rectifying element is a polycrystalline silicon film. 5. A step of forming a semiconductor layer made of polycrystalline silicon in a first region and a second region on an insulating substrate, and ion implantation on both sides of the semiconductor layer in the first region.
Forming a source region and a drain region, and forming a source electrode and a drain electrode on one surface of the first region.
Formed on the one surface of the semiconductor layer in the second region,
A cathode electrode connected to the source electrode and the drain
A gate electrode and a gate insulating film in the first region and the second region on the insulating substrate either before or after the step of forming the anode electrode connected to the cathode electrode and the step of forming the semiconductor layer. comprising a step of forming the front and forming a thin film transistor on the first region
A method of manufacturing a thin film transistor, wherein a controlled rectifying element is formed in the second region .