JPS6273673A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent the deterioration of an active layer and surface characteristics by providing a process, in which a second metallic film consisting of a high melting point metal or a compound thereof is formed onto a first metallic film, and a process in which a Schottky gate electrode composed of the first and second metallic films is shaped. CONSTITUTION:Ions are implanted in order to form an active layer 11 in a semiconductor substrate through a first metallic film 2, and a gate electrode 17 is shaped together with a second metallic film 5 as a gate-electrode lower section 14 while being used as an annealing protective film for the active layer. On the other hand, the second metallic film covers the first metallic film, and is utilized for forming an element while shaping the gate electrode together with the first metallic film as a gate-electrode upper section 7. Ions are implanted through the first metallic film in order to form the active layer, a channeling and a charge-up on ion implantation are removed, and the first metallic film is used as the protective film on the annealing of the active layer, and left as the gate electrode, thus preventing exposure during processes of the surface of the active layer. Accordingly, contamination and deterioration due to oxidation and noxious ions, etc. are removed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a field effect transistor.
In particular, the present invention relates to a method of manufacturing a Schottky barrier junction field effect transistor formed on a GaAs semiconductor substrate.

[Technical Background of the Invention] A Schottky Variable 17-Ga 1-field effect transistor (hereinafter abbreviated as 5BFET) has a GaAS substrate.
Because MESFETs composed of
Further improved manufacturing methods are needed.

Various methods are known for manufacturing GaAs MESFETs, but the currently mainstream method is to construct the gate electrode, which becomes a Schottky Vari V, by laminating one or more metals, while the active layer Another method is to form an N+ conductive layer under the source and drain electrodes using ion implantation. Also, in this method,
The following methods have been used for ion implantation and gate electrode formation.

In other words, the ion implantation methods include a method in which impurity ions are implanted into the semiconductor substrate through a metal film, and a method in which impurity ions are implanted into the semiconductor substrate through an insulating protective film used during activation annealing. On the other hand, there are two methods for forming gate electrodes of multilayer gold 3: one is to deposit different metals in multiple layers, and the other is to form multiple layers of the same metals with different concentrations of additive elements. is being carried out.

[Problems with backsliding technology] The conventional methods described above have the following problems.

(i) In the method of implanting ions through an insulating protective film used for activation annealing, the carrier
As the temperature increases, damage to the substrate due to ion implantation is reduced. Since the Goo1-electrode is deposited after removing the film, the semiconductor substrate surface exposed after removing the protective film is contaminated by various physical and chemical treatments during the erosion process, resulting in Schottky This tends to result in devices with unstable characteristics or non-uniform active layer characteristics.

(11) Even in the method of implanting ions into a semiconductor substrate through a metal film, the metal film is removed after ion implantation and is not used as a gate electrode. This is because the ion permeability of a metal film is generally lower than that of an insulating protective film, so the amount of ions implanted is smaller than that of the above method (+).

Therefore, in the case of this method, the thickness of the metal film is at most 5-1
Therefore, when used as a gate electrode, the sheet resistance of the gate becomes high, which impedes the high-speed operation of the FET, making it difficult to form an element that can operate at a higher frequency. This is because it would be impossible.

(iii) In the conventional method in which the gate electrode is made of multilayer metal, the lower metal film forming the lower part of the gate electrode is used for ion implantation of the active layer and the N+ conductive layer, regardless of whether the constituent metals are of the same kind or different kinds. It has never been used as a permeable membrane. As a result, (i) (i
Similar to method i), the surface of the semiconductor substrate was damaged during ion implantation, and the active layer and surface characteristics were deteriorated due to the effects of oxidation and etching in subsequent steps.

[Objective of the Invention] The object of the present invention is to solve the problems in the conventional method as described above, and to provide a method that does not cause contamination and deterioration of the surface of the active layer after ion implantation, and also provides low gate sheet resistance and high mutual inductance. High frequency FET with uniform characteristics
An object of the present invention is to provide a method for manufacturing a 5BFET that can manufacture a 5BFET.

[A of invention! [Summary] In the method according to the present invention, the gate electrode is finally composed of a multilayer metal of a first and second metal film made of a high melting point metal or a compound thereof, but the first metal film is transparent. ion implantation to form an active layer into the semiconductor substrate,
Further, it is used as a protective film for the active layer, and forms a gate electrode together with the second metal film as the lower part of the electrode. On the other hand, the second metal film is characterized in that it covers the first metal film and is used for device formation, and also forms a gate electrode together with the first metal film as a gate electrode portion.

In the method of the present invention, the ion implantation for forming the active layer is carried out through the first metal film, so channeling and charge-up during ion implantation are eliminated, and carriers are distributed at a high angle of 81 degrees near the surface. It is done like this. In addition, during annealing of the active layer, the first metal film is used as a protective film and left as a gate electrode, so the active layer surface is not exposed during the process, resulting in contamination and deterioration due to oxidation, harmful ions, etc. Never. Furthermore, since the first and second metal films constitute a thick gate electrode, the sheet resistance of the gate electrode is reduced.

A preferred embodiment of the method according to claim 2 provides that the first metal film is used not only for the ion implantation of the active layer and its activation annealing, but also for the ion implantation permeable film of the N+ conductive layer and its activation annealing. It is also used as a chemical annealing protective film.

In this embodiment, the N1 conductive layer is also formed at a high concentration near the surface, thereby reducing the contact resistance between the source and drain. Further, since the first gold a film covers the entire surface of the substrate and serves as a cushion for the non-uniform stress applied to the substrate during heat treatment, abnormal re-diffusion of doped impurity atoms during heat treatment is prevented. It is particularly preferable to use a high melting point metal compound such as tungsten nitride or tungsten silicide as the first metal film because it does not itself generate thermal stress on the GaAs substrate.

Moreover, in the present invention, the second metal film can be effectively used in forming the device together with the first metal film, so that the GaΔSMESFET can be manufactured efficiently.

[Embodiments of the Invention] The main steps of the method of the present invention will be described below with reference to the drawings.

In the first embodiment, as shown in FIG. 2(a), first,
A first metal film 2 made of, for example, WN (tungsten nitride) is formed on a semi-insulating substrate 1 made of GaAs.
Deposit on the entire surface with a film thickness of 0X or less.

A resist pattern 3 having an inlet perspiration opening 3a for forming an active layer is formed thereon as shown in FIG. 2(b), and the first metal film 2 is exposed in this opening 3a. Impurities are ion-implanted into the substrate 1 by passing through the substrate 1 to form an ion-implanted region 4 to become an active layer. Next, after removing the resist pattern 3, a second metal film 5 made of MO is deposited on the first metal film 2 to a thickness of 5, as shown in FIG. 2(C).
00 to 2000 people perform the deposition. Then, on top of this, a resist pattern 6 (or Si
After forming a pattern (made of an insulator such as O2 or a composite layer of a resist and an insulator) as shown in FIG. 2(d), a second gold layer 1ffilQ5 is etched using the resist pattern 6 as a mask. A gate electrode upper part 7 is formed as shown in Figure (e).

Next, after removing the resist pattern 6, a new resist film is deposited on the entire surface, and the resist film is patterned to form a resist pattern 8 as shown in FIG. 2(f). Openings for ion implantation for forming sources and drains are formed on both sides. Then, using the gate electrode upper part 7 and the resist pattern 8 as stoppers, impurity ions are transmitted through the first metal film 2 exposed on both sides of the gate electrode upper part 7 and into the substrate 1 as shown in FIG. 2(0). Then, two N+ ion implanted regions [9] which are to become source and drain conductive layers are formed between the ion implanted region 4. Thereafter, the resist pattern 8 is peeled off, and an insulating film 10 is deposited on the entire surface as shown in FIG. After forming a film, 8
Activation annealing is performed at 00°C for 5 to 40 minutes to activate and crystallize the ion implanted regions, thereby forming the ion implanted regions into active layer 11, source N+ conductive layer 12, and drain N+, respectively. It is formed on the conductive layer 13. For annealing, capless annealing in an arsine atmosphere, lamp annealing, or other methods may be used.

Next, after peeling off the insulating film 10 as shown in FIG. 2(i), the first metal film 2 is subjected to reactive ion etching using the upper part 7 of the gate electrode as a mask, thereby forming the first metal film 2 as shown in FIG. 2(j). A lower gate electrode 14 that is self-aligned with the upper gate electrode 7 is formed.

Then, through steps such as vapor deposition of a third metal film such as aluminum, formation of a resist pattern, and selective etching of the third metal film using the resist pattern as a mask, a second metal film is formed.
As shown in Figure (k), the source electrode 1 is in ohmic contact with the source N+ conductive layer 12 and the drain N+ conductive layer 13.
5 and a drain electrode 16 are formed to complete the element forming process.

As a result, according to the method of the present invention, as shown in FIG.
A GaASMESFET is obtained in which the upper part 7 of the gate electrode 17 is made of a second gold BWA such as MO, and the lower part 14 of the gate electrode 17 is made of a first metal film such as WN.

It should be noted that the first metal film 2 may be made of tungsten alone instead of WN, and the second metal film 5 may be made of an MO compound, but may be made of a high melting point material other than W or MO. It may be composed of a metal or a compound thereof.

FIG. 3 shows the process of another second embodiment.
The steps up to FIG. 2(e) are the same as in the first embodiment. Next, the resist pattern 6 is peeled off, and as shown in FIG. 3(a), oxide GL18 is deposited on the entire surface, and then the resist
Cover 9. If you etch back this, Figure 3 (
The sidewall 20 can be left on the sidewall of the upper gate electrode 7 as shown in b). A new resist film is applied to the entire surface, and the resist film is buttered and N
1. If a conductive layer and a base for ion implantation are formed and ion implantation is performed as shown in FIG. A GaAs MESFET in which region 21 (N+ conductive layer) is formed can be obtained.

FIG. 4 shows the process of another third embodiment of inserting an offset. In the process shown in FIG. 2 (1) of the first embodiment, if the first metal film 2 is etched by reactive ion etching and a method such as plasma etching that allows side etching with good controllability is also used. As shown in FIG. 4, an offset can be created between the lower gate electrode 22 and the N1 conductive layer 12, 13 by side etching.

FIG. 5 shows the process of the fourth embodiment, which differs in the activation annealing process. In this example, N”IJ
[Capless annealing is performed for 112 and 13 in an arsine atmosphere, but the active layer is protected by the first metal film 25, the second metal film 26, and the insulator 6 (the insulator of the composite resist remains). has been done.

[Effects of the Invention] According to the method of the present invention described above, the following effects can be obtained.

(1) In conventional manufacturing methods, the surface of the active layer ion-implanted region was exposed to unfavorable conditions such as oxidation, contamination, and etching after ion implantation, resulting in unstable Schottky characteristics or poor active layer characteristics. In contrast, in the method of the present invention, the ion implantation region is covered with the cylindrical metal film 2 during the entire process, so that an element with stable shot 4 characteristics and FETV characteristics can be obtained.

(11) In the method of the present invention, ions are implanted through the first metal film 2, and there is no channeling or charge-up during ion implantation, and the carrier distribution in the conductive layer is formed near the substrate surface, resulting in high phase H conductance. An FET with uniform characteristics is obtained.

(iii) Since the gate electrode is formed thickly by laminating multiple layers, the parasitic resistance of the gate is reduced, and as a result, an FET capable of high frequency operation is obtained.

According to a preferred embodiment, (iv) ion implantation and annealing of the N'' conductive layer are performed with the metal film 2 formed on the entire surface, so that an FET with reduced source-drain contact resistance is formed and doped. The abnormal re-diffusion of impurity atoms reduced,
As a result, an FET with small short channel effect can be obtained.

(V) By placing one large id in the first metal film 2 with good controllability, the source/drain region and gate f
An offset can be inserted into f1ti, and leakage current between the gate and source and between the gate and drain can be prevented.

[Brief explanation of drawings]

Figure 1 shows a GaAs MESFET manufactured by the method of the present invention.
2(a) to 2(k) are sectional views showing the steps of the first embodiment of the method of the present invention, and FIG. 3(a) to 3(C) are sectional views showing the steps of the second embodiment of the method of the present invention. 4 and 5 are cross-sectional views showing the main steps of the third embodiment and the fourth embodiment, respectively. 1... Semiconductor substrate, 2... First metal film, 3.
...Resist pattern, 4...Active layer ion implantation i
Area, 5... Second metal film, 6... Resist pattern, 7.26... Upper part of gate electrode, 8... Resist pattern, 9, 21... N+ conductive layer ion implantation region, 10 ...Insulating film, 11...Active layer, 12.
... Source N+ conductive layer, 13... Drain N+ conductive layer, 14.22.25... Lower part of gate electrode, 15
...source electrode, 16...drain electrode, 17
...Gate electrode, 20...Side wall. Fig. 1 Fig. 2 Fig. 2 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 1, Indication of the incident 1985 Patent Application No. 212201
1. Title of the invention: Field effect transistor 'ljJ
Construction method 3, relationship with the case of the person making the amendment Patent applicant 72-6 Horiyo-cho, Saiwai-ku, Yozaki City, Kanagawa Prefecture Number of inventions increased by the amendment O8, Contents of the amendment (1) Scope of claims Attached sheet As per (2) “Preferred methods of the method of the present invention” on page 7, lines 8 to 12 of the specification.
...It is something that will be used. ”, r In a preferred embodiment of the method of the present invention, the first metal film is
It can be used not only for ion implantation of the active layer and its activation annealing, but also as an ion implantation permeable film for the N'' conductive layer (claim 2) and for the ion implantation permeable film for the N+'4 conductive layer and its activation. It is also used as a chemical annealing protective film (Claim 3).'' (Attachment) Claim 1 A step of forming a first metal film made of a high melting point metal or its compound on a semiconductor substrate, and forming an active layer in the semiconductor substrate through the first metal film. a step of ion-implanting an impurity for use, a step of forming a second metal film made of a high melting point metal or a compound thereof on the first metal film, and a Schottky gate made of the first and second metal films. A method for manufacturing a field effect transistor, comprising the step of forming an electrode. The step of forming the second metal film T culm or the gate electrode includes a step of selectively etching the second metal film to form an upper part of the gate N, and using the upper part of the gate electrode as a stopper. A step of ion-implanting an impurity for forming an N'' conductive layer under the source and drain electrodes into the semiconductor substrate through the first metal film, and after annealing the activation of the active layer and the N+ conductive layer, The method for manufacturing a field effect transistor according to claim 1, comprising the step of etching the first metal film using the upper part of the electrode as a mask to form a lower part of the gate electrode. 4. The first metal film is tungstenite. A method for manufacturing a field effect transistor according to any one of claims 1 to 3, which is made of oxide or tungsten silicide.

Claims (1)

[Claims] 1. A step of forming a first metal film made of a high melting point metal or a compound thereof on a semiconductor substrate, and forming an active layer in the semiconductor substrate through the first metal film. a step of ion-implanting impurities, a step of forming a second metal film made of a high melting point metal or a compound thereof on the first metal film, and a Schottky gate electrode made of the first and second metal films. A method of manufacturing a field effect transistor, comprising a step of forming. 2. The step of forming the second metal film or the step of forming the gate electrode includes a step of selectively etching the second metal film to form an upper part of the gate electrode, and using the upper part of the gate electrode as a stopper. a step of ion-implanting impurities for forming an N^+ conductive layer under the source and drain electrodes into the semiconductor substrate through one metal film;
+ After activation annealing of the conductive layer, the first metal film is etched using the upper part of the gate electrode as a mask to form a lower part of the gate electrode. . 3. The method for manufacturing a field effect transistor according to claim 1 or 2, wherein the first metal film is made of tungsten nitride or tungsten silicide.