JPS62206886A - Manufacture of compound-semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain an excellent Schottky junction easily while improving uniformity and reproducibility by dividing a heat treatment process into at least two steps on manufacture and making the temperature of heat treatment for a gate electrode material lower than a temperature for forming source and drain regions. CONSTITUTION:PSG films 16 are shaped on both surfaces of a substrate 11 through a CVD method or the like, and a crystallized WN film 13b is formed through first heat treatment at a comparatively low temperature. The WN film is crystallized at the low temperature, and hardly diffuses mutually and reacts on the interface with the substrate 11, and the impurity distribution of an N-type active layer 12 hardly alters, also. Si ions are implanted to the whole surface of the substrate 11, PSG films 17 are shaped on both surfaces of the substrate 11, and source and drain regions 14, 15 are formed through second heat treatment at a comparatively high temperature. Since the WN film is thermally treated, crystallized and brought into a stable state previously at the low temperature at that time, it hardly diffuses mutually and reacts between the WN film and the substrate 11 through heat treatment at the high temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a compound semiconductor field effect transistor.

(Prior Art) A compound semiconductor field effect transistor using a compound semiconductor such as GaAS as a substrate is a Schottky barrier gate field effect transistor (hereinafter referred to as IEsFE), which is a Schottky barrier gate field effect transistor (hereinafter referred to as IEsFE), in which a metal etc. is directly formed on the substrate to form a Schottky junction.
(abbreviated as T) is commonly used. That HESFE
The source series resistance (R8) existing between the source electrode and the gate electrode is a major factor in determining the characteristics of T. That is, the intrinsic transconductance (gI
Tlo) and the actual transconductance (Qm> and R8
There is a relationship between Jm-Qmo/(1+Ra gmo>, and the smaller Rs is, the larger gm is. Therefore, reducing Rs is important for improving the performance of FETs.

From this point of view, conventionally, a method of forming source/drain regions in a self-aligned manner with respect to the gate electrode has been widely used. This will be explained with reference to examples thereof and FIGS. 4(2) to 4(C). First, 3i+ ions etc. are implanted into a semi-insulating GaAS substrate (41), and heat treated to form an n-type active layer (42).
form. Thereafter, a heat-resistant metal such as tungsten (W>conductive film or a compound thereof, tungsten nitride (WN>conductive 1 [(43)) is formed on the active layer (42) by sputtering vapor deposition or the like as shown in FIG. 4(2). Next, a conductive film (4
3) is patterned as shown in Fig. 4 υ to form the gate electrode (
43a).

Thereafter, Si ions or the like are implanted using the gate electrode (43a) as a mask, and the implanted ions are activated by heat treatment at a temperature of about 800° C. to form the source region (44) and drain region as shown in FIG. 4(C). (45) is formed.

It is assumed that the gate electrode at this time is crystallized, and is indicated by (431)) in the figure. Electrodes (not shown) are preferably formed in the source and drain regions (44) and (45), respectively.

A HESFET is obtained in this way, but the conductive film (43) made of a heat-resistant metal used as a gate electrode material is often in an amorphous state when formed by sputtering, etc., and a good Schottky junction cannot be obtained. do not have.

Therefore, in the conventional example described above, it was thought that heat treatment after ion implantation not only activates the implanted ions but also crystallizes the gate electrode material and improves the Schottky junction. However, the heat treatment temperature for activating the implanted ions is 8
Because the temperature is relatively high at around 00°C, mutual diffusion and reactions occur between the unstable amorphous state and the compound semiconductor (GaAS) substrate, causing deterioration of the Schottky junction and movement of the bonding interface, resulting in There was a problem in that the uniformity and reproducibility of the formed HESFET deteriorated.

(Problems to be Solved by the Invention) As explained above, in the conventional HESFET manufacturing method described above, it is difficult to obtain a good Schottky junction, and as a result, uniformity and reproducibility are poor.

In view of the above-mentioned points, the present invention provides a method for manufacturing a compound semiconductor field effect transistor, which makes it easy to obtain a good Schottky junction and has excellent uniformity and reproducibility.

[Structure of the invention]

(Means for Solving the Problems) When manufacturing a compound semiconductor field effect transistor, the present invention divides the heat treatment process into at least two stages, and changes the temperature of the heat treatment of the gate electrode material (conductive film) to that of the source and drain region formation. The feature is that the temperature is lower than that of

(Function) In this way, the heat treatment is divided into the heat treatment process for the gate electrode material (conductive film) and the heat treatment process for forming the source and drain regions, and the heat treatment temperature for the former is lower, for example, 4.
By heating the temperature to around 50° C., the gate electrode material changes from an amorphous state to a stable crystallized state, and at this time, almost no interdiffusion or reaction occurs between the gate electrode material and the compound semiconductor. In addition, after reaching a stable crystallization state,
Even during heat treatment at a temperature of around 800° C. for forming the source and drain regions, no interdiffusion or reaction occurs between the gate electrode material and the compound semiconductor, and a good Schottky junction can be obtained.

(Example) As an example of the present invention, FIG. 1 (Q This will be explained using (e).

First, Si ions are implanted into a semi-insulating GaAS substrate 1 at an acceleration voltage of 50 KeV and a dose of 2×10 12 /cd, and heat treatment is performed at a temperature of 850° C. for 15 minutes to form an n-type active layer 0 . Next, about 4000 layers of WNNO3 are formed as shown in FIG. 1(2) by sputtering vapor deposition. At this point, WNlliOΦ is in an amorphous state. After this, WNIIIO was etched by reactive ion etching (RIE) using CF4 as an etching gas.
This is patterned to form a gate electrode (13a) as shown in FIG. 1(C). Next, apply CVD method etc. to both sides of the board.
S G film Qee 5000A [formation t,,,4
A heat treatment is performed at 50° C. for 30 minutes (first heat treatment step) to form a crystallized WN film (13b) as shown in FIG. 1(C).

At this low temperature of about 450°C (400°C to 500°C), although the WN film crystallizes, there is almost no interdiffusion or reaction at the interface with the substrate (2).
Further, the impurity distribution in the n-type active layer 0 also hardly changes. After that, Si ions were accelerated at a voltage of 100 on the other side of the substrate.
Ion implantation was performed at KeV and a dose of 13x1013/~, and then a PSG film (b) was deposited on both sides of the substrate (2) by CVD.
Approximately 500 people were formed by
~850'C) for 20 minutes (second heat treatment step)
The source and drain regions QtJ Q'j are
Form as shown in FIG. At this point, the WN film was already 450 mm thick.
Since it is heat-treated at a temperature of about 800°C to crystallize and become stable, interdiffusion or reaction with the substrate (1) hardly occurs during heat treatment at about 800°C. In this case, AuG is placed on the source and drain regions aoae.
An e film is formed by sputtering vapor deposition, etc., and source and train electrodes (14a) (15a) are formed as shown in FIG. 1(e).

The HESFET obtained by the above method had a small dispersion σ of the threshold voltage Vth within the 2-inch wafer surface of about 307 rLV, and exhibited uniform FET characteristics. In addition, the variation between wafers is small, and the average value of the threshold voltage within a 2-inch wafer surface is 7; It was within the range of ±70TrLv.
The transconductance gm indicating the performance is also 2001nS.
/ms, which was good.

For comparison, when a HESFET is obtained by the method shown in the conventional example, that is, by performing the other steps in the same manner without performing the WN film heat treatment step (first heat treatment step), the dispersion σ of Vth is 40~40.
70Trt■, and 7i is 100 for Vth"
Some wafers were seen that had shifted to the positive side by ~200 mV. This is because mutual diffusion and reaction occur between the substrate and the amorphous WNli during the heat treatment process at approximately 800°C to activate the source and drain regions, and the Schottky junction interface moves, causing the active layer to become substantially This is thought to be due to the thinner thickness.

Next, as another example, immediately after forming the gate electrode material (conductive film), heat treatment (first heat treatment step) is performed, and during the heat treatment, patterning of the electrode material and ion implantation are performed, and the ions are activated. An example in which heat treatment (second heat treatment step) was performed will be described using FIG. 2 (0 to (e)).

First, as in Fig. 1, a semi-insulating GaAS substrate (2) is
1+ acceleration voltage 50 KeV1 dose 12X1012/
Ion implantation was performed at d, and heat treatment was performed at 850°C for 15 minutes to form n-type active I! ! Form @. Next, tungsten nitride (WN > film (23)
~4000 people are deposited (Figure 2 (2)). At this point, the WN film (23) is amorphous. After this, C
P S G It! ((26) wo~500
After depositing on both sides of the substrate (20), it was heated at 450℃ for 30 minutes.
Heat treatment is performed for 30 minutes (Fig. 2 0). This results in a WN film (2
3) crystallizes from near the interface with the substrate@, forms W2N, etc., and is stabilized. On the other hand, at this temperature, GaAS substrate @
Mutual diffusion and reaction with the rufous WN film (23) on the substrate rarely occurs. Also, regarding the n-type active layer 2,
No change in carrier distribution.

Next, WNII! was crystallized by reactive ion etching using CF4 as an etching gas. I (23a
) to form a gate electrode (23b) (FIG. 2(C)), 3 i
+ accelerating voltage 100 KeV, dose fi3X101
Ion implantation is performed at 3/cm. After this, the PSG film (27
) on both sides of the substrate (20 ~ 5000, then 80
Heat treatment was performed at 0°C for 20 minutes, and the source and drain regions (
24) Form (25) (Fig. 2 1). At this point, the gate electrode (23b) has already been crystallized from near the interface with the substrate and is in a stable state.
During the heat treatment, no mutual diffusion or reaction occurs between the GaAS substrate@substrate and the electrode (23b).

After this, A
Source/drain electrodes (24a) (25) made of uGe film
a) L, an FET as shown in FIG. 2(e) is obtained.

The characteristics of the tiEsFET thus obtained were similar to those shown in FIG.

Next, as another embodiment of the present invention, a gate electrode material (conductive film) is patterned, ions are implanted using the patterned electrode material as a mask, and then heat treatment is performed twice. 2) to 0 will be used for explanation.

First, as in Fig. 1, a semi-insulating GaAS substrate (31) is
Acceleration voltage 50 KeV, dose 12X1012/
Ion implantation is performed at step d, and heat treatment is performed at 850° C. for 15 minutes to form an n-type active layer (32). Next, tungsten nitride (WN > film (33)
~4000 people (see Figure 3)). At this point, the WN film (33) is amorphous. After this, CF
The WN film (33) is patterned by reactive ion etching using etching gas No. 4 as an etching gas to form a gate electrode (33a) (FIG. 3 υ).

Next, apply 3i to the entire surface of the substrate (31) at an accelerating voltage of 100 K.
Ion implantation is performed at eV and dose 113X1013/CIi to form ion implantation layers (341) (351) (FIG. 3(C)).

After this, PSGWi (36) is applied to both sides of the substrate (31) ~
After depositing 500 layers, heat treatment is performed. In this heat treatment step, heat treatment is performed at 450° C. for 30 minutes as a first step, and then heat treatment is performed at 800° C. for 20 minutes as a second step. Through the first stage heat treatment, ~VN film (33a)
crystallizes from near the interface with the substrate (31), forms W2N, etc., stabilizes, and becomes the gate electrode (33b) (third
figure@). On the other hand, at this temperature, almost no mutual diffusion or reaction occurs between the GaAS substrate (31) and the amorphous WN film (33a). Roughly, the ion implantation layers (341) (351) are activated by the second stage heat treatment,
Source/drain regions (34) and (35) are formed (FIG. 3(e)). At this point, the gate electrode material has already been crystallized near the interface with the substrate (31) due to the first stage heat treatment and is in a stable state, so even with the heat treatment at 800°C, the GaAS substrate and the gate electrode material are No mutual diffusion or reaction occurs between the two.

After this, A
Source/train electrodes (34a) (35) made of uGe film
The fEsFET forming a) (FIG. 3 (W), obtained by the above method) also had the same effect as the first example.

As described above, according to the method of this example, a HESFET with excellent uniformity and reproducibility and high performance can be manufactured.

Note that the method for manufacturing a HESFET of the present invention is not limited to the above embodiments. For example, the substrate is not limited to GaAS, but may be other compound semiconductors. The gate electrode material is also WN
Not limited to WS i, WAJ2. WS i N.

Any conductive material containing at least a high melting point metal such as MOTaN may be used. The heat treatment method is not limited to the method of the example, but also includes S j O2, S j N 1SiON, A
A cap annealing method using J2N or the like as a coating film, a capless annealing method in an ASH3 atmosphere, etc. may be used. Furthermore, the heat treatment methods for the first stage heat treatment and the second stage heat treatment do not necessarily have to be the same.

(Effects of the Invention) As explained above, according to the present invention, a MESFET having a good Schottky junction and excellent uniformity and reproducibility can be obtained.

[Brief explanation of drawings]

FIG. 1 is a process sectional view for explaining one embodiment of the present invention.
2 and 3 are process cross-sectional views for explaining another embodiment of the present invention, and FIG. 4 is a process cross-sectional view for explaining a conventional manufacturing method. 11... Semi-insulating GaAS substrate, 12... N-type active layer, 13... WN1 in amorphous state! , 13b...
WN gate electrode, 14, 15...source and drain region, 16, 17
...PSGIIi. 14a, 15b...source/drain electrodes. Agent Patent Attorney Nori Megumi Chika Yudo Takehana KikuoFigure 1Figure 1Figure 2Figure 3Figure 4

Claims (7)

[Claims] (1) A compound semiconductor field effect obtained by forming a conductive film containing a heat-resistant metal as a constituent element to serve as a gate electrode on a compound semiconductor substrate, and performing ion implantation using this conductive film as a mask to form source and drain regions. When manufacturing a transistor, the conductive film is divided into a first heat treatment step for crystallizing at least a portion of the conductive film and a second heat treatment step for forming the source and drain regions, and the second heat treatment step 1. A method of manufacturing a compound semiconductor field effect transistor, characterized in that the temperature of the first heat treatment step is lower than the temperature of . (2) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the temperature of the first heat treatment step is 400°C to 500°C, and the temperature of the second heat treatment step is 750°C to 850°C. . (3) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the first heat treatment step is performed after processing the conductive film. (4) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the first heat treatment step is performed before processing the conductive film. (5) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the first heat treatment step is performed after ion implantation. (6) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the compound semiconductor substrate is GaAs. (7) The method for manufacturing a compound semiconductor field effect transistor according to claim 1, wherein the conductive film is tungsten nitride.