JPS62274715A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62274715A JPS62274715A JP11946286A JP11946286A JPS62274715A JP S62274715 A JPS62274715 A JP S62274715A JP 11946286 A JP11946286 A JP 11946286A JP 11946286 A JP11946286 A JP 11946286A JP S62274715 A JPS62274715 A JP S62274715A
- Authority
- JP
- Japan
- Prior art keywords
- barrier metal
- contact window
- photoresist
- insulating film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 10
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 3
- 239000010936 titanium Substances 0.000 abstract description 3
- 229910052719 titanium Inorganic materials 0.000 abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052721 tungsten Inorganic materials 0.000 abstract description 3
- 239000010937 tungsten Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000001771 vacuum deposition Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特にコンタクト
窓に自己整合的に障壁金属を形成する工程を古む半導体
装置の製造方法に関する。Detailed Description of the Invention [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device that requires a step of forming a barrier metal in a self-aligned manner in a contact window. Regarding the method.
〔従来の技術Ｊ
従来、コンタクト窓含形成し、そのコンタクト窓を覆う
ように障壁金属を形成する工程を含む半導体装置の製造
は次のように行われていた。[Prior Art J Conventionally, a semiconductor device has been manufactured as follows, including a step of forming a contact window and forming a barrier metal to cover the contact window.
第２図（ａ）〜（ｅ）は従来の半導体装置の製造方法の
一例を説明するために工程順に示した半導体チップの断
面図である。FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip shown in order of steps to explain an example of a conventional method for manufacturing a semiconductor device.
まず、第２図（ａ＞に示す様に、半導体基板１の上に、
例えば酸化膜等の絶縁膜２を形成し、ホトレジスト３に
より、所望のパターンを形成する。First, as shown in FIG. 2 (a), on the semiconductor substrate 1,
For example, an insulating film 2 such as an oxide film is formed, and a desired pattern is formed using photoresist 3.
次に、第２図（ｂ）に示す様に、ホトレジスト−３′の
パターンをマスクにして不要部分の絶縁膜を例えばＣＦ
４＋Ｈ２アラズマにより取除く。Next, as shown in FIG. 2(b), using the pattern of photoresist 3' as a mask, unnecessary parts of the insulating film are removed using, for example, CF film.
Remove with 4+H2 alasma.
引続き、第２図（ｃ）に示す様に、ホトレジスト３′を
例えば０２プラズマにより取除き、その上に例えばチタ
ン・タングステン等の障壁金属４′と真空蒸着法により
被着する。Subsequently, as shown in FIG. 2(c), the photoresist 3' is removed by, for example, O2 plasma, and a barrier metal 4', such as titanium or tungsten, is deposited thereon by vacuum evaporation.
しかる後、第２図（ｄ）に示す様に、ホトレジスト５に
よりコンタクト窓を覆う様なパターンを形成する。Thereafter, as shown in FIG. 2(d), a pattern is formed using photoresist 5 to cover the contact window.
最後に、第２図（ｅ）に示す様に、ホトレジスト５をマ
スクに、不要部分の障壁金属４′を過酸化水素水により
取除き、更に、ホトレジスト５を０２プラズマにより取
去る。Finally, as shown in FIG. 2(e), using the photoresist 5 as a mask, unnecessary portions of the barrier metal 4' are removed with hydrogen peroxide solution, and then the photoresist 5 is removed with 02 plasma.
上述した従来の半導体装置の製造方法は、コンタクト窓
の形成と、障壁金属の形成を別々に行なっていた為、工
程数が多くしかもコンタクト窓と障壁金属のパターンと
の間に目合せのマージンが必要となり、チップ面積の縮
小化が難しいという欠点があった。In the conventional semiconductor device manufacturing method described above, the formation of the contact window and the formation of the barrier metal are performed separately, which requires a large number of steps and also requires a margin for alignment between the contact window and the barrier metal pattern. This has the disadvantage that it is difficult to reduce the chip area.
本発明の目的は、少ない工程数でしかもコンタクト窓と
障壁金属のパターンを自己整合的に形成してチップ面積
の縮小化を可能にする半導体装置の製造方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which requires a small number of steps and forms contact window and barrier metal patterns in a self-aligned manner, thereby reducing the chip area.
〔問題点を解決するための手段〕
本発明の半導体装置の製造方法は、半導体基板上に絶縁
膜を形成する工程と、前記絶縁膜上に所定のパターンで
ホトレジストを形成する工程と、前記ホトレジストをマ
スクとして前記絶縁膜を除去してコンタクト窓を開孔す
る工程と、前記コンタクト窓の前記半導体基板表面上を
覆うように障壁金属を形成する工程と、前記コンタクト
窓の前記半導体基板表面上の部分を除く前記障壁金属と
前記ホトレジストとをリフトオフ法によって除去する工
程と３含んで構成される。[Means for Solving the Problems] A method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate, a step of forming a photoresist in a predetermined pattern on the insulating film, and a step of forming a photoresist in a predetermined pattern on the insulating film. forming a barrier metal so as to cover the semiconductor substrate surface of the contact window, and forming a barrier metal so as to cover the semiconductor substrate surface of the contact window. 3. removing the barrier metal and the photoresist except for portions by a lift-off method.
次に、本発明の一実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ＞に示す様に、半導体基板１上に、例
えば酸化膜等の絶縁１１！２を形成し、続いて、ホトレ
ジスト３を所望のパターンに形成する。First, as shown in FIG. 1(a), an insulator 11!2 such as an oxide film is formed on a semiconductor substrate 1, and then a photoresist 3 is formed in a desired pattern.
次に、第１図（ｂ）に示す様に、ホトレジスト３をマス
クにして不要部分の絶縁膜２を、例えばＣＦ ４ ＋８
２プラズマにより除去する。Next, as shown in FIG. 1(b), using the photoresist 3 as a mask, unnecessary parts of the insulating film 2 are coated with, for example, CF 4 +8
2.Remove using plasma.
次に、第１図（ｃ）に示す様に、例えばチタン・タング
ステン等の障壁金属４を真空蒸着法により表面に被着す
る。Next, as shown in FIG. 1(c), a barrier metal 4 such as titanium or tungsten is deposited on the surface by vacuum evaporation.
最後に、第１図（ｄ）に示す様に、不要部分の障壁金属
４をリフトオフ法によりホトレジス？−３と一緒に除去
する。Finally, as shown in FIG. 1(d), unnecessary portions of the barrier metal 4 are removed using a photoresist method using a lift-off method. -Remove together with 3.
以上説明したように本発明は、コンタクト窓をエツチン
グにより取除いた後、ホトレジスＩ・を除去せずにその
上に障壁金属を被着することにより、自己整合的にコン
タクト窓と障壁金属のパターンとの位置合せができて、
工程数の減少とチップ面積の縮小化と分区ることができ
るという効果がある。As explained above, in the present invention, after the contact window is removed by etching, the barrier metal is deposited on it without removing the photoresist I, thereby forming a pattern of the contact window and the barrier metal in a self-aligned manner. The alignment with the
This has the effect of reducing the number of steps and reducing the chip area.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面するための工程
順に示した半導体チップの断面図である。
１・・・半導体基板、２・・・絶縁膜、３．３′・・・
ホトレジスト、４．４′・・・障壁金属、５・・ホトレ
ジスト。
１′。
代理人 弁理士 内 原 晋、↓ソ（久）
（Ｃ）Ｃｂ）
Ｃの
ｆ 半を眸＃某ネタ、 ２オ鹸雇膜、３ホトレジ゛゛
スト、４−障壁金属
８１ 図
（α） （ダシ（リ
（ｅ）ｆへ一１級、２絶縁簾、
箔２図FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for sectionalizing the semiconductor chip shown in the order of steps for explaining an embodiment of the present invention. 1... Semiconductor substrate, 2... Insulating film, 3.3'...
Photoresist, 4.4'... Barrier metal, 5... Photoresist. 1′. Agent: Patent attorney Susumu Uchihara, ↓So (Hisashi)
(C)Cb)
A look at the f half of C.
(e) Grade 11 to f, 2 insulated blinds, 2 foil drawings
Claims (1)
に所定のパターンでホトレジストを形成する工程と、前
記ホトレジストをマスクとして前記絶縁膜を除去してコ
ンタクト窓を開孔する工程と、前記コンタクト窓の前記
半導体基板表面上を覆うように障壁金属を形成する工程
と、前記コンタクト窓の前記半導体基板表面上の部分を
除く前記障壁金属と前記ホトレジストとをリフトオフ法
によって除去する工程とを含むことを特徴とする半導体
装置の製造方法。a step of forming an insulating film on a semiconductor substrate, a step of forming a photoresist in a predetermined pattern on the insulating film, a step of removing the insulating film using the photoresist as a mask and opening a contact window; The method includes the steps of: forming a barrier metal so as to cover the surface of the semiconductor substrate of the contact window; and removing the barrier metal and the photoresist except for the portion of the contact window on the surface of the semiconductor substrate by a lift-off method. A method for manufacturing a semiconductor device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11946286A JPS62274715A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11946286A JPS62274715A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274715A true JPS62274715A (en) | 1987-11-28 |
Family
ID=14761949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11946286A Pending JPS62274715A (en) | 1986-05-23 | 1986-05-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274715A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434451A (en) * | 1993-01-19 | 1995-07-18 | International Business Machines Corporation | Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines |
| WO1997020342A1 (en) * | 1995-11-29 | 1997-06-05 | Simage Oy | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918268A (en) * | 1972-06-09 | 1974-02-18 |
-
1986
- 1986-05-23 JP JP11946286A patent/JPS62274715A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4918268A (en) * | 1972-06-09 | 1974-02-18 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5434451A (en) * | 1993-01-19 | 1995-07-18 | International Business Machines Corporation | Tungsten liner process for simultaneous formation of integral contact studs and interconnect lines |
| WO1997020342A1 (en) * | 1995-11-29 | 1997-06-05 | Simage Oy | Forming contacts on semiconductor substrates for radiation detectors and imaging devices |
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