JPS63287019A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63287019A JPS63287019A JP12326487A JP12326487A JPS63287019A JP S63287019 A JPS63287019 A JP S63287019A JP 12326487 A JP12326487 A JP 12326487A JP 12326487 A JP12326487 A JP 12326487A JP S63287019 A JPS63287019 A JP S63287019A
- Authority
- JP
- Japan
- Prior art keywords
- reactive ion
- insulating film
- photoresist
- ion etching
- reaction product
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 239000007795 chemical reaction product Substances 0.000 claims abstract description 15
- 238000001020 plasma etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000007789 gas Substances 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 4
- 239000001301 oxygen Substances 0.000 claims abstract description 4
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 10
- 239000002184 metal Substances 0.000 abstract description 10
- 239000003960 organic solvent Substances 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000001771 vacuum deposition Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置ゐ製造方法に係D、%に反応性イオ
ンエツチングによシコンタクトホールを形成する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and relates to a method of forming contact holes by reactive ion etching.
従来、この種の半導体装置の製造方法は、次の様におこ
なわれていた。Conventionally, a method for manufacturing this type of semiconductor device has been carried out as follows.
第3図(a)乃至第3図(d)は、従来の半導体装置の
製造方法の一例を説明する為に工程順に示した半導体チ
ップの断面図である。FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor chip shown in order of steps to explain an example of a conventional method of manufacturing a semiconductor device.
まず、第3図(a)K示す様に、半導体基板21の上K
例えば酸化膜等の絶縁膜22を形成し、次にフォトレジ
スト23によシ、所望のパターンを形成する。First, as shown in FIG. 3(a)K, the top K of the semiconductor substrate 21 is
For example, an insulating film 22 such as an oxide film is formed, and then a desired pattern is formed using a photoresist 23.
次に1第3図(b)K示す様に、フォトレジスト23の
パターンをマスクにして、不要部分の絶縁[22を例え
ば(CF4+H,)プラズマ24によってとシ除く、こ
の時コンタクト窓の側壁にはサイドウオールと呼ばれる
反応生成物25が付着する。Next, as shown in FIG. 3(b)K, using the pattern of the photoresist 23 as a mask, remove unnecessary portions of the insulation [22] using, for example, (CF4+H,) plasma 24. At this time, the side wall of the contact window is removed. A reaction product 25 called a sidewall is attached.
引き続き、第3図(C)に示す様に、フォトレジスト2
3を例えば有機溶剤によってとシ除く。この際、反応生
成物25は有機溶剤では除去できない為、依然としてコ
ンタクト窓の側壁に付着したままである。Subsequently, as shown in FIG. 3(C), photoresist 2
3 is removed, for example, with an organic solvent. At this time, since the reaction product 25 cannot be removed with an organic solvent, it remains attached to the side wall of the contact window.
最後に第3図(d3に示す様に1例えばアルミニウム等
の配線金属27を表面に真空蒸着法によシ、被着する。Finally, as shown in FIG. 3 (d3), a wiring metal 27 such as aluminum is deposited on the surface by vacuum deposition.
前述した従来の半導体装置の製造方法では、反応生成物
25がコンタクト窓の側壁に残りているので1例えば熱
処理をおこなうと、反応生成物25からガスが発生し、
上層の配線金属27を圧迫し、はなはだしい場合、上層
の配線金属27が断線するという欠点があった。In the conventional semiconductor device manufacturing method described above, since the reaction product 25 remains on the side wall of the contact window, for example, when heat treatment is performed, gas is generated from the reaction product 25.
There is a drawback that the upper layer wiring metal 27 is pressed, and if the pressure is excessive, the upper layer wiring metal 27 may be disconnected.
本発明の目的は、前記欠点が解決され、上層の配線金属
が断線する事故が生じないようにする半導体装置の製造
方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above-mentioned drawbacks and prevents the occurrence of an accident in which the upper layer metal wiring is disconnected.
本発明の半導体装置の製造方法の構成は、半導体基板上
に絶縁膜を形成する工程と、前記絶縁膜上に所定のパタ
ーンでフォトレジストを形成する工程と、前記フォトレ
ジストをマスクとして第1の反応性イオンエッチングに
より、前記絶縁膜を除去してコンタクト窓を開孔する工
程と、酸素をエツチングガスとする第2の反応性イオン
エッチングにより、前記フォトレジストの一部と前記コ
ンタクト窓に付着している反応生成物とをとシ去る工程
とを含むことを特徴とする。The method for manufacturing a semiconductor device of the present invention includes a step of forming an insulating film on a semiconductor substrate, a step of forming a photoresist in a predetermined pattern on the insulating film, and a step of forming a first photoresist using the photoresist as a mask. A step of removing the insulating film and opening a contact window by reactive ion etching, and a second reactive ion etching process using oxygen as an etching gas, remove a portion of the photoresist and the contact window. The method is characterized in that it includes a step of removing a reaction product.
次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.
第1図(a)乃至第1図(e)は本発明の第1の実施例
の半導体装置の製造方法を工程順に示した半導体チップ
の断面図である。FIGS. 1(a) to 1(e) are cross-sectional views of a semiconductor chip showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention in order of steps.
まず第1図(a)に示す様K、半導体基板1上K例えば
酸化膜等の絶縁膜2を形成し、続いてフォトレジスト3
を所望のパターンに形成する。First, as shown in FIG. 1(a), an insulating film 2 such as an oxide film is formed on the semiconductor substrate 1, and then a photoresist 3 is formed.
is formed into a desired pattern.
次に第1図Cb)に示す様に、フォトレジスト3のパタ
ーンをマスクにして、不要部分の絶縁膜2を例えば(C
F、+112)プラズマ4による反応性イオンエツチン
グによルとシ除く、この時、コンタクト窓の側壁には、
サイドウオールと呼ばれる反応生成物5が付着する。Next, as shown in FIG. 1Cb), using the pattern of the photoresist 3 as a mask, unnecessary parts of the insulating film 2 are removed, for example (Cb).
F, +112) Remove the holes by reactive ion etching using plasma 4. At this time, the side wall of the contact window is etched.
A reaction product 5 called a sidewall is attached.
この後第1図(CJに示す様に、02プラズマ6による
反応性イオンエツチングによ〕、前記フォトレジスト3
の一部と、反応生成物5を取シ除く。After this, the photoresist 3 is etched by reactive ion etching using 02 plasma 6 as shown in FIG.
and reaction product 5 are removed.
続いて第1図(d)の様に、フォトレジスト3を有機溶
剤によシとシ除く。Subsequently, as shown in FIG. 1(d), the photoresist 3 is removed using an organic solvent.
最後に第1図(e)に示す様に1例えばアルミニウム等
の配線金属7を真空蒸着法によシ被着する。Finally, as shown in FIG. 1(e), a wiring metal 7 made of, for example, aluminum is deposited by vacuum evaporation.
第2図(a)乃至第2図(e)は本発明の第2の実施例
の半導体装置の製造方法を工程順に示した半導体チップ
の断面図である。FIGS. 2(a) to 2(e) are cross-sectional views of a semiconductor chip showing a method for manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.
まず、第2図(a)K示す様に、半導体基板11及び半
導体基板上ll上に部分的に形成した配線金属18上K
例えば酸化膜等の絶縁膜12を形成し、続いてフォトレ
ジスト13を所望のパターンに形成する。First, as shown in FIG. 2(a), first, as shown in FIG.
For example, an insulating film 12 such as an oxide film is formed, and then a photoresist 13 is formed in a desired pattern.
次に1第2図(b)に示す様に、フォトレジスト13の
パターンをマスクにして、不要部分の絶縁膜12を例え
ば(CF4+H2)プラズマ14による反応性イオンエ
ツチングによりとシ除く。この時、コンタクト窓の側壁
には、サイドウオールと呼ばれる反応生成物15が付着
する。Next, as shown in FIG. 2(b), using the pattern of the photoresist 13 as a mask, unnecessary portions of the insulating film 12 are removed by reactive ion etching using, for example, (CF4+H2) plasma 14. At this time, a reaction product 15 called a sidewall adheres to the sidewall of the contact window.
この後第2図(c)K示す様に、02プラズマ16によ
る反応性イオンエッチングにより、前記フォトレジスト
13の一部と1反応生成物15を取シ除く。続−て第2
図(d)の様に、フォトレジスト13を有機溶剤によシ
と)除く。Thereafter, as shown in FIG. 2(c)K, a part of the photoresist 13 and the 1 reaction product 15 are removed by reactive ion etching using 02 plasma 16. Then the second
As shown in Figure (d), the photoresist 13 is removed using an organic solvent.
最後に第2図(e)K示す様に、例えばアルミニウム等
の配線金属17を真空蒸着法によシ被着する。Finally, as shown in FIG. 2(e)K, a wiring metal 17, such as aluminum, is deposited by vacuum evaporation.
以上説明したように、本発明は、コンタクト窓を開孔す
る際にコンタクト窓の側壁に付着する反応生成物を、酸
素をエツチングガスとする反応性イオンエツチングによ
シとシ去ることによシ、コンタクト部分での上属金属の
断線を防ぐことができる効果がある。As explained above, the present invention uses reactive ion etching using oxygen as an etching gas to remove reaction products that adhere to the side walls of the contact window when opening the contact window. This has the effect of preventing disconnection of the upper metal at the contact portion.
第1図(a)乃至第1図(e)は本発明の第1の実施例
の半導体装置の製造方法を工程順に示した半導体基板の
断面図、第2図(a)乃至第2図(e)は本発明の第2
の実施例の製造方法を工程順に示した半導体基板の断面
図、第3図(a)乃至第3図(d)は従来の半導体装置
の製造方法を工程順に示す半導体基板の断面図である。
1.11.21・・・半導体基板、2,12.22・・
・絶縁膜、3,13.23・・・ホトレジスト、4,1
4,24・・・(CF4+H2)プラズマ、5,15.
25・・・反応生成物、6,16・・・02プラズマ、
7.17,27.18・・・配線金属。
代理人 弁理士 内 原 晋/、””;)蛎)
(C)(!A)
(d)(e)
蕩1図
22図
<(1’) (C’)第j図1(a) to 1(e) are cross-sectional views of a semiconductor substrate showing the manufacturing method of a semiconductor device according to the first embodiment of the present invention in the order of steps, and FIGS. 2(a) to 2(e) e) is the second aspect of the present invention.
FIGS. 3(a) to 3(d) are cross-sectional views of a semiconductor substrate showing a conventional method for manufacturing a semiconductor device in order of steps. 1.11.21...Semiconductor substrate, 2,12.22...
・Insulating film, 3, 13.23... Photoresist, 4, 1
4,24...(CF4+H2) plasma, 5,15.
25...reaction product, 6,16...02 plasma,
7.17, 27.18... Wiring metal. Agent: Susumu Uchihara, patent attorney
(C) (!A)
(d) (e) Figure 1 Figure 22 <(1')(C') Figure j
Claims (1)
製造方法において、前記半導体基板上に絶縁膜を形成す
る工程と、前記絶縁膜上に所定のパターンでフォトレジ
ストを形成する工程と、前記フォトレジストをマスクと
して第1の反応性イオンエッチングにより、前記絶縁膜
を部分的に除去してコンタクト窓を開孔する工程と、酸
素をエッチングガスとする第2の反応性イオンエッチン
グにより、前記フォトレジストの一部と前記コンタクト
窓に付着している反応生成物とをとり去る工程とを備え
ていることを特徴とする半導体装置の製造方法。A method for manufacturing a semiconductor device in which a contact hole is formed in a semiconductor substrate, which includes the steps of forming an insulating film on the semiconductor substrate, forming a photoresist in a predetermined pattern on the insulating film, and masking the photoresist. A step of partially removing the insulating film and opening a contact window by a first reactive ion etching process, and a second reactive ion etching process using oxygen as an etching gas to partially remove the photoresist. and a step of removing reaction products adhering to the contact window.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62123264A JPH0770523B2 (en) | 1987-05-19 | 1987-05-19 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62123264A JPH0770523B2 (en) | 1987-05-19 | 1987-05-19 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63287019A true JPS63287019A (en) | 1988-11-24 |
JPH0770523B2 JPH0770523B2 (en) | 1995-07-31 |
Family
ID=14856262
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62123264A Expired - Lifetime JPH0770523B2 (en) | 1987-05-19 | 1987-05-19 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0770523B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02271634A (en) * | 1989-04-13 | 1990-11-06 | Sony Corp | Formation of multi-layer wiring |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58204558A (en) * | 1982-05-25 | 1983-11-29 | Nec Corp | Wiring method |
JPS6022340A (en) * | 1983-07-18 | 1985-02-04 | Toshiba Corp | Semiconductor device and manufacture of the same |
JPS6289333A (en) * | 1985-10-14 | 1987-04-23 | エッセヂエッセ―トムソン マイクロエレクトロニクス・エッセ・エッレ・エッレ | Improved rie plasma etching for forming ohmic contact between metal and semiconductor |
-
1987
- 1987-05-19 JP JP62123264A patent/JPH0770523B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58204558A (en) * | 1982-05-25 | 1983-11-29 | Nec Corp | Wiring method |
JPS6022340A (en) * | 1983-07-18 | 1985-02-04 | Toshiba Corp | Semiconductor device and manufacture of the same |
JPS6289333A (en) * | 1985-10-14 | 1987-04-23 | エッセヂエッセ―トムソン マイクロエレクトロニクス・エッセ・エッレ・エッレ | Improved rie plasma etching for forming ohmic contact between metal and semiconductor |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02271634A (en) * | 1989-04-13 | 1990-11-06 | Sony Corp | Formation of multi-layer wiring |
Also Published As
Publication number | Publication date |
---|---|
JPH0770523B2 (en) | 1995-07-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |