JPS63245926A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS63245926A JPS63245926A JP8021987A JP8021987A JPS63245926A JP S63245926 A JPS63245926 A JP S63245926A JP 8021987 A JP8021987 A JP 8021987A JP 8021987 A JP8021987 A JP 8021987A JP S63245926 A JPS63245926 A JP S63245926A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- wiring
- ion etching
- rie
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000010408 film Substances 0.000 claims abstract description 25
- 238000001020 plasma etching Methods 0.000 claims abstract description 22
- 239000007795 chemical reaction product Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 238000004544 sputter deposition Methods 0.000 claims abstract description 9
- 239000011261 inert gas Substances 0.000 claims abstract description 8
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 238000000992 sputter etching Methods 0.000 claims description 11
- 239000012495 reaction gas Substances 0.000 claims description 4
- 238000006053 organic reaction Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 239000007789 gas Substances 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- 239000000047 product Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 101150097381 Mtor gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- LTVOKYUPTHZZQH-UHFFFAOYSA-N difluoromethane Chemical compound F[C]F LTVOKYUPTHZZQH-UHFFFAOYSA-N 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 229920002313 fluoropolymer Polymers 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路の製造方法、特にドライエツ
チングによる微細加工に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor integrated circuit, and particularly to microfabrication by dry etching.
大規模集積回路では、配線金属膜のバターニング、絶縁
膜の開孔等の微細加工手段として、ドライエツチング法
が広く用いられている。中でも、サイドエッチの減少、
マスクパターン寸法どおシの加工性などの点から反応性
イオンエツチング(以下RIEという)による異方性エ
ツチング技術が導入されている。In large-scale integrated circuits, dry etching is widely used as a microfabrication method for patterning metal wiring films, opening holes in insulating films, and the like. Among them, reduction in side etch,
Anisotropic etching technology using reactive ion etching (hereinafter referred to as RIE) has been introduced from the viewpoint of machinability of mask pattern dimensions.
RIEによってエツチング中に、ホトレジストから放出
された物質とエツチングガスプラズマとの反応生成物が
被エツチング部の側面に付着する。この反応生成物が、
RIE終了後も残っており、一度半導体基板を大気中に
さらすと反応生成物は酸化し、被エツチング部との密着
が強固になり、その後のレジスト除去工程でも取りさる
ことが難かしい。During etching by RIE, a reaction product between a substance released from the photoresist and the etching gas plasma adheres to the side surface of the portion to be etched. This reaction product is
The reaction products remain even after RIE is completed, and once the semiconductor substrate is exposed to the atmosphere, the reaction products oxidize and become firmly attached to the etched area, making it difficult to remove in the subsequent resist removal process.
レジスト除去工程において取りさられながった反応生成
物が原因になって、後工程で問題が生ずる。例えば配線
金属膜のパターニングの場合には、配線腐食が発生した
シ、眉間絶縁膜のスルーホール開孔の場合には、スルー
ホール部上に被着された配線金属膜が後工程の熱処理に
よって変質するというような問題がある。Reaction products that are not removed during the resist removal step cause problems in subsequent steps. For example, in the case of patterning a wiring metal film, wiring corrosion may occur, and in the case of through-hole opening in an insulating film between the eyebrows, the wiring metal film deposited on the through-hole portion may be altered by heat treatment in the post-process. There is a problem like that.
本拠明の目的は、上記反応生成物に起因する、不良発生
を除去する製造方法を提供することにある。The object of the present invention is to provide a manufacturing method that eliminates defects caused by the above-mentioned reaction products.
本発明は、半導体基板上に被着した絶縁膜もしくは金属
薄膜を、ホトレジストパターンをマスクとして選択的に
除去する反応性イオンエツチング工程の終了後に、半導
体基板を大気中に露出せず、前記イオンエツチング反応
ガスが除去さnた状態で、不活性ガスの高周波スパッタ
リングによシ、前記イオンエツチング工程で被エツチン
グ部に生じた有機反応生成物を除去するようにしたもの
である。In the present invention, after a reactive ion etching process for selectively removing an insulating film or metal thin film deposited on a semiconductor substrate using a photoresist pattern as a mask, the ion etching process is performed without exposing the semiconductor substrate to the atmosphere. With the reactive gas removed, organic reaction products produced in the etched area in the ion etching step are removed by high frequency sputtering of an inert gas.
RIE直後に、半導体基板を大気に露出させると、反応
生成物は酸化がすすみ、絶縁膜、金属薄膜への付着強度
が強くなり、後では除去できなくなる。本発明では大気
中に露出せず、不活性ガスにより高周波スパッタリング
することにより、容易に除去できる。ただし、イオンエ
ツチング反応ガスが残留しない状態で行なう必要がある
。If the semiconductor substrate is exposed to the atmosphere immediately after RIE, the reaction products will be oxidized, and their adhesion to the insulating film and metal thin film will become stronger, making it impossible to remove them later. In the present invention, it is not exposed to the atmosphere and can be easily removed by high frequency sputtering using an inert gas. However, it is necessary to carry out the process in a state where no ion etching reaction gas remains.
以下、図面を参照して本発明の実施例につき説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1実施例として、配線金属膜のバターニングについて
、一層目のアルミニウム配線の場合を説明する。As a first example, regarding patterning of a wiring metal film, a case of a first layer of aluminum wiring will be described.
第1図は、工程順に示した断面図である。11はシリコ
ン基板、12は例えば熱酸化によシ形成した酸化シリコ
ン膜である。この上にスパッタリングによシ、アルミニ
ウム膜13を被着する。FIG. 1 is a sectional view showing the steps in order. 11 is a silicon substrate, and 12 is a silicon oxide film formed by, for example, thermal oxidation. An aluminum film 13 is deposited thereon by sputtering.
次にホトレジストを回転塗布し、配線形成用マスクを通
して紫外光を照射後、現像を行ない、配線にする部分の
上にホトレジスh14ft残f(第1図(a))。次に
このホトレジスト14ヲマスクにしてまずRIEを行な
う。反応ガスとして、四塩化炭素(CCL)や三塩化ホ
ウ素(BCQs )等を用い、10m Tor rから
100m’l’orr程度の圧力下で、高周波放電させ
てエツチングする。配線部分の側面に、ホトレジスト1
4から放出された物質とエツチングガスとの反応による
生成物(塩化ポリマー)16が付着し、これが配線部分
の側面を保護し、異方性エツチングが成される。第1図
(b)はRIEが終了した状態で、一層目アルミニウム
配線15の側面に反応生成物16が付着したま〜になっ
ている。Next, photoresist is spin-coated, irradiated with ultraviolet light through a mask for wiring formation, and developed, leaving 14 feet of photoresist remaining on the portion to be wired (FIG. 1(a)). Next, RIE is first performed using this photoresist 14 as a mask. Etching is performed by high frequency discharge using carbon tetrachloride (CCL), boron trichloride (BCQs), or the like as a reaction gas under a pressure of about 10 mTorr to 100 m'l'orr. Photoresist 1 on the side of the wiring part
A product (chlorinated polymer) 16 resulting from the reaction between the substance released from 4 and the etching gas adheres, protects the side surfaces of the wiring portion, and anisotropic etching is performed. FIG. 1(b) shows a state in which RIE has been completed, with reaction products 16 still attached to the side surfaces of the first layer aluminum wiring 15.
次に、シリコン基板11を大気中に開放することなく、
アルゴン等の不活性ガスを、10mTOrr程度の圧力
下で、高周波放電スパッタリングによるエツチング(以
下ではスパッタエッチという)If:行なう。これによ
って第1図(C)に示すように反応生成物16が除去さ
れる。その後ホトレジスト14ヲ除去し、第1図(d)
に示すように、一層目アルミニウム配線15が形成され
る。Next, without exposing the silicon substrate 11 to the atmosphere,
Etching (hereinafter referred to as sputter etching) by high frequency discharge sputtering is performed using an inert gas such as argon under a pressure of about 10 mTOrr. As a result, the reaction product 16 is removed as shown in FIG. 1(C). After that, the photoresist 14 was removed, as shown in FIG. 1(d).
As shown in FIG. 1, the first layer aluminum wiring 15 is formed.
嘔らに第2実施例として、層間絶縁膜のスルーホール開
孔の場合につき1、第2図を参照して説明する。層間絶
縁膜は、低温酸化シリコンと低温窒化シリコンの2層構
造′ft有するものとする。第2図(Llは、一層目ア
ルミニウム配線15ヲ第1実施例の方法で形成した後、
化学気相成長法で、窒化シリコン膜21.酸化シリコン
展22を順に低温成長させ、その上にホトレジスト23
ヲ塗布し、スルーホール24′を閉孔した状態を示す。As a second embodiment, a case where a through hole is formed in an interlayer insulating film will be described with reference to FIGS. 1 and 2. The interlayer insulating film has a two-layer structure of low-temperature silicon oxide and low-temperature silicon nitride. FIG. 2 (Ll is after forming the first layer aluminum wiring 15 by the method of the first embodiment,
A silicon nitride film 21. is grown by chemical vapor deposition. Silicon oxide layer 22 is grown at low temperature in order, and photoresist 23 is placed on top of it.
The state in which the through hole 24' has been closed is shown.
ホトレジスト23ヲマスクとして、先ず酸化シリコンM
22をウェットエッチにより等方的にエツチングした後
、窒化ンリコ7 展21 k RI Eに。As a mask for the photoresist 23, first apply silicon oxide M.
After etching 22 isotropically by wet etching, it was etched using nitride silicon 7 and 21k RIE.
て異方性エツチングを行なう。反応ガスは、4フツ化炭
素(CF4)や、2水累化2フツ化炭素(CHsFz
)等を用い、10m’l’orrから100mTorr
程度の圧力下で行なう。第2図(b)はRIE終了後の
状態全示すもので、スルーホール24の側面に反応生成
物(フッ化ポリマー)25が付着している。Then perform anisotropic etching. The reaction gas is carbon tetrafluoride (CF4) or cumulative carbon difluoride (CHsFz).
) etc., from 10m'l'orr to 100mTorr
Do this under moderate pressure. FIG. 2(b) shows the entire state after RIE, in which a reaction product (fluorinated polymer) 25 is attached to the side surface of the through hole 24.
この後で、大気に露出することなく、圧力10mTOr
r程度の不活性ガス中でスパッタエッチを行ない、第2
図(c)に示すように反応生成物るを除去する。さもに
、ホトレジスト23を除去して、一層目アルミニウム配
線15と接続するためのスルーホール冴が層間絶縁膜中
に形成式れる。After this, a pressure of 10 mTor is applied without exposure to the atmosphere.
Perform sputter etching in an inert gas of approximately
The reaction product is removed as shown in Figure (c). Similarly, the photoresist 23 is removed and a through hole for connection to the first layer aluminum wiring 15 is formed in the interlayer insulating film.
なお、本実施例は、層間絶縁膜として2層構造となし、
等方性、異方性とエツチング方法を変えることで、上方
の口径の広い形のスルーホール24を形成して2層目ア
ルミニウム配線との接続を確実にするようにしたもので
ある。Note that in this example, the interlayer insulating film has a two-layer structure,
By changing the etching method to be isotropic or anisotropic, a through hole 24 with a wide upper diameter is formed to ensure a secure connection with the second layer aluminum wiring.
第1実施例、第2実施例とも、RIE後、半導体基板を
大気に露出せず、連続的にスパッタエッチを行なう。こ
れは大気に開放すると、反応生成物が酸化し、時間が経
つとその除去が困難になるためである。In both the first and second embodiments, sputter etching is performed continuously after RIE without exposing the semiconductor substrate to the atmosphere. This is because the reaction products become oxidized when exposed to the atmosphere, and their removal becomes difficult over time.
上記のRI E、高周波スパッタリングを、半導体基板
を大気中に取出嘔ず、連続的に行なうことを可能とする
装置の一例を、第3図に示す。FIG. 3 shows an example of an apparatus capable of continuously performing the above-mentioned RIE and high-frequency sputtering without taking out the semiconductor substrate into the atmosphere.
エツチング装置は、ロードロック室31.トランスファ
ー室に、中間室お1反応室(RIE室)あ、およびスパ
ッタエッチ室あからなり、矢印はウェーハの送られる方
向(順番)を示す。The etching device has a load lock chamber 31. The transfer chamber consists of an intermediate chamber, a reaction chamber (RIE chamber), and a sputter etch chamber, and the arrows indicate the direction (order) in which the wafers are sent.
RI Ei34とスパッタエッチ室あとは、中間室間で
隔離され、各室お〜あはそれぞれ独立の排気系を有し、
また各室間はパルプIの開閉により連絡され、また閉鎖
されることで、半導体基板の搬送受渡しがなされる。パ
ルプIの操作により、反応室あ、スパッタエッチ室あが
同時に中間室おに接続されないようにできるので、スパ
ッタエッチ室あに反応ガスが混入することが完全に防が
れ、スパッタエッチ中にRIEによる反応生成物の再付
着が生ずることはない。The RI Ei34 and the sputter etch chamber are isolated between intermediate chambers, and each chamber has an independent exhaust system.
Further, the respective chambers are communicated by opening and closing the pulp I, and by closing the pulp I, the semiconductor substrates are transferred and delivered. By operating Pulp I, it is possible to prevent the reaction chamber A and the sputter etch chamber A from being connected to the intermediate chamber O at the same time, which completely prevents reaction gases from entering the sputter etch chamber and prevents RIE during sputter etching. No redeposition of reaction products occurs.
以上、説明したように、本発明では半導体基板上に被着
した絶縁膜もしくは金属薄膜を反応性イオンエツチング
(RIE)法で選択的に除去した後、大気中に露出せず
、連続して不活性ガス中で高周波スパッタエッチを行な
うことにより、RIEによる被エツチング部に付着した
反応生成物を除去する。し九がって、従来におけるよう
な大気に露出することによシ、反応生成物が酸化し、後
工程で除去することができず、配線金属の腐食あるいは
変質といった事故を完全に防ぐことができる。As explained above, in the present invention, after an insulating film or metal thin film deposited on a semiconductor substrate is selectively removed by reactive ion etching (RIE), it is not exposed to the atmosphere and is continuously etched. By performing high frequency sputter etching in an active gas, reaction products adhering to the portion to be etched by RIE are removed. Therefore, due to exposure to the atmosphere as in conventional methods, reaction products oxidize and cannot be removed in subsequent processes, making it impossible to completely prevent accidents such as corrosion or deterioration of wiring metal. can.
なお、スパッタエッチは、アルゴン等の不活性ガスのプ
ラズマ中で行なわれるので、レジスト分子とガス分子と
が反応することはない。ガス中に放出さnたレジスト分
子が被エツチング部に再付着しても、後のレジスト工程
で容易に除去される。Note that since sputter etching is performed in plasma of an inert gas such as argon, resist molecules and gas molecules do not react. Even if the resist molecules released into the gas re-adhere to the etched area, they are easily removed in a subsequent resist process.
第1図、第2図は本発明の実施例を示す断面図、第3図
は本発明を実施するエツチング装置の1例を示す図であ
る。
11・・・シリコン基板、12・・・酸化シリコン膜、
13・・・アルミニウム膜、14・・・ホトレジスト、
15・・・一層目アルミニウム配線、
】6・・・反応生成物、 21・・・窒化シリコン膜
、n・・・酸化シリコン膜、乙・・・ホトレジスト、訊
・・・スルーホール、 5・・・反応生成物、お・・・
中間室、 あ°°°反応室1あ・・・スパッタエ
ッチ室、
謁・・・パルプ。
手続主甫正書(自発)FIGS. 1 and 2 are cross-sectional views showing embodiments of the present invention, and FIG. 3 is a view showing an example of an etching apparatus for carrying out the present invention. 11... Silicon substrate, 12... Silicon oxide film,
13... Aluminum film, 14... Photoresist,
15...First layer aluminum wiring, ]6...Reaction product, 21...Silicon nitride film, n...Silicon oxide film, B...Photoresist, Q...Through hole, 5...・Reaction products,...
Intermediate chamber, ah°°°reaction chamber 1a...sputter etch chamber, audience...pulp. Procedural master's letter (spontaneous)
Claims (1)
トレジストパターンをマスクとして選択的に除去する反
応性イオンエツチング工程において、 前記工程の終了後、半導体基板を大気中に露出せず、前
記イオンエッチング反応ガスが除去された状態で、不活
性ガスの高周波スパッタリングにより、前記イオンエッ
チング工程で被エッチング部に生じた有機反応生成物を
除去することを特徴とする半導体集積回路の製造方法。[Claims] In a reactive ion etching process for selectively removing an insulating film or metal thin film deposited on a semiconductor substrate using a photoresist pattern as a mask, after the process is completed, the semiconductor substrate is exposed to the atmosphere. A semiconductor integrated circuit characterized in that organic reaction products generated in the etched portion in the ion etching step are removed by high frequency sputtering of an inert gas in a state where the ion etching reaction gas is removed. Production method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8021987A JPS63245926A (en) | 1987-03-31 | 1987-03-31 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8021987A JPS63245926A (en) | 1987-03-31 | 1987-03-31 | Manufacture of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63245926A true JPS63245926A (en) | 1988-10-13 |
Family
ID=13712266
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8021987A Pending JPS63245926A (en) | 1987-03-31 | 1987-03-31 | Manufacture of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63245926A (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0316126A (en) * | 1989-03-10 | 1991-01-24 | Hitachi Ltd | Method and apparatus for treatment of specimen |
JPH0415919A (en) * | 1990-05-09 | 1992-01-21 | Hitachi Ltd | Method of post treatment |
JPH07326606A (en) * | 1995-01-30 | 1995-12-12 | Hitachi Ltd | Sample treatment |
JPH07326607A (en) * | 1995-01-30 | 1995-12-12 | Hitachi Ltd | Sample treatment |
JPH088236A (en) * | 1995-01-30 | 1996-01-12 | Hitachi Ltd | Sample treatment method |
JPH088235A (en) * | 1995-01-30 | 1996-01-12 | Hitachi Ltd | Sample treatment method |
KR100317894B1 (en) * | 1998-02-12 | 2001-12-22 | 가네꼬 히사시 | Method of manufacturing semiconductor device |
KR100604798B1 (en) * | 1999-12-30 | 2006-07-26 | 삼성전자주식회사 | Method of etching thin layer preventing surface roughness |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS579878A (en) * | 1980-06-20 | 1982-01-19 | Toshiba Corp | Plasma etching method and apparatus |
JPS5742131A (en) * | 1980-08-27 | 1982-03-09 | Mitsubishi Electric Corp | Parallel flat board type dry etching device |
JPS57157525A (en) * | 1981-03-23 | 1982-09-29 | Fujitsu Ltd | Surface treating method |
JPS57170536A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Dry etching method |
JPS609888A (en) * | 1983-06-29 | 1985-01-18 | Sumitomo Metal Ind Ltd | Method for cleaning surface of metallic and semiconductor substrate |
JPS61113778A (en) * | 1984-11-07 | 1986-05-31 | Hitachi Ltd | Surface treating device |
-
1987
- 1987-03-31 JP JP8021987A patent/JPS63245926A/en active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS579878A (en) * | 1980-06-20 | 1982-01-19 | Toshiba Corp | Plasma etching method and apparatus |
JPS5742131A (en) * | 1980-08-27 | 1982-03-09 | Mitsubishi Electric Corp | Parallel flat board type dry etching device |
JPS57157525A (en) * | 1981-03-23 | 1982-09-29 | Fujitsu Ltd | Surface treating method |
JPS57170536A (en) * | 1981-04-15 | 1982-10-20 | Toshiba Corp | Dry etching method |
JPS609888A (en) * | 1983-06-29 | 1985-01-18 | Sumitomo Metal Ind Ltd | Method for cleaning surface of metallic and semiconductor substrate |
JPS61113778A (en) * | 1984-11-07 | 1986-05-31 | Hitachi Ltd | Surface treating device |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0316126A (en) * | 1989-03-10 | 1991-01-24 | Hitachi Ltd | Method and apparatus for treatment of specimen |
JPH0415919A (en) * | 1990-05-09 | 1992-01-21 | Hitachi Ltd | Method of post treatment |
JPH07326606A (en) * | 1995-01-30 | 1995-12-12 | Hitachi Ltd | Sample treatment |
JPH07326607A (en) * | 1995-01-30 | 1995-12-12 | Hitachi Ltd | Sample treatment |
JPH088236A (en) * | 1995-01-30 | 1996-01-12 | Hitachi Ltd | Sample treatment method |
JPH088235A (en) * | 1995-01-30 | 1996-01-12 | Hitachi Ltd | Sample treatment method |
KR100317894B1 (en) * | 1998-02-12 | 2001-12-22 | 가네꼬 히사시 | Method of manufacturing semiconductor device |
US6339019B1 (en) | 1998-02-12 | 2002-01-15 | Nec Corporation | Method of manufacturing semiconductor device having reduced connection failure between wiring layers |
KR100604798B1 (en) * | 1999-12-30 | 2006-07-26 | 삼성전자주식회사 | Method of etching thin layer preventing surface roughness |
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