JP2000269220A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain the manufacturing method of a semiconductor device, in which a processed layer used as the layer having a protective function in an after etching process can be accurately processed. SOLUTION: This manufacturing method comprises a first process, where an organic silicon layer 4 which contains an organic silicon compound is formed on a processed layer 3, a second process where the organic silicon layer 4 is patterned, a third process where the processed layer 3 is etched using the organic silicon layer 4 as a mask, and a fourth process where oxygen ions or radicals are fed to the organic silicon layer 4 so as to turn it into a silicon oxide layer 4'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and an object of the present invention is to provide a method of manufacturing a semiconductor device using an organic silicon layer containing an organic silicon compound.

[0002]

2. Description of the Related Art In a self-aligned contact formation (SAC) etching process, first, when a gate wiring is processed, it is firstly performed. An SiN layer is formed on the WSi layer and the polysilicon layer that are the gate wiring layers. Next, a resist layer is formed on the SiN layer, the SiN layer is processed by etching using the resist layer as a mask, and the WSi layer and the polysilicon layer, which are gate wiring layers, are etched using the SiN layer as a mask.

In this case, the SiN layer is used not only as a mask when processing WSi and polysilicon, but also as an etching stopper layer in a later step, for example, when forming a self-aligned contact hole on a gate wiring. . Therefore, the SiN layer needs to have a certain thickness, and as the miniaturization of the semiconductor device progresses, etching with a high aspect ratio is required, and there is a problem that processing becomes difficult.

As described above, when processing a layer used as a layer having a function of protecting from etching in a later step, such as an etching stopper layer or a mask used in another etching, a certain thickness is required. Therefore, processing with a high aspect ratio is required. However, there is a problem that the higher the aspect ratio, the more difficult it is to process.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a semiconductor device capable of accurately processing a layer used as a layer having a function of protecting from etching in a later step. It is to provide a manufacturing method of.

[0006]

SUMMARY OF THE INVENTION The present invention comprises a step of forming an organic silicon layer containing an organic silicon compound on a layer to be processed, a step of patterning the organic silicon layer, and a step of masking the organic silicon layer. A step of etching a layer to be processed and a step of supplying oxygen ions or radicals to the organic silicon layer to form a silicon oxide layer.

The organic silicon layer according to the present invention functions as an anti-reflection layer, and the silicon oxide layer obtained by oxidizing the organic silicon layer has high etching resistance. Therefore, according to the present invention, a protective layer having high etching resistance can be accurately formed on a layer to be processed. The protective layer protects the processed layer from unnecessary shaving in a later step, for example, when etching the wiring layer using the processed film as a mask, or when forming a self-aligned contact hole on the processed film. It shows the functions of a mask, an etching stopper layer, and the like. By forming such a protective layer according to the present invention, the layer to be processed can be thinned, so that the layer to be processed can be processed with high accuracy.

The present invention is effective in forming a self-aligned contact hole, and is more effective in forming a self-aligned contact in a NANDE ² PROM structure process in which a gate aspect ratio is increased.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to the present invention will be described with reference to FIG.
The steps of processing the layers will be described as an example for each step.

(First Step) The first step is a step of forming an organic silicon layer on the layer to be processed. As shown in FIG. 1A, a wiring layer 2 serving as a gate wiring is formed on a silicon substrate 1, and a SiN layer (processed layer) 3 used as a gate wiring processing mask is formed on the wiring layer 2. Are formed. In order to process such a layer 3 to be processed,
First, the organic silicon layer 4 is formed on the processing target layer 3.

In the present invention, the layer to be processed is not limited to the SiN layer shown in FIG. 1, but may be a conductive layer made of a wiring material or an electrode material formed on a silicon substrate, polyimide, S
An insulating layer made of an organic material such as OG or an inorganic material, a blank mask material, or the like can be used.

The layer to be processed in the present invention is preferably a layer used as an etching mask in a later step or a layer used as an etching stopper.

On the other hand, the organic silicon layer used in the present invention contains an organic silicon compound.

The organic silicon compound used in the present invention is a compound having a direct bond between carbon and silicon.
In particular, it has a direct bond between carbon and silicon and has Si-S in the main chain.
A polymer compound having an i bond is desirable, and examples thereof include polysilane and polysilene. The molecular weight of these compounds is not particularly limited, but is preferably 200
~ 100,100, more preferably 500 ~ 300,0
00 is good.

As specific examples, for example, the following chemical formulas 1-1 to 1-1:
1-19 and 2-1 to 2-13. Note that n and m in these chemical formulas represent positive integers.

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Embedded image The organic silicon layer contains various additives other than the above-mentioned organic silicon compound, such as a thermal polymerization inhibitor for improving storage stability as needed, and an adhesion improver for improving adhesion to a substrate. It may be.

The organosilicon layer is usually formed by dissolving the organosilicon compound and, where appropriate, additives in a solvent to form a solution, coating the solution on a substrate, and then heating to volatilize the solvent.

The thickness of the organic silicon layer is 10 to 5000 n.
m is preferable.

The organic silicon layer containing the organic silicon compound functions not only as a mask and a protective layer by oxidation but also as an anti-reflection layer when the resist layer is exposed.

(Second Step) The second step is a step of patterning the organic silicon layer.

In patterning the organic silicon layer, for example, as shown in FIG. 1B, a resist pattern 5 is formed on the organic silicon layer 4 by using photolithography, and then as shown in FIG. 1C. The etching can be performed by etching the organic silicon layer 4 using the resist pattern 5 as an etching mask. The formation of the resist pattern 5 is obtained by irradiating the resist layer with exposure light through a desired mask and developing the exposed resist layer.

For etching the organic silicon layer, an etching apparatus such as a reactive plasma etching system, a magnetron reactive plasma etching system, an electron beam plasma etching system, a TCP etching system, an ICP etching system, or an ECR plasma etching system is used. can do.

(Third Step) In a third step, the layer to be processed is processed using the organic silicon layer as a mask.

As shown in FIG. 1D, using the resist pattern 5 and the silicon oxide layer 4 'as a mask, a reactive plasma etching method, a magnetron reactive plasma etching method, an electron beam plasma etching method,
The layer 3 to be processed is etched by an etching apparatus such as a CP etching method, an ICP etching method, or an ECR plasma etching method.

(Fourth Step) In a fourth step, a step of supplying oxygen ions or radicals to the patterned organic silicon layer to form a silicon oxide layer is performed.

As shown in FIG. 1D, the organic silicon layer 4
To supply oxygen ions or radicals to form a silicon oxide layer 4 '. At this time, the silicon oxide layer 4 'can be obtained from the organic silicon layer 4 by irradiating a high energy beam in an atmosphere containing oxygen to oxidize the bond between silicon and silicon. Examples of the high energy beam include ultraviolet light, an electron beam, an ion beam, and X-rays. At this time, the resist layer 5 may also be peeled off at the same time.

Thereafter, a post-process according to the structure of the device is performed. For example, when the wiring layer is etched using the film to be processed as a mask or when a self-aligned contact hole is formed on the film to be processed. Since the silicon oxide film layer 4 'is formed on the surface of the processing target layer 3, the processing target film 3 can be protected from unnecessary shaving.

[0027]

(Embodiment 1) FIG. 2 shows a magnetron RIE apparatus which is an etching apparatus used in Embodiments 1 and 2. In FIG. 2, a mounting table 23 on which the workpiece 22 is mounted is provided in the vacuum chamber 21, and a counter electrode 24 is provided to face the mounting table 23. The mounting table 23 has a temperature control mechanism, and
Temperature can be controlled.

A gas inlet tube 25 is connected to the top wall of the vacuum chamber. Gas is introduced into the vacuum chamber 21 from the gas introduction pipe 25, and the pressure is adjusted by a valve at the exhaust port 26. After the pressure shows stability,
The plasma is generated in the vacuum chamber by applying a high frequency from the lower high-frequency electrode 27. Further, a magnet 28 is provided on the outer peripheral portion of the vacuum chamber, and a high-density magnetic field is generated in a vacuum so that ions in the plasma have anisotropy, so that the object 22 is etched.

In the present invention, other than the magnetron RIE apparatus, other dry etching apparatuses such as ECR, helicon, and inductively coupled plasma can be used.

In this embodiment, the present invention was used to fabricate a gate wiring of a device having a self-aligned contact hole by the following procedure. FIG. 3 is a schematic view showing a gate wiring processing step of this embodiment. First, as shown in FIG.
A thin thermal oxide layer 32 is formed on a silicon substrate 31, a polysilicon layer 33 and a WSi layer 34 are formed, and then the SiN layer 3 to be processed is formed using a low pressure CVD apparatus.
5 is formed. After forming the SiN layer 35, polysilane 36 is applied to the anti-reflection layer, applied to the polysilane 36, exposed,
The gate wiring is patterned using the developed resist layer 37. Next, using the etching apparatus of FIG.
75 (mTorr), 300 (W), Cl / O ₂ = 75
Resist layer 3 using a mixed gas of / 10 (sccm).
After the etching of the polysilane 36 using the mask 7 as a mask, as shown in FIG. 3B, using the resist layer 37 and the polysilane 36 as a mask, 40 (mTorr), 1200
(W), CF ₄ / O ₂ = 100/20 (sccm),
The SiN layer 35 is etched. Next, as shown in FIG. 3C, the resist layer 37 was peeled off by O ₂ ashing. Conditions are 300 (mTorr), 700
(W), O ₂ = 80 (sccm). At this time, the polysilane 36 is removed simultaneously with the removal of the resist layer 37.
Is removed as CO, and O ₂ is supplied to the C portion to form an SiO ₂ layer 36 ′. At this time, polysilane 3
6 shows that the layer thickness of about 1800 (A) at the time of formation
_After forming the SiO ₂ layer 36 'by ₂ ashing, 600
(A) It became about.

[0031] The SiO ₂ as further shown in FIG. 3 (d)
Using the layer 36 'and the SiN layer 35 as a mask, the WSi layer 3
4 and the polysilicon layer 33 are processed and stopped by the underlying thermal oxide layer. At this time, the WSi layer 34 is formed using 20 (mTorr) 200 (W), H
Etching was performed at Cl / Cl ₂ / O ₂ = 50/10/5 (sccm). At this time, the selectivity with respect to SiO ₂ is:
It was possible to obtain about 20. The polysilicon layer 33 is made of 100 (mTorr), 300 (W), HBr.
Etching was performed at / Cl ₂ = 100/10 (sccm). At this time, it was possible to obtain a selectivity of about 100 with respect to SiO ₂ .

By etching the gate wiring using the SiO ₂ layer 36 ′ as a mask, the WSi layer 34
(A) Etching is performed, and the polysilicon layer 33 is
Even when the etching was performed at about 000 (A), the SiO ₂ layer 36 ′ was cut off only at about 40 (A), so that sufficient processing was possible.

On the other hand, if the gate wiring is etched similarly using only the silicon nitride layer as a mask, the silicon nitride layer is cut off by about 200 to 300 (A).

Therefore, the upper SiN layer is protected by the SiO ₂ layer, and the thickness of the SiN layer can be reduced accordingly.

According to the present invention, even in the case of a gate wiring structure having a high aspect such as a NAND structure, the processing becomes easy and the thickness of SiN can be sufficiently reduced. This time, 600
(A) Polysilane having a thickness of about (A) is formed into SiO ₂ , and processing is performed. However, in the case of processing wiring with a high aspect ratio, it is also possible to increase the thickness of the SiO ₂ layer by applying polysilane thickly. .

In a later step, as shown in FIG. 3E, the interlayer insulating layer 38 made of an organic silicon oxide film or an inorganic silicon oxide film formed on the gate wiring was etched to form a self-aligned contact hole. . At this time, the SiN layer 35 on the gate wiring layer served as an etching stopper, and high selective etching could be performed.

On the other hand, without forming the SiO ₂ layer 36 ′,
When only the N layer is formed and a self-aligned contact hole is formed in a later step, the etching selectivity at the shoulder portion of the gate wiring is reduced to about one third as compared with a flat portion ( From about 39 to about 13 (selectivity of SiO ₂ to SiN etching), and in this embodiment, it was improved to about 20.
It is considered that this is because the SiN layer was protected by the SiO ₂ layer and was not exposed to ions during the gate wiring processing in the present embodiment, so that no ion damage occurred on the shoulder portion of the SiN layer. (Embodiment 2) In this embodiment, metal wiring was processed by the following procedure using the present invention. FIGS. 4 and 5 are schematic diagrams showing the metal wiring processing steps of this embodiment.

On a silicon substrate 41 (SiO ₂ or FS
G) through two interlayer insulating layers 42.
An Al—Cu wiring material layer 43 was formed, and a SiN layer 44 was formed on the wiring material layer 43. Then, FIG.
As shown in FIG. 7, a polysilane 45 and a resist layer 46 were applied on the SiN layer 44, and the resist layer 46 was exposed, developed, and patterned.

Next, using the same apparatus as in the first embodiment, using the resist layer 46 as a mask, 75 (mTorr), 300
(W), the polysilane 45 was etched at Cl / O ₂ = 75/10 (sccm).

Next, a resist layer 46 and a polysilane 45
(MTorr), 1200 (W), CF
₄ / O ₂ = 100/20 (sccm) and the SiN layer 44
Was etched.

Next, as shown in FIG. 4B, the resist layer 46 was peeled off by O ₂ ashing. Condition is 300
(MTorr), 799 (W), O ₂ = 80 (scc)
m). At this time, C constituting the polysilane 45
Is removed as CO, and O is supplied to the part C,
The result was an SiO ₂ layer 45 ′.

Next, as shown in FIG.
_{Using the two} layers 45 'and the SiN layer 44 as a mask, the wiring material layer 43 was etched. The etching of the wiring material layer 43 stopped at the interlayer insulating layer 42.

Next, as shown in FIG.
Very high etchin with SiN using 44 as mask
(40 (mTorr), 1400
(W), C ₄F₈/ CO / Ar = 10/50/200
(Sccm)), contacting the lower interlayer insulating layer 42
Perform hole etching and alkali wet treatment
Do.

Next, as shown in FIG.
3 was formed in the contact hole.

Next, as shown in FIG. 5F, the wiring material 43 was planarized by CMP using the SiN layer 44 as a stopper.

Next, as shown in FIG. 5G, an interlayer insulating layer 42 'was formed, and a contact hole was formed in the interlayer insulating layer 42' again.

The SiN layer 44 serves as a stopper for borderless etching in the contact hole forming etching process. This makes it possible to suppress borderless etching and easily form a wiring. In particular, the mixed Logic part with a narrow fringe width and Lo
The gic part is a very effective technique.

In this case, Al, Al-
Although using Cu, polysilicon, tungsten,
WSi, Nb or the like may be used. (Embodiment 3) In this embodiment, an interlayer insulating film was processed by the following procedure using the present invention. FIG. 6 is a schematic view showing a step of processing the interlayer insulating film of this embodiment.

First, an interlayer insulating layer 62 (made of SiO ₂ or FSG) was formed on a silicon substrate 61, and a carbon layer 63 was formed as a film to be processed. Carbon layer 6
Numeral 3 is used as a mask when etching the interlayer insulating layer 62. At this time, an organic silicon film, an inorganic silicon film, or a silicon oxide film was used as the interlayer insulating film 62. Further, the carbon layer 63 is formed by the CVD method, but may be formed by a coating type apparatus.

Thereafter, as shown in FIG. 6A, a polysilane 64 and a resist layer 65 were applied on the carbon layer 63, and the resist layer 64 was exposed, developed, and patterned.

Next, as shown in FIG. 6B, using the same apparatus as in the first embodiment, the resist
(MTorr), 300 (w), Cl / O ₂ = 75/1
The polysilane 64 was etched at 0 (sccm).

Next, as shown in FIG.
5, and 70 (mTorr) using polysilane 64 as a mask.
r), 500 (W), O₂= 20 (sccm)
The bon layer 63 was etched. At this time, the resist layer
65 is peeled off, and C constituting the polysilane 64 is CO 2
As a result, O is supplied to the portion C and SiO 2 is removed.₂
The layer 64 'is formed of SiO₂By oxygen etching
Can not be scraped, so the actual SiO₂Layer 64 'is carbon layer 6
3 is the mask. At this time, the carbon layer and SiO ₂layer
Is about 200.

Next, as shown in FIG. 4D, after the SiO ₂ layer 64 ′ is peeled off, the carbon layer 63 is used as a mask.
40 (mTorr), 1400 (W), C ₄ F ₈ / CO
The etching of the interlayer insulating layer 62 was performed under the condition of / Ar / O ₂ = 10/50/200/8 (sccm). The selectivity between the interlayer insulating film 62 and the carbon layer was about 20 in the case where the interlayer insulating film was an organic silicon film, an inorganic silicon film, or a silicon oxide film.

In this embodiment, after the SiO ₂ layer 64 ′ is peeled off, the interlayer insulating layer 62 is etched using the carbon layer 63 as a mask, but without removing the SiO ₂ layer 64 ′,
The etching may be performed using the carbon layer and the SiO ₂ layer 64 ′ as a mask.

According to the present embodiment, the processing from the processing of the carbon layer 63 to be processed to the processing of the interlayer insulating film 62 can be performed by the same method.

In this embodiment, when etching a low dielectric constant film such as an organic silicon oxide film or an inorganic silicon oxide film used as an interlayer insulating film, a large amount of O ₂ is required as an etching gas. Conventionally, such a low dielectric constant film has been etched using a resist pattern as a mask. However, if etching is performed using a large amount of O ₂ gas as described above, the selectivity with the resist cannot be obtained, and the resist cannot be processed. Processing was very difficult because of thinning along with miniaturization.

However, if etching is performed as in this embodiment, a low dielectric constant film such as an organic silicon oxide film or an inorganic silicon oxide film can be selectively etched. In this embodiment, the interlayer insulating film is etched using the carbon film as a mask, but a resist layer may be used instead of the carbon film.

[0058]

As described above, according to the present invention, a layer used as a layer having a protective function in a later step can be processed with high accuracy.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a process of processing a SiN layer serving as a mask for processing a gate wiring, which is applied to one embodiment of the present invention.

FIG. 2 is a configuration diagram of an etching apparatus applied to the embodiment.

FIG. 3 is a schematic view showing a gate wiring processing step according to the first embodiment.

FIG. 4 is a schematic view showing a metal wiring processing step according to the second embodiment.

FIG. 5 is a schematic view showing a metal wiring processing step according to the second embodiment.

FIG. 6 is a schematic view showing an interlayer insulating film processing step of a third embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 wiring layer 3 processed layer (SiN layer) 4 organic silicon layer 4 ′ silicon oxide layer 5 resist pattern 21 vacuum chamber 22 processed object 23 mounting table 24 counter electrode 25 ... gas inlet pipe 26 ... exhaust port 27 ... high-frequency electrode 28 ... magnets 31 ... silicon substrate 32 ... thermal oxide layer 33 ... polysilicon layer 34 ... WSi layer 35 ... SiN layer 36 ... polysilane 36 '... SiO ₂ layer 37 ... resist layer 38 ... interlayer insulation film 41 ... silicon substrate 42, 42 '... interlayer insulating layer 43 ... wiring material (layer) 44 ... SiN layer 45 ... polysilane 45' ... SiO ₂ layer 46 ... resist layer 61 ... silicon substrate 62 ... interlayer insulating layer 63 ... carbon layer 64 ... polysilane 64 '... SiO ₂ layer 65 ... resist layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 4M104 AA01 BB01 CC05 DD02 DD07 DD16 DD20 DD62 DD71 EE05 EE14 EE17 FF14 5F004 AA04 BA13 BA14 BA19 BB13 BB14 BD01 BD03 DA00 DA01 DA04 DA26 DA29 DB00 DB02 DB03 DB07 DB17 EA23 EB01 5H04H HH09 HH17 HH19 HH28 JJ04 JJ08 JJ09 JJ17 JJ19 JJ28 KK04 KK08 KK09 KK17 KK19 KK28 MM15 NN16 NN40 QQ04 QQ08 QQ09 QQ10 QQ12 QQ13 QQ25 QQ26 QQ28 QQ37 QQ48 QQ49 QQ60 QQ63 QQ89 RR04 RR06 RR09 RR22 RR23 RR25 SS11 SS21 SS25 VV06

Claims (4)

[Claims] 1. A step of forming an organic silicon layer containing an organic silicon compound on a layer to be processed, a step of patterning the organic silicon layer, and a step of etching the layer to be processed using the organic silicon layer as a mask. And a step of supplying oxygen ions or radicals to the organic silicon layer to form a silicon oxide layer. 2. The method according to claim 1, further comprising etching using the silicon oxide layer and the layer to be processed as a mask. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of performing etching using the silicon oxide layer and the layer to be processed as an etching stopper layer. 4. A step of forming an organic silicon layer containing an organic silicon compound on a layer to be processed comprising a carbon layer or a resist layer formed on an interlayer insulating film, and a step of patterning the organic silicon layer. Etching the layer to be processed using the organic silicon layer as a mask; supplying oxygen ions or radicals to the organic silicon layer to form a silicon oxide layer; and 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of etching the layer to be processed or the interlayer insulating film using the layer to be processed as a mask.