JPS58204558A - Wiring method - Google Patents

Wiring method

Info

Publication number
JPS58204558A
JPS58204558A JP8822482A JP8822482A JPS58204558A JP S58204558 A JPS58204558 A JP S58204558A JP 8822482 A JP8822482 A JP 8822482A JP 8822482 A JP8822482 A JP 8822482A JP S58204558 A JPS58204558 A JP S58204558A
Authority
JP
Japan
Prior art keywords
window
wiring
wirings
aluminum
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8822482A
Other languages
Japanese (ja)
Inventor
Shuji Asai
浅井 周二
Yukinori Kuroki
黒木 幸令
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8822482A priority Critical patent/JPS58204558A/en
Publication of JPS58204558A publication Critical patent/JPS58204558A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a good electric contact in an ultrafine electrode window by etching and opening a window at an interlayer insulating film on aluminum wirings with CF4 gas, treating it with O2 plasma, coating high melting point metal on the window, heating it. CONSTITUTION:After an SiO2 film 3 and a photoresist 4 are superposed on aluminum wirings 2 on an Si substrate 1, a window 5 is opened at the film 3 by a reactive sputter etching method of a parallel flat plate with gaseous CF4, fluoride polymer produced at the aluminum on the window 5 is ashed and removed. Then, Ti 6, Al 7 are continuously deposited. Wirings are formed by dry etching of CCl4, with the resist mask, the mask 4 is removed, heated in N2 gas, Ti is diffused in aluminum, the wirings 7 are conducted. According to this configuration, a good electric contact connection can be formed in the ultrafine electrode window.

Description

【発明の詳細な説明】 本発明は集積回路の多層配線の方法に関し、特にAIと
の良好な電気的接触を得る方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for multilayer interconnection of integrated circuits, and in particular to a method for obtaining good electrical contact with AI.

A1は、Auに次ぐ良′Wt導体であり、微細加工性も
よく、安価であるために、半導体や集積回路などの配線
金属として用いられている。しかし、Alは空気中の水
分や水を用いた処理などにより表面に数百Aのアルミナ
層が生じ、アルミナは不導通のため金属をただ接触させ
ただけでは接触抵抗が大きい。そこで集積回路において
、AI配線上の層間絶縁膜S10.にスルーホールをバ
ッファド弗酸液で開口し C,%Ti、Moなどの高融
点金属を介してムl配線を形成し、約300℃以上で熱
処理をすれば、高融点金属がアルミナ層中に拡散し、数
μm角と小さいスルーホールでも接触抵抗lΩΩトドな
り良好な導通が得られる。
A1 is a good Wt conductor next to Au, has good microfabricability, and is inexpensive, so it is used as a wiring metal for semiconductors, integrated circuits, and the like. However, when Al is treated with moisture in the air or water, an alumina layer of several hundred amperes is formed on the surface, and since alumina is non-conductive, contact resistance is large when metals are simply brought into contact. Therefore, in an integrated circuit, an interlayer insulating film S10. By opening through holes in the alumina layer with a buffered hydrofluoric acid solution and forming mulch wiring through high melting point metals such as C, %Ti, Mo, etc., and heat-treating at about 300°C or higher, the high melting point metals will form in the alumina layer. The contact resistance is 1ΩΩ and good conductivity can be obtained even with a small through hole of several μm square.

・しかしながら、バッファド弗酸液ではナイドエツチン
グ太き(高集積化には適さない。そこで、サイドエツチ
ングを小さく、正確に数μm角のスルーホールを開口す
るために、CF4ガスによるリアクティブスパッタエツ
チングにより開口して前記のように配線したが、同様な
よい導通は得られないことが分った。熱処理をしても接
触抵抗の降下が遅くばらつきが大きい。そして、確実に
開口しようとしてドライエツチング時間を長くするほど
、この傾向は顕著になる。
・However, with buffered hydrofluoric acid solution, the side etching is too thick (not suitable for high integration. Therefore, in order to reduce the side etching and accurately open through holes of several μm square, reactive sputter etching using CF4 gas is used. Although I made an opening and wired it as described above, I found that I could not obtain the same good conduction.Even with heat treatment, the contact resistance decreased slowly and had large variations.In order to ensure the opening, I tried dry etching. This tendency becomes more pronounced as the time increases.

導通が得にくい原因を調べるために、長時間ドライエツ
チングしたものについでスルーポール下のA1表面をオ
ージェ分析などにより調べてみると、A1表面にF%C
,OlHなどの堆積物があることが分った。AtはCF
、ガスでエツチングされないため、8i0tを開口する
ときのマスクであるホトレジストとCF4ガスの反応し
重合化した喀)のがAt上に堆積していることが考えら
れ、これが高融点金属のAIへの拡散を妨げているよう
である。
In order to investigate the reason why it is difficult to obtain conductivity, we investigated the A1 surface under the through pole by Auger analysis after dry etching for a long time, and found that F%C was found on the A1 surface.
It was found that there were deposits such as , OlH, etc. At is CF
Since it is not etched by the gas, it is thought that the photoresist used as a mask when opening the 8i0t is reacted and polymerized by the CF4 gas, which is deposited on the At. It appears to be preventing its spread.

本発明の目的は、以上のような欠点に鑑み、接触面積が
数μm角と小さくてもAIとの良好な電気的接触を得る
ことが可能な配線方法を提供することにある。
SUMMARY OF THE INVENTION In view of the above drawbacks, an object of the present invention is to provide a wiring method that can obtain good electrical contact with AI even if the contact area is as small as several μm square.

基板上にA1配線を形成し、該AI配線を含む全面に層
間絶縁膜を形成した後、前記A+配線上の所定部分の層
間絶縁膜を弗化炭素系ガスを用いたドライエツチングに
より開口し、鹸素プラズマ処理を行い該開口に高融点金
属を被着し、配線を形成し、’、Ill、’、’、l。
After forming an A1 wiring on a substrate and forming an interlayer insulating film on the entire surface including the AI wiring, opening a predetermined portion of the interlayer insulating film on the A+ wiring by dry etching using a carbon fluoride gas; A high-melting point metal is applied to the opening by saponium plasma treatment, and wiring is formed.',Ill,',',l.

加熱する工程を有することを蒔徴とする配線方法。A wiring method that includes a heating process.

以下、本@明についての実施例を図面を用いて説明する
Examples of this @ Ming will be described below with reference to the drawings.

第1図〜第7図は、本発明の一実施例を説明するだめの
図である。第1図のようにSi窒化膜で全面が被覆され
た8i基板1の上にAIを0.3μm蒸着し、ホトレジ
スト膜マスクをしてCCl4  ドライエツチングしA
1配線2を形成し、ホトレジスト膜を除去し、第2図の
ように全面に層間絶縁膜として1fiiO,3を厚さ0
.4μm気相成長し、第3図のように2μm角の開ロバ
ターン5のあるホトレジスト膜4を形成し、第4図のよ
うにCF4ガスを用いて平行半板リアクティブスパッタ
エツチングによりガス圧100mtorr、高周波電力
100W約5分間で8i0.J[3に開口5を設け、第
5図のようにエツチングガスを酸素0.に変えてガス圧
200 mtorr 。
1 to 7 are diagrams for explaining one embodiment of the present invention. As shown in Fig. 1, AI was deposited to a thickness of 0.3 μm on the 8i substrate 1 whose entire surface was covered with a Si nitride film, and CCl4 dry etching was performed using a photoresist film mask.
1 wiring 2 is formed, the photoresist film is removed, and 1fiiO,3 is deposited on the entire surface as an interlayer insulating film with a thickness of 0.
.. A photoresist film 4 with an open pattern 5 of 2 μm square as shown in FIG. 3 is formed by vapor phase growth of 4 μm, and as shown in FIG. 8i0. An opening 5 is provided in J[3, and as shown in FIG. The gas pressure was changed to 200 mtorr.

高周波電力100W、約10分間でホトレジスト膜4と
開口5のAt上に生じた弗化重合物を灰化して除去し、
第6図のようにTi6とAt 7を厚さ0.21 μmと0.5μmと連続して蒸着し、第7図のように1
)Lz&X、I[y爲□゛:・MrCCl、 ’f5イ
エ、ヶングにより配線を形成しホトレジスト膜を除去し
、窒素雰囲気中で350℃(9)分間加熱してTiをA
t中へ熱拡散させることにより配線を導通させることが
できる。
The fluorinated polymer produced on the photoresist film 4 and the At of the opening 5 is incinerated and removed using a high frequency power of 100 W for about 10 minutes.
As shown in Figure 6, Ti6 and At7 were successively deposited to a thickness of 0.21 μm and 0.5 μm, and as shown in Figure 7,
) Lz &
The wiring can be made electrically conductive by diffusing heat into the t.

2μmμmシスルーホール抗値は、熱処理前では数十Ω
〜数にΩまでばらついているが、350℃で約15分の
熱処理により10以下になる。350℃で加分熱処理し
たものの一例として、1枚のウェハにつき100点で(
資)枚のウェハについて測定した抵抗値は0.32±0
.12J] (95%分布限界)テアリ、抵抗値とばら
つき共に非常に小さくなる。また、CF4で開口しホト
レジスト膜をばくり液で除去したものでは、350℃加
分の熱処理で数Ω〜数十〇であり、10以下になるまで
1こは1時間以上の熱処理が必要となり、スルーホール
抵抗の下がり方は遅くなる。
The resistance value of 2 μm μm through hole is several tens of Ω before heat treatment.
Although it varies from Ω to Ω, it becomes less than 10 after heat treatment at 350°C for about 15 minutes. As an example of a product heat-treated at 350°C, 100 points per wafer (
The resistance value measured for two wafers was 0.32±0.
.. 12J] (95% distribution limit) Tearing, resistance value, and variation are both extremely small. In addition, when the photoresist film is opened with CF4 and the photoresist film is removed with a stripping solution, the resistance is several ohms to several tens of ohms after heat treatment at 350°C, and heat treatment for one hour or more is required to reduce the resistance to 10 or less. , the through-hole resistance decreases more slowly.

このような本発明によれば、スルーホールが2μm角と
小さくても、スルーホール抵抗は10以下になり、抵抗
値とばらつき共に小さく、従来では得られなかった値で
あることからも本発明の効果は明らかである。
According to the present invention, even if the through hole is as small as 2 μm square, the through hole resistance is 10 or less, and both the resistance value and the variation are small, which is a value that could not be obtained in the past. The effect is clear.

実施例では、弗化炭素ガスとしてCF、を用いたが、C
HF、、 c、ps、C5F’aなどであってもよい。
In the examples, CF was used as the carbon fluoride gas, but C
It may be HF, c, ps, C5F'a, etc.

また、実施例では、酸素プラズマ処理を開口を同じリア
クティブスパッタエソチングでおこなったが、一般的な
円筒型プラズマエツチングであってもよい。
Further, in the embodiment, the oxygen plasma treatment was performed using the same reactive sputter etching to form the openings, but general cylindrical plasma etching may be used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第7図はAIとの電気的接触を得る本発明の詳
細な説明するための図である。図においてlは、絶縁さ
れた基板、2は第1層AI配線、3は層間絶縁膜sio
、、4はホトレジスト膜、5は開口(スルーホール)、
6は高融点金属、7は第2層AI配線である。
1 to 7 are diagrams for explaining in detail the present invention for obtaining electrical contact with AI. In the figure, l is an insulated substrate, 2 is a first layer AI wiring, and 3 is an interlayer insulating film sio.
,, 4 is a photoresist film, 5 is an opening (through hole),
6 is a high melting point metal, and 7 is a second layer AI wiring.

Claims (1)

【特許請求の範囲】[Claims] 基板上にAI配線を形成し、該A1配線を含む全面に層
間絶縁膜を形成した後、前記AI配線上の所定部分の層
間絶縁膜を弗化炭素糸ガスを用いたドライエツチングに
より開口し、酸素プラズマ処理を行い該開口に高融点金
属を被着し、配線を形成し、加熱する工程を有すること
を%黴とする配線方法。
After forming an AI wiring on a substrate and forming an interlayer insulating film on the entire surface including the A1 wiring, opening the interlayer insulating film at a predetermined portion on the AI wiring by dry etching using fluorocarbon thread gas, A wiring method that includes the steps of applying oxygen plasma treatment, depositing a high melting point metal on the opening, forming wiring, and heating.
JP8822482A 1982-05-25 1982-05-25 Wiring method Pending JPS58204558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8822482A JPS58204558A (en) 1982-05-25 1982-05-25 Wiring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8822482A JPS58204558A (en) 1982-05-25 1982-05-25 Wiring method

Publications (1)

Publication Number Publication Date
JPS58204558A true JPS58204558A (en) 1983-11-29

Family

ID=13936896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8822482A Pending JPS58204558A (en) 1982-05-25 1982-05-25 Wiring method

Country Status (1)

Country Link
JP (1) JPS58204558A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61152042A (en) * 1984-12-20 1986-07-10 エツセ・ジ・エツセ・ミクロエレツトロニーカ・エツセ・ピ・ア Metalization pattern of semiconductor element and method thereof
JPS6260240A (en) * 1985-09-10 1987-03-16 Matsushita Electric Ind Co Ltd Multilayer interconnection
JPS63287019A (en) * 1987-05-19 1988-11-24 Nec Corp Manufacture of semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61152042A (en) * 1984-12-20 1986-07-10 エツセ・ジ・エツセ・ミクロエレツトロニーカ・エツセ・ピ・ア Metalization pattern of semiconductor element and method thereof
JPS6260240A (en) * 1985-09-10 1987-03-16 Matsushita Electric Ind Co Ltd Multilayer interconnection
JPS63287019A (en) * 1987-05-19 1988-11-24 Nec Corp Manufacture of semiconductor device

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