JPS61113259A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS61113259A
JPS61113259A JP23554684A JP23554684A JPS61113259A JP S61113259 A JPS61113259 A JP S61113259A JP 23554684 A JP23554684 A JP 23554684A JP 23554684 A JP23554684 A JP 23554684A JP S61113259 A JPS61113259 A JP S61113259A
Authority
JP
Japan
Prior art keywords
film
plasma
resist
plasma cvd
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23554684A
Other languages
Japanese (ja)
Inventor
Mikio Takebayashi
幹男 竹林
Yoichi Onishi
陽一 大西
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP23554684A priority Critical patent/JPS61113259A/en
Publication of JPS61113259A publication Critical patent/JPS61113259A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable to prevent he generation of pinholes in the plasma CVD film by a method wherein the protrusion part on the surface of the substrate, whereon the plasma CVD film is formed, is removed by performing a dry etching using an etchback method and the surface of the substrate is flattened. CONSTITUTION:When a silicon oxide film 12 and an Al wiring layer 13 are formed on a substrate 11, a protrusion 13a to be called a hillock is generated. A resist 16 is applied over the whole surface of the Al wiring layer 13. Then, a dry etching is performed on the resist 16 and the protrusion 13a by an etchback method and a flattening of the Al wiring layer 13 is performed. Accordingly, when a plasma SiN film 14 is formed on the Al wiring layer 13 by a plasma CVD method in the following process, the surface of the plasma SiN film 14 also becomes flat and a positive-type resist, which is used as a mask when an etching is performed on the plasma SiN film 14, can be applied on the whole surface of the plasma SiN film 4 without exception. By said procedure, any pinhole is not generated in the plasma CVD film 14. As a result, the generation of failure such as short-circuit decreases sharply, and moreover, the moisture resisting characteristics, the insulation characteristics and the barrier characteristics to sodium ions and so forth are made to improve.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、プラズマcVD (Chemical Va
pourDepos i t i on )法によって
基材表面にプラズマCVD膜を形成する半導体装置の製
造方法に関し、特に、半導体装置における電気絶縁性、
耐湿性の向上、ナトリウムイオン(Na十)の侵入防止
を目的とした保護膜や多層配線構造の半導体装置におけ
る層間絶縁膜を形成するだめの方法に関するものである
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to plasma cVD (Chemical Vacuum
A method for manufacturing a semiconductor device in which a plasma CVD film is formed on the surface of a substrate by a pour deposition method, particularly for improving electrical insulation in a semiconductor device,
The present invention relates to a method for forming a protective film and an interlayer insulating film in a semiconductor device having a multilayer interconnection structure for the purpose of improving moisture resistance and preventing the intrusion of sodium ions (Na+).

従来例の構成とその問題点 第1図は従来の方法による半導体装置の製造工程を示す
断面図である。第1図(a)は、Al配線3を形成し、
Al配線3を安定化させるだめに熱処理を施した後の断
面を示すものであり、ところどころに1〜2μm程度の
ヒロックとよばれる突起3aが発生する。第1図(bl
は、Al配線3上にプラズマCVD法によって窒化シリ
コン膜4(以下プラズマSiN膜と略す)を形成した後
の断面を示すものである。ここで、プラズマCVD法は
、ステップカバレッジ(膜の被覆性)が良いため、前記
突起3aを完全に被覆する。第1図(C1は、プラズマ
SiN膜4上にレジスト5を塗布した図であるが、レジ
スト5は、スピンナーにて塗布するだめ突起3aの先端
部分に平坦部と同様の膜厚でレジストを塗布することが
困難である。次にレジスト5を露光並びに現像した後、
レジスト5をマスクにしてコンタクトホールを開けるた
めに、プラズマSiN膜4のドライエツチングを行なう
Structure of the Conventional Example and Its Problems FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device by a conventional method. In FIG. 1(a), an Al wiring 3 is formed,
This shows a cross section after heat treatment has been applied to the Al wiring 3 in order to stabilize it, and protrusions 3a called hillocks of about 1 to 2 μm are generated here and there. Figure 1 (bl
1 shows a cross section after forming a silicon nitride film 4 (hereinafter abbreviated as plasma SiN film) on Al wiring 3 by plasma CVD method. Here, since the plasma CVD method has good step coverage (film coverage), the projections 3a are completely covered. FIG. 1 (C1 is a diagram showing the resist 5 applied on the plasma SiN film 4. The resist 5 is applied with a spinner, but the resist is applied to the tip of the protrusion 3a with the same film thickness as the flat part. Next, after exposing and developing the resist 5,
Dry etching of the plasma SiN film 4 is performed using the resist 5 as a mask to open a contact hole.

しかしながら、前述のように突起3aの先端は、レジス
ト5の膜厚が薄いまたは塗布されないため第1図(d)
のように突起3a先端部分のプラズマSiN膜4がエツ
チング除去されピンホールとなる。以下レジスト4を除
去し、第2層目のAl配線を行なうが、ピンホールがあ
ると第1層目のAl配線3と第2層目のAl配線を絶縁
することができずショート不良の原因となる。
However, as mentioned above, the tip of the protrusion 3a has a thin film of resist 5 or is not coated, so the tip of the protrusion 3a is
The plasma SiN film 4 at the tip of the protrusion 3a is etched away to form a pinhole as shown in FIG. After that, the resist 4 is removed and the second layer of Al wiring is performed, but if there is a pinhole, the first layer of Al wiring 3 and the second layer of Al wiring cannot be insulated, causing a short circuit. becomes.

このように従来の製造方法では、Al配線の表面の平坦
化を行なわずに処理していたため、Al配線3上に生ず
る突起3a共に起因して、プラダ−r S iN膜4に
ピンホールが生じ、その結果、多層配線構造の半導体装
置にこのプロセスを適用した場合、ショート不良の原因
となシ、製造歩留りの低下をまねき、生産性を悪化させ
る。また半導体装置の保護膜に適用した場合、半導体装
置の耐湿特性、絶縁特性、ナトリウムイオンのバリア特
性を劣化させ、半導体装置の信頼性を大巾に低減すると
いう欠点を有していた。
In this way, in the conventional manufacturing method, the surface of the Al wiring was processed without flattening, so pinholes were formed in the Prader-r SiN film 4 due to the protrusions 3a formed on the Al wiring 3. As a result, when this process is applied to a semiconductor device with a multilayer interconnection structure, it causes short-circuit defects, lowers manufacturing yield, and deteriorates productivity. Further, when applied to a protective film of a semiconductor device, it has the disadvantage that it deteriorates the moisture resistance properties, insulation properties, and sodium ion barrier properties of the semiconductor device, and greatly reduces the reliability of the semiconductor device.

発明の目的 本発明は上記欠点に鑑み、半導体装置におけるプラズマ
CVD膜のピンホール発生を防止することが可能となる
半導体装置の製造方法を提供するものである。
OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a method for manufacturing a semiconductor device that makes it possible to prevent the occurrence of pinholes in a plasma CVD film in a semiconductor device.

発明の構成 本発明は、プラズマ(、VD膜を形成する基材表面の突
起部をエッチバック法を用いドライエツチング法によっ
て除去して、基材表面の平坦化を行なった後、基材にプ
ラズマCVD膜を形成することによって、後工程のレジ
ストを塗布する際に均一に塗布することができ、その結
果、プラズマCVD膜内のピンホールの発生を防止し1
シヨート不良を低減、並びに、耐湿特性、絶縁特性、ナ
トリウムイオン等のバリア特性を向上させ、半導体装置
の製造歩留りを向上することを可能にするという特有の
効果を有する。
Structure of the Invention The present invention is a method of flattening the surface of a substrate by removing protrusions on the surface of the substrate on which a VD film is to be formed using an etch-back method and dry etching, and then applying plasma to the substrate. By forming a CVD film, it is possible to apply the resist uniformly in the subsequent process, and as a result, the generation of pinholes in the plasma CVD film can be prevented.
It has the unique effect of reducing shot defects, improving moisture resistance properties, insulation properties, barrier properties against sodium ions, etc., and making it possible to improve the manufacturing yield of semiconductor devices.

実施例の説明 以下、本発明の一実施例について、図面を参照しながら
説明する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

第2図は、本発明の一実施例における半導体装置の製造
方法を示す各工程の断面図である。
FIG. 2 is a cross-sectional view of each step showing a method for manufacturing a semiconductor device in an embodiment of the present invention.

!2図において、11は材質がシリコンの基板、12は
熱処理により基板11の表面を酸化させた厚さが約50
00への酸化シリコン膜、13はスパッタリング法で形
成した、材質がアルミニウムで厚さが約1μmの導体薄
膜であシ、フォトフアプリケーション工程にて薄膜導体
回路に加工された後、酸化シリコン膜12との密着性の
向上並びに薄膜導体回路の安定化のため、約400’C
の雰囲気炉で熱処理されたA7?配線である。13aは
熱処理後にAl配線13の表面に生じるヒロックとよば
れる突起、14は材質が窒化シリコンであるプラズマS
iN膜、16は、突起13aをエッチバック法によって
除去し、AA’配線13の表面を平坦化するために用い
る厚さ約3μmのポジ型のレジストである。ここでエッ
チバック法とは、レジスト16と突起13a両材質のエ
ツチング速度をほぼ同じくし、すなわち、エツチング選
択比を約1としてエツチングすることにより、突起13
aを除去する方法である。
! In Figure 2, 11 is a substrate made of silicon, and 12 is a substrate whose surface is oxidized by heat treatment and has a thickness of approximately 50 mm.
A silicon oxide film 13 is formed by a sputtering method and is made of aluminum and has a thickness of about 1 μm. After being processed into a thin film conductor circuit in a photo application process, the silicon oxide film 12 Approximately 400'C in order to improve adhesion and stabilize the thin film conductor circuit.
A7 heat treated in an atmospheric furnace? It's the wiring. 13a is a protrusion called a hillock formed on the surface of the Al wiring 13 after heat treatment, and 14 is a plasma S made of silicon nitride.
The iN film 16 is a positive resist with a thickness of approximately 3 μm used to remove the protrusion 13a by an etch-back method and planarize the surface of the AA' wiring 13. Here, the etch-back method means that the resist 16 and the protrusion 13a are etched at approximately the same etching speed, that is, the etching selection ratio is approximately 1.
This is a method of removing a.

第2図(a)は、基板11に酸化シリコン膜、Al配線
13を形成した後、熱処理した後の断面を示す図である
。ヒロックとよばれる突起13aは、平均1.8μmの
高さであった。第2図(b)は、レジスト16をスピン
ナーで3μm程度塗布した後の断面を表わす図であり、
Al配線13面は、突起13aを含めて全面に渡シレジ
スト16が塗布されている。次に、レジスト16と突起
13aのエツチング速度をほぼ同じくし、すなわち、エ
ツチング選択比を約1となるエツチング条件にてドライ
エツチングを行う。本実施例では、平行平板電極型のド
ライエツチング装置を用い、四塩化炭素(CC14)と
酸素(o2)との混合ガスの低温プラズマにてドライエ
ツチングし、ドライエツチング後すぐに水洗を行なった
。なお、高周波電力の周波数は13.56MH2の電源
を用いた一上記エッチバック法を実施した後の断面を第
2図(c)に示す。
FIG. 2(a) is a diagram showing a cross section after a silicon oxide film and an Al wiring 13 are formed on the substrate 11 and then heat-treated. The protrusions 13a called hillocks had an average height of 1.8 μm. FIG. 2(b) is a diagram showing a cross section after applying the resist 16 to a thickness of about 3 μm using a spinner.
A cross-sectional resist 16 is applied to the entire surface of the Al wiring 13 including the protrusions 13a. Next, dry etching is performed under etching conditions such that the etching speed of the resist 16 and the protrusion 13a are approximately the same, that is, the etching selection ratio is approximately 1. In this example, a parallel plate electrode type dry etching apparatus was used, and dry etching was performed with low temperature plasma of a mixed gas of carbon tetrachloride (CC14) and oxygen (O2), and water washing was performed immediately after dry etching. Note that FIG. 2(c) shows a cross section after performing the above-mentioned etch-back method using a power source with a high frequency power frequency of 13.56 MH2.

これによって、l配線13の平坦化がなされた。As a result, the l wiring 13 was flattened.

従って、次に第2図(cl)のようにAl配線13上に
プラズマCVD法でプラズマSiN膜を形成した場合、
プラズマSiN膜14の表面も平坦になる。
Therefore, if a plasma SiN film is then formed on the Al wiring 13 by the plasma CVD method as shown in FIG. 2 (cl),
The surface of the plasma SiN film 14 also becomes flat.

従って、コンタクトウィンドーを形成する際、プ2ズマ
SfN膜14のエツチングを実施するためマスクとなる
有機材料すなわち、ポジ型のレジ2トを全面にもれなく
塗布することが可能となるkめ、プラズマCVD膜14
内のピンホールの発住がなく、その結果、ショート不良
か激減し、さらに耐湿特性、絶縁特性、ナト17ウムイ
オン等のノリア特性が向上し、半導体装置の製造歩留り
を向上することができた。
Therefore, when forming a contact window, it is possible to completely coat the entire surface with an organic material that serves as a mask for etching the plasma SfN film 14, that is, a positive resist. CVD film 14
As a result, the number of short-circuit defects was drastically reduced, and the moisture resistance, insulation properties, and nitrogen properties such as sodium 17ium ions were improved, and the manufacturing yield of semiconductor devices was improved.

なお、本実施例では、Al配線13の材質をアルミニウ
ムとしたが、微小量(3%以内)の少なくともシリコン
を含むアルミニウム合金としても良い。また、本実施例
では、突起13aが、熱処理によって生じるヒロックに
起因するものとしたが、アルミニウム薄膜をスパッタリ
ング法で形成する際にクラスタ等に起因した、アルミニ
ウム薄膜表面の荒れに起因するものであっても良い。
In this embodiment, the material of the Al wiring 13 is aluminum, but it may be an aluminum alloy containing at least a small amount (within 3%) of silicon. Furthermore, in this embodiment, the protrusions 13a are caused by hillocks generated by heat treatment, but they may also be caused by roughness on the surface of the aluminum thin film caused by clusters or the like when forming the aluminum thin film by sputtering. It's okay.

なお、本実施例では、スパッタリング法にてアルミニウ
ム薄膜を形成したが、真空蒸着法、イオンブレーティン
グ法によって形成しても良い。
In this example, the aluminum thin film was formed by a sputtering method, but it may also be formed by a vacuum evaporation method or an ion blating method.

また、本実施例ではプラズマCVD法で窒化シの いるレジストの材質をポジ型としたが、ネガ型レジスト
としても良い。
Furthermore, in this embodiment, the material of the resist containing nitride was made positive by the plasma CVD method, but it may be made of a negative resist.

発明の効果 以上のように本発明によれば、プラズマCVD1   
膜を形成させる基材表面の突起部分をエッチバック法に
よって除去した後プラズマCVD膜の形成を行なうこと
により、プラズマCVD膜のピンホール発生を減少させ
ることができる。その結果、半導体装置のシミh不良が
低減し、並びに耐湿特性、絶縁特性、ナトリウムイオン
等のバリア特性を向上させ、半導体装置の製造歩留りを
大巾に向上することができ、その実用的効果は犬なるも
のがある。
Effects of the Invention As described above, according to the present invention, plasma CVD1
By forming the plasma CVD film after removing the protrusions on the surface of the base material on which the film is to be formed by an etch-back method, it is possible to reduce the occurrence of pinholes in the plasma CVD film. As a result, it is possible to reduce stain h defects in semiconductor devices, improve moisture resistance properties, insulation properties, barrier properties such as sodium ions, and greatly improve the manufacturing yield of semiconductor devices.The practical effects are as follows: There is something called a dog.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、従来の半導体装置の製造方法を示す工程毎の
断面図、第2図は本発明による半導体装置の製造方法を
示す工程毎の断面図である。 11・・・・・・シリコンJIS、12・・・・・・酸
化シリコン膜、13・・・・・・Al配線、14・・・
・・・プラズマ5iNli、16・・山・レジスト、1
3a・・・・・・突起。 代理人の氏名 弁理士 中 尾 敏 男 はが1名第1
FIG. 1 is a cross-sectional view of each step showing a conventional method of manufacturing a semiconductor device, and FIG. 2 is a cross-sectional view of each step of a method of manufacturing a semiconductor device according to the present invention. 11...Silicon JIS, 12...Silicon oxide film, 13...Al wiring, 14...
...Plasma 5iNli, 16...Mountain/Resist, 1
3a... Protrusion. Name of agent: Patent attorney Toshio Nakao (1st person)
figure

Claims (1)

【特許請求の範囲】[Claims]  基材にプラズマCVD膜を形成する際、基材表面の突
起部をエッチバック法を用いドライエッチングによって
除去することにより基材表面の平坦化を行なった後、前
記基材にプラズマCVD膜を形成する工程を施す半導体
装置の製造方法。
When forming a plasma CVD film on a base material, the protrusions on the surface of the base material are removed by dry etching using an etch-back method to flatten the surface of the base material, and then a plasma CVD film is formed on the base material. A method for manufacturing a semiconductor device that includes a process of
JP23554684A 1984-11-08 1984-11-08 Manufacture of semiconductor device Pending JPS61113259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23554684A JPS61113259A (en) 1984-11-08 1984-11-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23554684A JPS61113259A (en) 1984-11-08 1984-11-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS61113259A true JPS61113259A (en) 1986-05-31

Family

ID=16987579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23554684A Pending JPS61113259A (en) 1984-11-08 1984-11-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS61113259A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104026A (en) * 1986-10-21 1988-05-09 Nec Corp Manufacture of liquid crystal display device
KR100434031B1 (en) * 1996-12-30 2004-09-04 주식회사 하이닉스반도체 Method of manufacturing ferroelectric capacitor of semiconductor device to prevent hillock

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63104026A (en) * 1986-10-21 1988-05-09 Nec Corp Manufacture of liquid crystal display device
KR100434031B1 (en) * 1996-12-30 2004-09-04 주식회사 하이닉스반도체 Method of manufacturing ferroelectric capacitor of semiconductor device to prevent hillock

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