JPH03185823A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the generation of pin holes, improve heat resistance, and obstruct the punchthrough of low melting point metal, by filling a contact hole formed in the interlayer insulating film on a semiconductor substrate with polycrystalline silicon, and forming a barrier metal layer thereon by reactive sputtering while applying a bias voltage to the semiconductor substrate. CONSTITUTION:An interlayer insulating film 3A is formed by laminating the following in order on a semiconductor substrate 1 provided with a diffusion layer 2; a silicon oxide film 13, a spin-on-glass film 14, and a phosphorus silicate glass film 15. A contact hole 4 is formed in the layer 3A; a natural oxide film 11 and damaged parts are eliminated by chemical dry etching; and then polycrystalline silicon 5 is buried in the contact hole. The whole part is etched back by reactive ion etching; the polycrystalline silicon is left only in the contact hole 4 and a plug 6 is formed; and a natural oxide film 18 on the upper surface is again eliminated by chemical dry etching. While an RF bias 40 is applied to the semiconductor substrate 1, reactive sputtering is performed, thereby forming a barrier metal layer 9 and depositing a low melting point metal layer 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, particularly a method for removing a natural oxide film between a base exposed in a contact hole and polycrystalline silicon buried in the contact hole; The present invention also relates to a method for forming a barrier metal layer.

[Summary of the Invention] The present invention provides a method for manufacturing a semiconductor device having a wiring structure made of polycrystalline silicon buried in a contact hole and a low-melting point metal, in which the underlying layer exposed at the bottom of the contact hole is removed by chemical dry etching. While removing the natural oxide film and the autothermal oxide film on the top surface of the polycrystalline silicon buried in the contact hole, a barrier metal layer is formed on the polycrystalline silicon by reactive sputtering while applying a bias to the semiconductor substrate. By forming a low melting point metal layer on top of the layer, it is possible to remove the natural oxide film with good workability without causing damage to the base, side attack of the contact hole, or enlargement of the hole diameter, while improving the heat resistance of the barrier metal layer. This is something that can be improved.

[Prior Art] In the manufacturing method of semiconductor devices such as LSI and ULSI, as shown in Publication No. 81-6698, the diameter of contact holes has become smaller due to miniaturization of design rules. Since the aspect ratio of contact holes tends to increase, a plug method is known in which contact holes are filled with good step coverage. This will be illustrated and explained in FIG.

■As shown in FIG. 3(A), an interlayer insulating film 3 formed on a semiconductor substrate l such as a silicon (St) substrate l having a diffusion layer 2 has a Using the resist pattern as a mask, reactive ion etching is performed until the diffusion layer 2 is exposed, thereby forming a contact hole 4.

■As shown in Figure 3 (B), low pressure CVD (LPGV
D), polycrystalline silicon (PolySi) 5 is deposited over the entire surface of interlayer insulating film 3, and contact hole 4 is filled with polycrystalline silicon 5.

■As shown in FIG. 3(C), the entire surface of the polycrystalline silicon 5 is etched back by reactive ion etching to form a plug 6 leaving polycrystalline silicon only in the contact hole 4. A dopant is injected into the plug 6, and the plug 6 is activated by short-time annealing.

■As shown in Figure 3 (D), a titanium (Ti) film of 7° titanium nitride (TiN) or titanium oxynitride (TiOx) is formed by reactive sputtering without bias.
A barrier metal layer 9 such as Ny) film 8 and a low melting point metal layer 10 of aluminum (AI) are sequentially deposited. As a result, a wiring structure made of polycrystalline silicon buried in the contact hole 4 and a low melting point metal is formed on the semiconductor substrate 1.

[Problem to be Solved by the Invention 1] In the step (2) described above, as shown in FIG. is formed. For this reason, as a pretreatment for (2), the semiconductor substrate 1 on which the contact hole 4 has been formed is immersed for about 15 seconds in diluted hydrofluoric acid prepared by diluting hydrofluoric acid I with 100% pure water, so that the diffusion layer 1 The natural oxide film 11 formed on the upper surface is removed, and the upper surface of the diffusion layer 2 from which the natural oxide film 11 has been removed is coated with hydrofluoric acid to make the surface texture difficult for the natural oxide film 11 to form. Also, in the process of ■,
Since damage 12 such as crystal defects occurs in the diffusion layer 2 exposed at the bottom of the contact hole 4 due to ion bombardment during ion etching, after light etching with dilute hydrofluoric acid, which is the pretreatment in step ① above, the above-mentioned process is performed. The damage 12 is removed by removing the upper surface of the diffusion layer 2 from which the natural oxide film 11 has been removed by wet etching using a different etchant.

By the way, for the purpose of planarizing the interlayer insulating film 3, the fourth
As shown in the figure, a thermal oxide film 13 made of silicon oxide (Sins) is formed sequentially from the semiconductor substrate 1 side. Spin-on glass (SOG) film 14. Phosphorsilicate glass (PS
G) A thermal oxide film 13 formed of a film 15 or formed sequentially from the semiconductor substrate l side as shown in FIG. There is a tendency to use a boron silicate glass (BPSG) film 16.

For this reason, when the glabellar insulating film 3 shown in FIG. Side attack 17 enters the hole wall. Furthermore, when the interlayer insulating film 3 shown in FIG. 5 is pretreated with dilute hydrofluoric acid, the etching rate of the boron silicate glass film 16 with dilute hydrofluoric acid is fast, so the diameter of the contact hole 4 is significantly increased. This has the disadvantage of expanding to

On the other hand, in the above-mentioned step (2), since a natural oxide film 18 is formed on the upper surface of the plug 6 made of doped and activated polycrystalline silicon, the plug 6 is formed in the same dilute hydrofluoric acid as described above. 30 completed semiconductor substrates
By soaking for seconds, the natural oxide film 18 is removed, and the upper surface of the plug 6 from which the natural oxide film 18 has been removed is coated with hydrofluoric acid to make the surface texture difficult for the natural oxide film 18 to form.

Further, the upper surface of the plug 6 from which the natural oxide film 18 has been removed is
As shown in FIG. 6, the surface has fine irregularities reflecting the grain boundaries of polycrystalline silicon. For this reason,
When a barrier metal layer 9 such as a titanium film 7, titanium nitride or titanium oxynitride film 8 is deposited on the top surface of the plug 6, the barrier metal layer 9 does not adhere well to the recesses on the top surface of the plug 6 with good step coverage. , a portion having minute pinholes 19 is finally formed. The portion of this barrier metal layer 9 having the pinhole 19 is 40
Easily broken at a sintering temperature of about 0℃, low melting point metal layer 1
There is a problem that penetration of aluminum from zero to the diffusion layer 2 occurs.

[Means for Solving the Problems] Therefore, the first invention is to fill a contact hole formed in an insulating film between the eyebrows on a semiconductor substrate with polycrystalline silicon, and to sequentially form a barrier metal layer and a low melting point metal layer on this polycrystalline silicon. In the method for manufacturing a semiconductor device, the barrier metal layer is formed by reactive sputtering while applying a bias to the semiconductor substrate.

A second invention is a method for manufacturing a semiconductor device, which includes a step of filling a contact hole formed in an interlayer insulating film on a semiconductor substrate with polycrystalline silicon, and sequentially forming a barrier metal layer and a low melting point metal layer on the polycrystalline silicon. After forming the contact hole, the underlying natural oxide film exposed at the bottom of the contact hole is removed by chemical dry etching, the contact hole is immediately filled with polycrystalline silicon, and then the natural oxide film on the top surface of the polycrystalline silicon is removed by chemical dry etching. After removing by dry etching,
A barrier metal layer is formed on this polycrystalline silicon.

[Function] In the first invention, when forming a barrier metal layer, the evaporated atoms from the target are electrically pulled toward the semiconductor substrate side, so that the evaporated atoms form the concave portion of the upper surface of the polycrystalline silicon filled with the contact hole I. The barrier metal layer is also adhered with good step coverage to form a pinhole-free barrier metal layer.

In the second invention, when removing the natural oxide film of the base exposed in the contact hole and the polycrystalline silicon buried in the contact hole, the etching gas is turned into plasma by microwave irradiation without exposing the semiconductor substrate, In this plasma, an active gas is generated that has a low etching rate for the interlayer insulating film and a high etching rate for the silicon natural oxide film and the diffusion layer, and this active gas is uniformly irradiated onto the semiconductor substrate in the etching chamber. The active gas chemically reacts with the components of the natural oxide film and diffusion layer exposed at the bottom of the contact hole to generate volatile substances, thereby removing the natural oxide film and damaged parts of the underlying layer. do.

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, with the same reference numerals assigned to the same parts as those in the conventional structure described above.

In this embodiment, first, processing corresponding to the second invention is performed. That is, as shown in FIG. 1A, a glabellar insulating film 3A is formed to a thickness of, for example, 0.5 μm on a semiconductor substrate i such as a silicon (Sl) substrate having a diffusion layer 2. This interlayer insulating film 3A is formed from the silicon oxide film 13. Spin-on glass film 14. It is formed by sequentially stacking phosphosilicate glass films 15. Then, the interlayer insulating film 3A formed on the semiconductor substrate l is etched by reactive ion etching using a resist pattern (not shown) formed by photolithography as a mask until the diffusion layer 2 is exposed. For example, a contact hole 4 having a hole diameter of 0.6 μm is formed. In this reactive ion etching, a natural oxide film 11 is formed on the upper surface of the diffusion layer 2 exposed at the bottom of the contact hole 4, and damage 12, which is a crystal defect due to ion bombardment, is caused to a depth of several tens of layers. It is formed by

For this reason, after forming the contact hole 4, chemical dry etching is performed for about 30 seconds as shown in FIG. 1(B). Specifically, as shown in FIG. 2, after a semiconductor substrate l including an interlayer insulating film 3A and a contact hole 4 is placed in an etching chamber 30, an exhaust system is used to transport the semiconductor substrate l that communicates with the inside of the etching chamber 30. A vacuum atmosphere is formed in the tube 31 and the quartz tube 33 that communicates with the tube 33 and passes through the waveguide 32, and 30 SCCM of Freon (CP) gas is added to the quartz tube 33 as an etching gas Gl.
408 CCM of oxygen (O7) gas was supplied to the etching chamber 30. Transport pipe 31. The inside of the quartz tube 33 was set at 30 Pa, and the etching gas Gl introduced into the quartz tube 33 was
Microwaves generated by an applied power of 350 W are irradiated at the disposed portion of the waveguide 32 to form a plasma, and in this plasma an active gas G2 that contributes to etching is generated, and this active gas G2 is transferred from the transport pipe 31 A nozzle 3 that leads to the etching chamber 30 and communicates with the etching chamber 3I side of the transport pipe 31.
The active gas G is uniformly irradiated onto the semiconductor substrate l from
2 chemically reacts with the components of the natural oxide film 11 and the diffusion layer 2 exposed at the bottom of the contact hole 4 to generate a volatile substance G3, thereby preventing damage to the natural oxide film 11 and the diffusion layer 2. Etching is performed such that the parts are removed in one step. With this chemical dry etching,
The upper surface of the contact hole 4 including the natural oxide film 11 is etched to a depth of, for example, 20 to 30 nm, and the natural oxide film 11 and the damage are removed, and the exposed upper surface of the contact hole 4 is coated with fluorine, making it difficult to oxidize. becomes the surface texture. In this chemical dry etching,
Interlayer insulation g! Thermal oxide film 13 that constitutes 3A. Spin-on glass film 14. Since phosphosilicate glass G (15) has a low etching rate, problems such as side attack on the fourth contact hole and enlargement of the hole diameter do not occur.Furthermore, since the semiconductor substrate I is not exposed to plasma, no damage occurs.

Immediately after this, as shown in FIG. 1(C),
Polycrystalline silicon (Pol
yS i) 5 to the entire surface of the interlayer insulating film 3A, for example, 0.5μ.
The polycrystalline silicon 5 is deposited to a thickness of m to fill the contact hole 4 with polycrystalline silicon 5.

Then, as shown in FIG. 1(D), the entire surface of the polycrystalline silicon 5 is etch-packed by reactive ion etching to form a plug 6 leaving polycrystalline silicon only in the contact hole 4. For example, BFt
60KeV 1x10"cm-" or P"5
Dopants were implanted under the conditions of 0KeV lX10"am-" and further annealed at a temperature of 110
After activating the plug 6 by lamp annealing at 0°C for 10 seconds, the natural oxide film 18 attached to the top surface of the plug 6 is removed.
As shown in FIG. 1(E), it is removed again by chemical dry etching for 60 seconds.

Next, processing corresponding to the first invention is performed. That is, as shown in FIG. 1(F), a titanium film 7 is deposited to a thickness of 30 nm by reactive sputtering using argon (Ar) gas, and then the semiconductor substrate I is subjected to an RF bias of 40 nm.
6% oxygen (0,) in nitrogen (N,) while
A titanium oxynitride film 8 is deposited to a thickness of 70 nm by reactive sputtering while applying a power of 3 KW to a Ti target in a gas containing argon gas to form a barrier metal layer 9. Aluminum alloy (A
A low melting point metal layer 10 of I-8t) is deposited to a thickness of 300 nm.

Thereafter, although not shown, a titanium oxynitride film as an antireflection film for photolithography is deposited to a thickness of 30 nm by reactive sputtering without bias. Then, barrier metal layer 9 and low melting point metal layer 10
After forming a wiring pattern by pattern etching the wiring layer and anti-reflection film consisting of the above using a photolithographic resist pattern as a mask,
After the deposition of an interlayer insulating film, an upper wiring layer, a publicization film, etc. different from those mentioned above, opening of a bonding pad, and sintering heat treatment, one cycle of the wiring process is completed. As a result, a wiring structure consisting of the polycrystalline silicon buried in the contact hole 4 and the low melting point metal wiring is formed on the semiconductor substrate l.

Here, a sample was prepared in which the titanium oxynitride film 8 in the barrier metal layer 9 was formed by reactive sputtering without applying a bias.
Two samples were prepared, one in which the titanium oxynitride film 8 was formed by reactive sputtering with bias applied, and the other in which the titanium oxynitride film 8 was subjected to sinter heat treatment for 0 minutes.
When we verified the case of performing sinter heat treatment at 50°C for 120 minutes, it was found that in the sample without bias application, penetration of aluminum forming the low melting point metal layer 10 into the diffusion layer 2 occurred, but in the sample with bias application, penetration occurred into the diffusion layer 2. In the sample, no penetration of aluminum into the diffusion layer 2 occurred, and it was confirmed that the barrier metal layer 9 had excellent heat resistance.

Note that the present invention is not limited to the above embodiments,
Although not shown, for example, the interlayer insulating film may be composed of only the thermal oxide film 13 such as silicon oxide.

Also, instead of titanium oxynitride in the barrier metal layer, TiN, TiW, TiWN.

It can also be applied to WN etc.

Furthermore, as the low melting point metal layer, in addition to AI, Cu, W
It is also possible to use wiring materials such as.

[Effects of the Invention] As described above, according to the first invention, since the barrier metal layer is formed by reactive sputtering while applying a bias to the semiconductor substrate, evaporated atoms from the target are electrically transferred to the semiconductor substrate side. It adheres to the concave part of the top surface of the polycrystalline silicon that is pulled and buried in the contact hole with good step coverage, forming a pinhole-free barrier metal layer.Therefore, the heat resistance of the barrier metal layer is significantly improved, making it easy to use during sinter heat treatment. Penetration of low melting point metals can be prevented. .

According to the second invention, since the natural oxide film of the base exposed in the contact hole and the polycrystalline silicon buried in the contact hole is removed by chemical dry etching, it is not necessary to expose the semiconductor substrate to the etching gas. In this plasma, an active gas is generated that has a low etching rate for the interlayer insulating film and a high etching rate for the natural silicon oxide film and the diffusion layer, and this active gas is uniformly spread over the semiconductor substrate in the etching chamber. By irradiating the contact hole, the natural oxide film and the damaged portion of the diffusion layer can be removed with good workability without causing damage to the underlying layer, side attack of the contact hole, or enlargement of the hole diameter. Moreover, since the natural oxide film between the semiconductor substrate and the barrier metal layer is removed, ohmic contact in the wiring structure can be ensured.

[Brief explanation of drawings]

FIGS. 1(A) to (F) are cross-sectional views showing each processing step in an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a chemical dry etching apparatus of the same embodiment, and FIGS. 3(A) to (D) is a cross-sectional view showing each conventional processing step, FIG. 4 is a cross-sectional view showing a state in which a side attack is formed in a conventional contact hole, and FIG. 5 is a cross-sectional view showing a state in which a side attack is formed in a conventional contact hole. FIG. 6 is a sectional view showing a state in which a pinhole is formed in the conventional barrier metal layer. I... Semiconductor substrate, 2... Diffusion layer (base), 3.3
A... Interlayer insulating film, 4... Contact hole, 9...
...Barrier metal layer, lO...Low melting point metal layer, 11.
18... Natural oxide film, 12... Damage, 17...
・Side attack, 19...pinhole. 11 Contour 7 holes of 4 rows of oxidation order! Memunda Wh exemption episode Figure 1 C) Chemical Dry Etsuna published by Toragahii Lt is 1st page Figure 1 (E) Figure 1 (F) 11 Self-expense short - Tsuyoshi Fyoichi 1 Part 3 Diagram (D)

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device comprising the steps of filling a contact hole formed in an interlayer insulating film on a semiconductor substrate with polycrystalline silicon and sequentially forming a barrier metal layer and a low melting point metal layer on the polycrystalline silicon, A method for manufacturing a semiconductor device, characterized in that the barrier metal layer is formed by reactive sputtering while applying a bias to the semiconductor substrate. (2) A method for manufacturing a semiconductor device comprising the steps of filling a contact hole formed in an interlayer insulating film on a semiconductor substrate with polycrystalline silicon and sequentially forming a barrier metal layer and a low melting point metal layer on the polycrystalline silicon, After forming the contact hole, remove the underlying natural oxide film exposed at the bottom of the contact hole by chemical dry etching, immediately fill the contact hole with polycrystalline silicon, and then remove the natural oxide film on the top surface of the polycrystalline silicon by chemical dry etching. A method for manufacturing a semiconductor device, comprising forming a barrier metal layer on the polycrystalline silicon after removing the polycrystalline silicon.