KR100342827B1 - Method for forming barrier metal layer of semiconductor device - Google Patents
Method for forming barrier metal layer of semiconductor device Download PDFInfo
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- KR100342827B1 KR100342827B1 KR1019950025925A KR19950025925A KR100342827B1 KR 100342827 B1 KR100342827 B1 KR 100342827B1 KR 1019950025925 A KR1019950025925 A KR 1019950025925A KR 19950025925 A KR19950025925 A KR 19950025925A KR 100342827 B1 KR100342827 B1 KR 100342827B1
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 22
- 239000002184 metal Substances 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 20
- 239000010703 silicon Substances 0.000 claims abstract description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 19
- 239000001301 oxygen Substances 0.000 claims abstract description 17
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 15
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010936 titanium Substances 0.000 claims abstract description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 4
- 238000009413 insulation Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 abstract 1
- 229910001882 dioxygen Inorganic materials 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 230000003405 preventing effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005546 reactive sputtering Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 베리어 금속층 형성방법에 관한 것으로, 특히 실리콘기판과의 계면에 티타늄실리콘(TiSi2)층을 형성시키며 티타늄나이트라이드(TiN)층의 그레인(Grain) 사이에 산소(O2)를 충분히 충진시키므로써 소자의 신뢰성을 향상시킬 수 있도록 한 반도체 소자의 베리어 금속층 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a barrier metal layer of a semiconductor device, and in particular, forms a layer of titanium silicon (TiSi 2 ) at an interface with a silicon substrate, and provides oxygen (O 2 ) between grains of the titanium nitride (TiN) layer. The present invention relates to a method for forming a barrier metal layer of a semiconductor device, which is capable of improving the reliability of the device by sufficiently filling the P.
일반적으로 반도체 소자의 제조에 사용되는 베리어 금속(Barrier Metal)은실리콘기판에 형성된 접합영역에 알루미늄(Al)과 같은 금속이 접촉되는 경우 알루미늄(Al)과 실리콘(Si)의 상호 확산에 의해 발생되는 접합파괴(Junction Spiking) 현상을 방지하기 위하여 금속층을 형성하기 전에 증착하는 확산 방지용 금속이다. 그러므로 알루미늄 및 실리콘과의 반응성이 없어야 하고 고온에서 열적 안정성이 우수해야 하며, 또한 알루미늄, 실리콘 등에 대한 확산 억제 능력이 높고 실리콘과 저항성 접촉(Ohmic Contact)이 가능한 금속이어야 한다. 현재 이러한 베리어 금속으로는 티타늄(Ti)/티타늄나이트라이드(TiN)를 사용한다. 그러면 종래 반도체 소자의 베리어 금속층 형성방법을 설명하면 다음과 같다.In general, a barrier metal used in the manufacture of a semiconductor device is generated by mutual diffusion of aluminum (Al) and silicon (Si) when a metal such as aluminum (Al) contacts a junction region formed on a silicon substrate. It is a diffusion preventing metal deposited before forming a metal layer in order to prevent a junction spiking phenomenon. Therefore, it must be non-reactive with aluminum and silicon, have excellent thermal stability at high temperature, and be a metal with high diffusion suppression ability to aluminum, silicon, etc. and capable of ohmic contact with silicon. Currently, the barrier metal is titanium (Ti) / titanium nitride (TiN). The barrier metal layer forming method of the conventional semiconductor device will now be described.
종래에는 접합영역이 형성된 실리콘기판상에 절연층을 형성하고 상기 접합영역이 노출되도록 상기 절연층을 패터닝하여 콘택홀을 형성한 상태에서, 먼저 상기 접합영역과의 접촉저항을 감소시키며 상기 실리콘기판과의 접착성을 증가시키기 위하여 전체 상부면에 티타늄(Ti)을 증착한다. 이후 반응성 스퍼터링(Reactive Sputtering) 방법을 이용하여 상기 티타늄상에 티타늄나이트라이드(TiN)를 증착하고 확산 방지 효과를 증대시키기 위하여 열처리공정을 실시하여 베리어 금속층을 형성한다. 여기서 상기 열처리공정은 두가지 방법으로 구분된다. 첫째는 급속 열처리 장치를 이용한 열처리공정이고, 둘째는 반응로를 이용한 열처리공정이다. 그런데 상기 첫째의 방법을 이용하면 실리콘기판과의 계면에 티타늄실리콘(TiSi2)층을 형성하여 상부에 형성될 금속층과 상기 접합영역과의 접촉저항을 감소시킬 수는 있으나, 접합 파괴 현상을 방지하기는 어렵다. 반면에 둘째의 방법을 이용하면 티타늄니이트라이드의 그레인 사이에 산소를 충분히 충진시켜 접합 파괴 현상을 방지하는 데는 효과적이나, 열처리시 접합의 깊이가 증가되고 과도한 두께의 티타늄실리콘층을 형성하는 경우 접합영역에 존재하는 도펀트(Dopant)의 흡수로 인해 접촉저항이 증가되어 소자의 성능이 저하되는 단점이 있다. 그러므로 열처리 온도 및 시간에 많은 제약이 따른다.Conventionally, in the state where an insulating layer is formed on a silicon substrate on which a junction region is formed and a contact hole is formed by patterning the insulation layer so that the junction region is exposed, first, a contact resistance with the junction region is reduced, and In order to increase the adhesion of the titanium deposited on the entire upper surface (Ti). Thereafter, a titanium nitride layer (TiN) is deposited on the titanium using a reactive sputtering method and a heat treatment process is performed to increase the diffusion preventing effect to form a barrier metal layer. Here, the heat treatment process is divided into two methods. The first is a heat treatment process using a rapid heat treatment apparatus, the second is a heat treatment process using a reactor. By using the first method, however, a titanium silicon (TiSi 2 ) layer may be formed at an interface with a silicon substrate to reduce contact resistance between the metal layer to be formed thereon and the junction region. Is difficult. On the other hand, the second method is effective in filling oxygen between grains of titanium nitride to sufficiently prevent the fracture of the junction. However, when the heat treatment increases the depth of bonding and forms a titanium silicon layer with an excessive thickness, the bonding is performed. Due to absorption of dopants present in the region, the contact resistance is increased, resulting in deterioration of device performance. Therefore, there are many restrictions on the heat treatment temperature and time.
따라서 본 발명은 실리콘기판과의 계면에 티타늄실리콘(TiSi2)층을 형성시키며 티타늄나이트라이드(TiN)층의 그레인(Grain) 사이에 산소(O2)를 충분히 충진시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 베리어 금속층 형성방법을 제공하는 데 그 목적이 있다.Therefore, the present invention forms a titanium silicon (TiSi 2 ) layer at the interface with the silicon substrate and the oxygen (O 2 ) is sufficiently filled between the grains of the titanium nitride (TiN) layer to solve the above disadvantages. It is an object of the present invention to provide a method for forming a barrier metal layer of a semiconductor device.
상기한 목적을 달성하기 위한 본 발명은 접합영역이 형성된 실리콘 기판상에 절연층을 형성하고, 상기 접합영역이 노출되도록 상기 절연층을 패터닝하여 콘택홀을 형성시킨 상태에서, 전체 상부면에 티타늄 및 티타늄나이트라이드를 순차적으로 증착하는 단계와, 상기 단계로부터 상기 실리콘 기판과의 계면에 티타늄실리콘층을 생성시키며, 상기 티타늄나이트라이드의 그레인 사이에 산소가 채워지도록 소정 온도 및 소정 량의 산소가 첨가된 질소 가스 분위기 상태에서 제 1 열처리공정을 실시하는 단계와, 상기 단계로부터 상기 티타늄실리콘층의 생성을 억제시키며, 상기 티타늄나이트라이드의 그레인 사이에 채워진 산소를 충분히 확산시키기 위하여 소정 온도에서 제 2 열처리공정을 실시하는 단계로 이루어지는 것을 특징으로 한다.In order to achieve the above object, the present invention provides an insulating layer on a silicon substrate on which a junction region is formed, and forms a contact hole by patterning the insulation layer to expose the junction region. Sequentially depositing titanium nitride, and forming a titanium silicon layer at the interface with the silicon substrate, and adding a predetermined temperature and a predetermined amount of oxygen to fill oxygen between the grains of the titanium nitride. Performing a first heat treatment step in a nitrogen gas atmosphere, and suppressing formation of the titanium silicon layer from the step, and performing a second heat treatment step at a predetermined temperature to sufficiently diffuse oxygen filled between the grains of the titanium nitride. Characterized in that the step consisting of.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1A 내지 제 1C 도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성방법을 설명하기 위한 소자의 단면도로서,1A to 1C are cross-sectional views of a device for explaining a method of forming a barrier metal layer of a semiconductor device according to the present invention.
제 1A 도는 접합영역(2)이 형성된 실리콘기판(1)상에 절연층(3)을 형성하고, 상기 접합영역(2)이 노출되도록 상기 절연층(3)을 패터닝하여 콘택홀을 형성시킨 상태에서, 전체 상부면에 티타늄(Ti: 4)을 증착한 후 반응성 스퍼터링 방법을 이용하여 상기 티타늄(4)상에 티타늄나이트라이드(TiN: 5)를 증착한 상태의 단면도이다.1A or the insulating layer 3 is formed on the silicon substrate 1 in which the junction area | region 2 was formed, and the insulating layer 3 is patterned so that the said junction area | region 2 may be exposed, and the contact hole was formed. In FIG. 3, a titanium nitride (Ti: 4) is deposited on the entire upper surface, and then titanium nitride (TiN: 5) is deposited on the titanium 4 using a reactive sputtering method.
제 1B 도는 600 내지 700℃의 온도 및 5 내지 10%의 산소(O2)가 첨가된 질소(N2) 가스 분위기 상태인 급속 열처리 장치내에서 수초 내지 수십초 동안 제 1 열처리공정을 실시한 상태의 단면도인데, 이때 상기 티타늄(4)은 하부층과 반응하여 티타늄실리콘층(4A)을 생성시키고, 상기 티타늄나이트라이드(5)의 그레인 사이에는 산소(6)가 채워진다.1B is a state in which the first heat treatment process is performed for several seconds to several tens of seconds in a rapid heat treatment apparatus having a temperature of 600 to 700 ° C. and a nitrogen (N 2 ) gas atmosphere to which 5 to 10% of oxygen (O 2 ) is added. In this case, the titanium (4) is reacted with the lower layer to produce a titanium silicon layer (4A), the oxygen (6) is filled between the grains of the titanium nitride (5).
제 1C 도는 상기 티타늄실리콘층(4A)의 생성을 억제시키며, 상기 티타늄나이트라이드(5)의 그레인 사이에 채워진 산소(6)를 충분히 확산시키기 위하여 600℃ 이하의 온도에서 수십분 내지 1시간 동안 제 2 열처리공정을 실시한 상태의 단면도이다.FIG. 1C shows the second silicon nitride layer 4A suppressing the production of the titanium silicon layer 4A, and the second one for several minutes to one hour at a temperature of 600 ° C. or less to sufficiently diffuse the oxygen 6 filled between the grains of the titanium nitride 5. It is sectional drawing of the state which performed the heat processing process.
상술한 바와 같이 본 발명에 의하면 두번의 열처리공정을 통하여 실리콘기판과의 계면에 티타늄보다 낮은 비저항 값을 갖는 티타늄실리콘(TiSi2)층을 형성하므로 상부에 형성될 금속층과 접합영역과의 접촉저항을 감소시킬 수 있다. 또한 티타늄나이트라이드(TiN)의 그레인(Grain) 사이에 산소(O2)를 충분히 충진시켜 알루미늄과 실리콘의 상호 확산에 의한 접합 파괴 현상의 발생을 방지하므로써 누설전류의 발생이 방지되어 소자의 신뢰성이 향상될 수 있는 탁월한 효과가 있다.As described above, according to the present invention, a titanium silicon (TiSi 2 ) layer having a lower resistivity value than that of titanium is formed at the interface with the silicon substrate through two heat treatment processes, thereby improving contact resistance between the metal layer and the junction region to be formed thereon. Can be reduced. In addition, the oxygen (O 2 ) is sufficiently filled between the grains of titanium nitride (TiN) to prevent the occurrence of junction breakdown due to the mutual diffusion of aluminum and silicon, thereby preventing the occurrence of leakage current, thereby improving the reliability of the device. There is an excellent effect that can be improved.
제 1A 내지 제 1C 도는 본 발명에 따른 반도체 소자의 베리어 금속층 형성방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method for forming a barrier metal layer of a semiconductor device according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
1: 실리콘기판 2: 접합영역1: silicon substrate 2: junction area
3: 절연막 4: 티타늄3: insulation film 4: titanium
4A: 티타늄실리콘층 5: 티타늄나이트라이드4A: titanium silicon layer 5: titanium nitride
6: 산소6: oxygen
Claims (5)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950025925A KR100342827B1 (en) | 1995-08-22 | 1995-08-22 | Method for forming barrier metal layer of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019950025925A KR100342827B1 (en) | 1995-08-22 | 1995-08-22 | Method for forming barrier metal layer of semiconductor device |
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| KR970013218A KR970013218A (en) | 1997-03-29 |
| KR100342827B1 true KR100342827B1 (en) | 2002-11-04 |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07161660A (en) * | 1993-12-13 | 1995-06-23 | Nec Corp | Manufacture of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH07161660A (en) * | 1993-12-13 | 1995-06-23 | Nec Corp | Manufacture of semiconductor device |
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