KR20000041873A - Formation method of metal distribution - Google Patents

Formation method of metal distribution Download PDF

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Publication number
KR20000041873A
KR20000041873A KR1019980057886A KR19980057886A KR20000041873A KR 20000041873 A KR20000041873 A KR 20000041873A KR 1019980057886 A KR1019980057886 A KR 1019980057886A KR 19980057886 A KR19980057886 A KR 19980057886A KR 20000041873 A KR20000041873 A KR 20000041873A
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South Korea
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film
cobalt
contact hole
semiconductor substrate
layers
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KR1019980057886A
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Korean (ko)
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김영수
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김영환
현대반도체 주식회사
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Priority to KR1019980057886A priority Critical patent/KR20000041873A/en
Publication of KR20000041873A publication Critical patent/KR20000041873A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

PURPOSE: A metal distribution formation is provided by lowering a contact resistance value, and by removing the problems to weaken an adhesion because of the penetration of fluorine gas. CONSTITUTION: A formation method of the metal distributions contains the following processes: a process to deposit in vapor the dielectric layers having the contact holes so as to disclose a region in semiconductor substrate; a process to deposit in vapor the thin barrier layers and cobalt layers orderly thereon; a process to grow up the cobalt silicide layers below the contact holes being contacted the semiconductor substrate and the barrier layers by rapid thermal process; and a process to form the metal distribution layers in the contact holes and on the cobalt layers.

Description

금속배선 형성방법Metal wiring formation method

본 발명은 반도체 소자의 배선에 대한 것으로, 특히 저항을 낯추고 배선의 신뢰성을 높이기에 알맞은 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to wiring of semiconductor devices, and more particularly, to a method for forming metal wiring suitable for reducing resistance and increasing wiring reliability.

첨부 도면을 참조하여 종래 금속배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional metal wiring forming method will be described below.

도 1a 내지 도 1c는 종래 금속배선 형성방법을 나타낸 공정단면도이다.1A to 1C are cross-sectional views illustrating a conventional metal wiring forming method.

종래 금속배선 형성방법은 도 1a에 도시한 바와 같이 반도체기판(1)상에 산화막(2)을 증착한다. 이후에 산화막(2)상에 감광막(도면에는 도시되지 않았다)을 도포한 후 차후에 콘택홀을 형성할 부분을 노광 및 현상공정하여 선택적으로 감광막을 패터닝한다. 이후에 패터닝된 감광막을 마스크로 산화막(2)을 이방성식각해서 콘택홀을 형성한다.In the conventional metal wiring forming method, an oxide film 2 is deposited on a semiconductor substrate 1 as shown in FIG. 1A. Thereafter, a photoresist film (not shown in the figure) is applied onto the oxide film 2, and then a portion to form a contact hole is subsequently exposed and developed to selectively pattern the photoresist film. Thereafter, the oxide film 2 is anisotropically etched using the patterned photoresist as a mask to form contact holes.

그리고 도 1b에 도시한 바와 같이 베리어막으로써 상기 콘택홀 및 산화막(2)상에 티타늄(Ti)막(3)과 티타늄나이트라이드(TiN)막(4)을 차례로 증착한다.As shown in FIG. 1B, a titanium (Ti) film 3 and a titanium nitride (TiN) film 4 are sequentially deposited on the contact hole and the oxide film 2 as barrier films.

다음에 급속열공정(Rapid Thermal Process)을 이용하여 티타늄막(3)과 반도체기판(1)의 사이에 티타늄실리사이드(TiSi2)막(5)을 형성한다. 이에 따라서 티타늄실리사이드막(5)은 밀도가 높아진다.Next, a titanium silicide (TiSi 2 ) film 5 is formed between the titanium film 3 and the semiconductor substrate 1 by using a rapid thermal process. As a result, the titanium silicide film 5 has a high density.

다음에 도 1c에 도시한 바와 같이 상기 콘택홀내 및 상기 티타늄나이트라이드막(4)상에 화학기상증착법으로 텅스텐을 증착한다. 텅스텐 증착가스로 WF6를 사용한다.Next, as shown in FIG. 1C, tungsten is deposited by chemical vapor deposition in the contact hole and on the titanium nitride film 4. WF 6 is used as the tungsten deposition gas.

이후에 텅스텐을 에치백이나 화학적 기계적 연마법을 이용하여 금속배선층(6)을 형성한다.Thereafter, tungsten is etched back or chemical mechanical polishing is used to form the metallization layer 6.

상기와 같이 종래 금속배선 형성방법은 다음과 같은 문제가 있다.As described above, the conventional metal wiring forming method has the following problems.

첫째, 열처리하여 티타늄실리사이드막을 형성할 때 열처리 온도가 높을수록 티타늄나이트라이드막 덩어리(agglomeration)가 발생하여 콘택부분에서 정션누설전류가 발생하고, 또한 콘택저항이 높아지는 문제가 있다.First, when the titanium silicide film is formed by heat treatment, the higher the heat treatment temperature, the more the titanium nitride film agglomeration occurs, the junction leakage current is generated in the contact portion, and the contact resistance is increased.

둘째, 텅스텐을 증착할 때 사용되는 플로린(Fluorin)이 티타늄나이트라이드막으로 침투하여 콘택홀의 바닥부분에서 축적되어 정션 누설전류가 발생되고, 또한 콘택저항이 높아지는 문제가 있다.Second, florin, which is used to deposit tungsten, penetrates into the titanium nitride film and accumulates at the bottom of the contact hole to generate a junction leakage current and increase contact resistance.

셋째, 소자를 고집적화 시킬 때 WF6가스와 Ti가 반응하여 TiF3화합물이 생성되는데, 이화합물에 의해서 티타늄막과 산화막의 접촉력이 약화되는 문제가 있다.Third, when the device is highly integrated, the WF 6 gas and Ti react to form a TiF 3 compound, which causes a problem of weakening the contact force between the titanium film and the oxide film.

본 발명은 상기와 같은 문제를 해결하기 위하여 안출한 것으로 특히, 콘택저항값을 낮추고, 플로린가스의 침투로 인하여 접촉력이 약화되는 문제를 없애서 배선의 신뢰성을 높이기에 알맞은 금속배선 형성방법을 제공하는 데 그 목적이 있다.The present invention has been made to solve the above problems, in particular, to provide a method for forming a metal wiring suitable for improving the reliability of the wiring by lowering the contact resistance value, eliminating the problem of weakening the contact force due to the penetration of florin gas. Its purpose is.

도 1a 내지 도 1c는 종래 금속배선 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method of forming a metal wiring according to the related art.

도 2a 내지 도 2c는 본 발명 금속배선 형성방법을 나타낸 공정단면도Figure 2a to 2c is a cross-sectional view showing a process for forming a metal wiring of the present invention

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

11: 반도체기판 12: 산화막11: semiconductor substrate 12: oxide film

13: 티타늄 나이트라이드막 14: 코발트막13: titanium nitride film 14: cobalt film

15: 코발트실리사이드막 16: 금속배선층15: cobalt silicide film 16: metal wiring layer

상기와 같은 목적을 달성하기 위한 본 발명 금속배선 형성방법은 반도체기판의 일영역이 드러나도록 콘택홀을 갖는 절연막을 증착하는 공정과, 상기 콘택홀 및 상기 절연막상에 얇은 두께의 베리어막과 코발트막을 차례로 증착하는 공정과, 급속열공정으로 상기 반도체기판과 상기 베리어막이 접하는 콘택홀 하부에 코발트실리사이드막을 성장시키는 공정과, 상기 콘택홀 내 및 상기 코발트막 상에 금속배선층을 형성하는 공정을 포함하여 제조됨을 특징으로 한다.In order to achieve the above object, the present invention provides a method for forming a metal wiring, by depositing an insulating film having a contact hole so that a region of a semiconductor substrate is exposed; And a step of growing a cobalt silicide film under the contact hole in which the semiconductor substrate and the barrier film are in contact with each other by a rapid thermal process, and forming a metal wiring layer in the contact hole and on the cobalt film. It is characterized by.

첨부 도면을 참조하여 본 발명 금속배선 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of forming a metal wire according to the present invention will be described.

도 2a 내지 도 2c는 본 발명 금속배선 형성방법을 나타낸 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a metal wiring according to the present invention.

본 발명 금속배선 형성방법은 도 2a에 도시한 바와 같이 반도체기판(11)상에 산화막(12)을 증착한다. 이후에 산화막(12)상에 감광막(도면에는 도시되지 않았다)을 도포한 후 차후에 콘택홀을 형성할 부분을 노광 및 현상공정하여 선택적으로 감광막을 패터닝한다. 이후에 패터닝된 감광막을 마스크로 산화막(12)을 이방성식각해서 콘택홀을 형성한다.In the method for forming metal wirings of the present invention, the oxide film 12 is deposited on the semiconductor substrate 11 as shown in FIG. 2A. Thereafter, a photoresist film (not shown in the figure) is applied onto the oxide film 12, and then a portion to form a contact hole is subsequently exposed and developed to selectively pattern the photoresist film. Thereafter, the oxide film 12 is anisotropically etched using the patterned photoresist as a mask to form a contact hole.

그리고 도 2b에 도시한 바와 같이 베리어막으로써 상기 콘택홀 및 산화막(12)상에 50∼200Å정도의 두께를 갖도록 티타늄나이트라이드(TiN)막(13)을 증착하고, 티타늄나이트라이드(TiN)막(13)상에 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition)방식을 이용해서 100∼200Å범위의 두께를 갖도록 코발트(Co)막(14)을 증착한다.As shown in FIG. 2B, a titanium nitride (TiN) film 13 is deposited on the contact hole and the oxide film 12 so as to have a thickness of about 50 to 200 microseconds as a barrier film, and a titanium nitride (TiN) film is deposited. A cobalt (Co) film 14 is deposited on (13) to have a thickness in the range of 100 to 200 microseconds using PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition).

이후에 700∼850℃범위의 온도에서 급속열공정(Rapid Thermal Process)하여 반도체기판(11)과 접한 티타늄나이트라이드(TiN)막(13)의 사이에 균일하게 코발트실리사이드(CoSi2)막(15)을 성장시키고, 또한 밀집된(Dense) 티타늄 나이트라이드막(13)이 형성되도록 한다.Afterwards, a cobalt silicide (CoSi 2 ) film 15 is uniformly interposed between the titanium nitride (TiN) film 13 in contact with the semiconductor substrate 11 by a rapid thermal process at a temperature in the range of 700 to 850 ° C. ), And also a dense titanium nitride film 13 is formed.

상기에서 베리어막을 사용되는 얇은 두께의 티타늄 나이트라이드막(13)을 증착하는 이유는 코발트막(14)과 반도체기판(11)의 실리콘이온(Si)이 직접만나면 열처리공정시 코발트막의 3배정도의 두께를 갖는 코발트실리사이드막(15)이 형성되는데 이와 같은 후속열처리공정시에 반도체기판(11)의 실리콘이온과 코발트막의 사이에 티타늄 나이트라이드막을 형성하여서 매우 얇고 균일한 두께의 코발트 실리사이드(CoSi2)막을 형성시키기 위해서이다. 이에 따라서 콘택홀 하단에 형성되는 정션 특성을 악화시킬 수 있는 소지를 미리 방지함과 동시에 코발트 원자가 반도체기판(11)쪽으로 확산되는 것을 제어하기 위함이다.The reason for depositing the thin titanium nitride film 13 using the barrier film is that the cobalt film 14 and the silicon ions (Si) of the semiconductor substrate 11 directly meet the thickness of about 3 times that of the cobalt film during the heat treatment process. A cobalt silicide layer 15 having a cobalt silicide layer 15 is formed. A titanium nitride layer is formed between the silicon ion of the semiconductor substrate 11 and the cobalt layer in the subsequent heat treatment process to form a cobalt silicide (CoSi 2 ) layer having a very thin and uniform thickness. To form. Accordingly, the purpose of the present invention is to prevent the material from deteriorating the junction characteristics formed at the bottom of the contact hole in advance and to control the diffusion of cobalt atoms toward the semiconductor substrate 11.

다음에 도 2c에 도시한 바와 같이 상기 콘택홀을 포함한 코발트(Co)막(14)상에 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition)방식이나 PVD와 CVD방법을 함께 이용하는 방식을 통하여 코발트를 증착하므로써 금속배선층(16)을 형성한다.Next, as shown in FIG. 2C, cobalt is deposited on the cobalt (Co) film 14 including the contact hole by using a PVD (Physical Vapor Deposition) or CVD (Chemical Vapor Deposition) method or a PVD and CVD method. By depositing the metal wiring layer 16 is formed.

상기에서 코발트로 금속배선층(16)을 형성하면 코발트가 800℃이상의 고온에서 산화막과 어떤 반응도 하지 않으므로 배선의 신뢰성이 좋다.When the metal wiring layer 16 is formed of cobalt as described above, cobalt does not react with the oxide film at a high temperature of 800 ° C. or higher, so the reliability of the wiring is good.

상기와 같은 본 발명 금속배선 형성방법은 다음과 같은 효과가 있다.The metal wiring forming method of the present invention as described above has the following effects.

첫째, 콘택홀 하부에 CoSi2막을 형성하여 콘택저항값을 낮출 수 있다.First, a contact resistance value may be lowered by forming a CoSi 2 film under the contact hole.

둘째, 코발트막과 반도체기판 사이에 베리어막으로써 얇은 두께의 티타늄나이트라이드막을 형성하므로 금속배선 콘택의 신뢰성을 증대시킬 수 있다.Second, since a thin titanium nitride film is formed as a barrier film between the cobalt film and the semiconductor substrate, the reliability of the metallization contact can be increased.

Claims (7)

반도체기판의 일영역이 드러나도록 콘택홀을 갖는 절연막을 증착하는 공정과,Depositing an insulating film having a contact hole so that one region of the semiconductor substrate is exposed; 상기 콘택홀 및 상기 절연막상에 얇은 두께의 베리어막과 코발트막을 차례로 증착하는 공정과,Depositing a thin barrier film and a cobalt film in sequence on the contact hole and the insulating film; 급속열공정으로 상기 반도체기판과 상기 베리어막이 접하는 콘택홀 하부에 코발트실리사이드막을 성장시키는 공정과,Growing a cobalt silicide film under a contact hole in contact with the semiconductor substrate and the barrier film by a rapid thermal process; 상기 콘택홀 내 및 상기 코발트막 상에 금속배선층을 형성하는 공정을 포함하여 제조됨을 특징으로 하는 금속배선 형성방법.And forming a metal wiring layer in the contact hole and on the cobalt layer. 제 1 항에 있어서, 상기 베리어막으로 50∼200Å정도의 두께로 증착함을 특징으로 하는 금속배선 형성방법.2. The method of claim 1, wherein the barrier film is deposited to a thickness of about 50 to about 200 microns. 제 1 항에 있어서, 상기 베리어막은 티타늄나이트라이드막을 사용하는 것을 특징으로 하는 금속배선 형성방법.The method of claim 1, wherein the barrier film is a titanium nitride film. 제 1 항에 있어서, 상기 코발트막은 100∼200Å정도의 두께로 증착함을 특징으로 하는 금속배선 형성방법.2. The method of claim 1, wherein the cobalt film is deposited to a thickness of about 100 to about 200 microns. 제 1 항에 있어서, 상기 급속열처리공정은 700∼850℃정도에서 실시함을 특징으로 하는 금속배선 형성방법.The method of claim 1, wherein the rapid heat treatment is performed at about 700 to 850 캜. 제 1 항에 있어서, 상기 코발트막은 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition)방식을 이용하여 증착함을 특징으로 하는 금속배선 형성방법.The method of claim 1, wherein the cobalt film is deposited using a PVD (Physical Vapor Deposition) or a CVD (Chemical Vapor Deposition) method. 제 1 항에 있어서, 상기 금속배선층은 코발트막을 PVD(Physical Vapor Deposition) 또는 CVD(Chemical Vapor Deposition)방식이나, PVD와 CVD를 함께 혼합한 방식을 통하여 형성함을 특징으로 하는 금속배선 형성방법.The method of claim 1, wherein the metal wiring layer is formed by a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method, or a method in which PVD and CVD are mixed together.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014105477A1 (en) * 2012-12-28 2014-07-03 Intel Corporation Cobalt based interconnects and methods of fabrication thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014105477A1 (en) * 2012-12-28 2014-07-03 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
GB2522825A (en) * 2012-12-28 2015-08-05 Intel Corp Cobalt based interconnects and methods of fabrication thereof
GB2522825B (en) * 2012-12-28 2018-12-12 Intel Corp Cobalt based interconnects and methods of fabrication thereof

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