KR100313417B1 - Method of forming a wiring in a seminconductor device - Google Patents
Method of forming a wiring in a seminconductor device Download PDFInfo
- Publication number
- KR100313417B1 KR100313417B1 KR1019990023926A KR19990023926A KR100313417B1 KR 100313417 B1 KR100313417 B1 KR 100313417B1 KR 1019990023926 A KR1019990023926 A KR 1019990023926A KR 19990023926 A KR19990023926 A KR 19990023926A KR 100313417 B1 KR100313417 B1 KR 100313417B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- metal
- forming
- silicon
- vapor deposition
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- 239000010703 silicon Substances 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 76
- -1 silicon ions Chemical class 0.000 claims description 18
- 239000010936 titanium Substances 0.000 claims description 10
- 239000012790 adhesive layer Substances 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 abstract description 5
- 230000002776 aggregation Effects 0.000 abstract description 4
- 229910021645 metal ion Inorganic materials 0.000 abstract description 3
- 238000005054 agglomeration Methods 0.000 abstract 1
- 229910052721 tungsten Inorganic materials 0.000 description 9
- 239000010937 tungsten Substances 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 8
- 229910021341 titanium silicide Inorganic materials 0.000 description 6
- 238000004220 aggregation Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000015271 coagulation Effects 0.000 description 2
- 238000005345 coagulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 150000003657 tungsten Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 금속 배선 형성 시에 접착층(adhesion layer) 및 금속 이온 확산 방지층 역할을 하는 배리어 금속층(barrier layer)이 적용되고 있는데, 배리어 금속층을 형성하기 전에 콘택홀 저면을 이루는 접합부(junction) 표면에 에피텍셜 실리콘층(epitaxial silicon layer)을 형성하고, 이후 배리어 금속층 형성 및 후속 열공정에 의해 금속-실리사이드층(metal-silicide layer)을 형성하므로써, 열공정 동안 배리어 금속층의 금속이 에피텍셜 실리콘층의 실리콘과 반응하여 균일한 두께 및 농도를 갖는 금속-실리사이드층이 형성되므로 인해 기존 공정과 같이 접합부의 실리콘과의 반응이 억제되어, 접합부에서 금속-실리사이드층이 과도하게 형성되거나 응집 현상이 발생하므로 인한 콘택 저항 증가 및 접합부의 누설 전류 증가 등의 문제를 해결할 수 있어, 소자의 신뢰성 향상 및 소자의 고집적화, 초고속화를 실현시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, wherein a barrier metal layer serving as an adhesion layer and a metal ion diffusion preventing layer is applied at the time of forming a metal wiring. During the thermal process by forming an epitaxial silicon layer on the junction surface forming the bottom of the hole and then forming a metal-silicide layer by barrier metal layer formation and subsequent thermal process Since the metal of the barrier metal layer reacts with the silicon of the epitaxial silicon layer to form a metal-silicide layer having a uniform thickness and concentration, the reaction of the junction metal with silicon is suppressed as in the conventional process, so that the metal-silicide layer is formed at the junction. Increased contact resistance and leakage current at junctions due to overforming or agglomeration It can solve the problems, such as is described with regard to improved reliability of the device and the high integration of elements, metal wiring formation method of a semiconductor device which can realize a high-speed screen.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 금속-실리사이드층(metal-silicide layer)을 형성할 때, 접합부(junction)의 실리콘과의 반응을 억제시켜, 접합부에서 금속-실리사이드층이 과도하게 형성되거나 응집 현상이 발생하므로 인한 콘택 저항 증가 및 접합부의 누설 전류 증가 등을 방지하므로써, 소자의 신뢰성 향상 및 소자의 고집적화, 초고속화를 실현시킬 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a metal wiring of a semiconductor device, and when forming a metal-silicide layer, suppresses the reaction of the junction with silicon so that the metal-silicide layer is excessive at the junction. The present invention relates to a method for forming a metal wiring of a semiconductor device capable of realizing improved reliability of the device, high integration of the device, and high speed by preventing an increase in contact resistance, an increase in leakage current at the junction, and the like, due to the formation of a high density or aggregation.
일반적으로, 반도체 소자의 금속 배선에서 장벽 금속층은 타이타늄(Ti)과 타이타늄나이트라이드(TiN)의 이중층(double layer)으로 구성된다. 타이타늄층은 금속 배선의 주 재료인 텅스텐(W)이나 알루미늄(Al)이 하부층과 잘 접착되도록 하는 접착층 역할을 하면서, 실리콘 기판과 반응하여 타이타늄실리사이드층(TiSi2layer)을 형성하므로 콘택 저항을 낮추어 주는 역할을 한다. 타이타늄나이트라이드층은 금속 배선의 주 재료인 텅스텐(W)이나 알루미늄(Al)이 실리콘 기판과 직접 반응하는 것을 차단하는 금속 이온 확산 방지층 역할을 하면서, 금속층 증착시 시드층 (seed layer) 역할을 한다.In general, the barrier metal layer in the metal wiring of the semiconductor device is composed of a double layer of titanium (Ti) and titanium nitride (TiN). The titanium layer acts as an adhesive layer that allows the tungsten (W) or aluminum (Al), which is the main material of the metal wiring, to adhere well to the lower layer, and reacts with the silicon substrate to form a titanium silicide layer (TiSi 2 layer), thereby reducing contact resistance. Role. Titanium nitride layer acts as a seed layer during metal layer deposition while acting as a metal ion diffusion preventing layer that blocks tungsten (W) or aluminum (Al), which is a main material of metal wiring, from directly reacting with the silicon substrate. .
반도체 소자가 고집적화 되어 감에 따라 금속 배선 공정시 콘택의 크기 감소 및 애스팩트 비(aspect ratio)의 증가로 매립 공정에 많은 문제가 발생하고 있으며, 또한 얕은 접합부(shallow junction)를 통하여 구현되는 트랜지스터를 필요로 하는 소자가 많기 때문에 금속 배선 공정을 진행하는데 많은 문제가 발생되고 있다. 즉, 얕은 접합부에서 콘택 저항을 낮추기 위해 실리콘 기판의 실리콘과 타이타늄층의 타이타늄을 반응시켜 타이타늄-실리사이드층을 형성하게 되는데, 이러한 타이타늄-실리사이드층은 증착된 타이타늄층의 2배 가까운 두께로 만들어지게 되고, 이로 인하여 얕은 접합부에서 실리콘을 소모하게 되어 접합부의 파괴를 동반하게 되며, 이러한 접합부의 파괴는 트랜지스터의 동작이 제대로 되지 않으며, 과도하지 않을 경우에도 누설 전류가 증가하는 문제가 발생하기도 한다.As semiconductor devices become highly integrated, many problems arise in the buried process due to the decrease in contact size and the increase in aspect ratio during the metal wiring process, and also the transistors implemented through shallow junctions Due to the large number of devices required, many problems have arisen in carrying out the metal wiring process. In other words, in order to lower the contact resistance at the shallow junction, the silicon of the silicon substrate and the titanium of the titanium layer are reacted to form a titanium-silicide layer. The titanium-silicide layer is made twice as thick as the deposited titanium layer. As a result, the silicon is consumed in the shallow junction, which causes the junction to be destroyed, and the junction is not properly operated, and the leakage current may increase even when the junction is not excessive.
또한, 폴리실리콘을 이용하는 비트 라인 공정을 텅스텐 플러그 형성 공정으로 대체하여 반도체 소자의 집적화 및 빠른 속도를 구현하려고 하는 경우에 텅스텐을 증착하기 위한 배리어 금속층의 증착에서 나타나는 접합부의 파괴 및 이후 공정에서 얻어지는 열 공정에 의한 접합부 파괴 등과 같은 문제가 발생하여 반도체 소자의 신뢰성 및 공정의 안정화에 많은 문제가 발생하고 있다. 즉, 현재 비트 라인 콘택이나 금속 배선 콘택 형성시 콘택홀을 형성한 후에 이를 매립하는데, 대부분 텅스텐 플러그 공정을 사용하며, 이러한 텅스텐 플러그 공정에서는 배리어 금속층으로 타이타늄나이트라이드를 많이 사용하게 되나, 타이타늄나이트라이드는 비저항이 높기 때문에 이러한 비저항을 낮출 수 있는 타이타늄 증착을 이용하여 타이타늄-실리사이드를 형성한다. 그러나, 이러한 금속 배선 공정에서는 반도체 소자의 제조 공정에서 서멀 버짓(thermal budget)이 많아지게 되면, 타이타늄-실리사이드의 응집 현상이 나타나게 되고, 이러한 응집 현상이 반도체 소자의 금속 배선 저항을 높게 하여 신뢰성 및 속도를 저하시키는 요인이 된다.In addition, when the bit line process using polysilicon is replaced with a tungsten plug forming process, integration of semiconductor devices and high speed can be achieved, the breakage of the junction shown in the deposition of a barrier metal layer for depositing tungsten and the heat obtained in a subsequent process Problems such as breakage of junctions caused by processes have occurred, resulting in many problems in reliability of semiconductor devices and stabilization of processes. In other words, at the present time, a contact hole is formed in the formation of a bit line contact or a metal wiring contact, and the gap is buried. Mostly, a tungsten plug process is used. In this tungsten plug process, titanium nitride is frequently used as a barrier metal layer. Because of its high resistivity, titanium-silicide is formed using titanium deposition, which can lower the resistivity. However, in such a metal wiring process, when the thermal budget increases in the manufacturing process of the semiconductor device, a coagulation phenomenon of titanium-silicide appears, and this coagulation phenomenon increases the metal wiring resistance of the semiconductor device, thereby increasing reliability and speed. It becomes a factor which lowers.
전술한 문제를 해결하기 위하여, 퍼니스(furnace)에서 고온 공정을 통하여 다결정 실리콘층을 형성시켜 타이타늄-실리사이드층을 만들어줄 버퍼층(bufferlayer)으로 이용하는 방법이 적용되고 있으나, 이 방법은 고온 공정이라는 측면에서 얕은 접합부를 필요로 하는 소자에 적합하지 않고, 또한 실제 공정이 장시간을 요하기 때문에 제조 비용 및 생산성 저하를 초래한다. 아울러, 이러한 공정을 텅스텐 비트 라인이 적용된 소자에서 사용하게 되면, 서멀 버짓에 의한 텅스텐 비트 라인의 페일(fail)이 발생할 가능성이 많으며, 이러한 경우 실제 반도체 소자의 신뢰성에 많은 문제가 된다.In order to solve the above problem, a method of using a buffer layer to form a titanium-silicide layer by forming a polycrystalline silicon layer through a high temperature process in a furnace has been applied. It is not suitable for devices requiring a shallow junction, and also results in a reduction in manufacturing cost and productivity since the actual process requires a long time. In addition, when such a process is used in a device to which a tungsten bit line is applied, a failure of the tungsten bit line due to the thermal budget is likely to occur, and in this case, there are many problems in the reliability of the actual semiconductor device.
따라서, 본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 금속-실리사이드층을 형성할 때, 접합부의 실리콘과의 반응을 억제시켜, 접합부에서 금속-실리사이드층이 과도하게 형성되거나 응집 현상이 발생하므로 인한 콘택 저항 증가 및 접합부의 누설 전류 증가 등을 방지하므로써, 소자의 신뢰성 향상 및 소자의 고집적화, 초고속화를 실현시킬 수 있는 반도체 소자의 금속 배선 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention relates to a method for forming a metal wiring of a semiconductor device, and when forming a metal-silicide layer, by suppressing the reaction with the silicon of the junction, excessive formation of the metal-silicide layer or aggregation phenomenon at the junction Therefore, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can improve the reliability of the device, and achieve high integration and ultra-high speed of the device by preventing contact increase and leakage current increase in the junction.
이러한 목적을 달성하기 위한 본 발명의 반도체 소자의 금속 배선 형성 방법은 콘택홀을 갖는 층간 절연막이 형성된 실리콘 기판이 제공되는 단계; 고밀도 플라즈마를 이용하여 형성된 실리콘 이온을 상기 콘택홀 저면을 이루는 접합부 표면으로 이동시켜 에피텍셜 실리콘층을 형성하는 단계; 상기 에피텍셜 실리콘층을 갖는 상기 콘택홀을 포함한 층간 절연막 상에 장벽 금속층을 형성하는 단계; 및 상기 장벽 금속층을 열처리하여 금속-실리사이드층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, a method of forming a metal wiring of a semiconductor device according to the present invention includes providing a silicon substrate having an interlayer insulating film having a contact hole; Forming an epitaxial silicon layer by moving silicon ions formed using a high density plasma to a junction surface forming the bottom of the contact hole; Forming a barrier metal layer on the interlayer insulating film including the contact hole having the epitaxial silicon layer; And heat treating the barrier metal layer to form a metal-silicide layer.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 금속 배선 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of devices for explaining a metal wiring forming method according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1: 실리콘 기판 2: 접합부1: silicon substrate 2: junction
3: 층간 절연막 4: 콘택홀3: interlayer insulating film 4: contact hole
5: 장벽 금속층 5A: 접착층5: barrier metal layer 5A: adhesive layer
5B: 확산 방지층 6: 금속층5B: diffusion barrier layer 6: metal layer
10: 에피텍셜 실리콘층 50: 금속-실리사이드층10: epitaxial silicon layer 50: metal-silicide layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 금속 배선 형성 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of devices for describing a metal wiring forming method according to an embodiment of the present invention.
도 1a를 참조하면, 접합부(2)가 형성된 실리콘 기판(1) 상에 층간 절연막(3)을 형성하고, 층간 절연막(3)의 일부분을 식각 하여 접합부(2)가 노출되는 콘택홀(4)을 형성한다. 저온 플라즈마를 이용하여 형성된 실리콘 이온(Si+)을 콘택홀(4) 저면을 이루는 접합부(2) 표면으로 이동시켜 10 내지 500Å의 두께의 에피텍셜 실리콘층(epitaxial silicon layer; 10)을 형성한다.Referring to FIG. 1A, an interlayer insulating film 3 is formed on a silicon substrate 1 on which a junction part 2 is formed, and a portion of the interlayer insulating film 3 is etched to expose a contact hole 4 through which the junction part 2 is exposed. To form. Silicon ions (Si + ) formed by using a low temperature plasma are transferred to the surface of the junction portion 2 forming the bottom of the contact hole 4 to form an epitaxial silicon layer 10 having a thickness of 10 to 500 Å.
상기에서, 실리콘 이온은 고밀도 플라즈마 장비에서 SiH4가스를 플라즈마 처리하여 형성된다. 이렇게 형성된 실리콘 이온의 경우 네거티브 챠지 바이어스(negative charge bias)를 인가하게 되면 실리콘 이온이 방향성을 갖게되어 이동을 할 수 있으며, 이러한 이동을 통하여 실리콘 이온만을 웨이퍼로 이동시켜 에피텍셜 실리콘층(10)을 형성한다. 에피텍셜 실리콘층(10)을 형성하기 위해서는 실리콘 이온만을 선택적으로 웨이퍼 표면으로 이동시켜야 하는데, 이와 같이 실리콘 이온만을 이동시키는 방법은 플라즈마가 형성되는 부분 밑에 메쉬(mesh)를 설치하여 접지 바이어스(ground bias) 혹은 웨이퍼 부분보다 상대적으로 현저히 낮은바이어스를 인가하여 전체적으로 중성을 지니고 있는 입자의 이동을 방해하고, 실리콘 이온만을 이동하게 한다. 또한, 현재 사용하고 있는 장비에서 산화막을 형성할 때 소오스 가스로 사용되는 O2성분만을 제거하여 Si+이온과 Si*이온 상태의 플라즈마를 만들어주고, 이러한 상태에서 바이어스를 인가하게 되면, 메쉬 없이 실리콘 이온의 이동이 가능하며, 이러한 이동에서 낮은 에너지 예를 들어, 50 내지 150eV를 갖는 상태로 이동하게 되면, 실제 표면에서의 손상(damage) 없이 실리콘 이온을 지속적으로 성장시킬 수 있다.In the above, the silicon ions are formed by plasma treatment of SiH 4 gas in a high density plasma equipment. In the case of the silicon ions formed as described above, when a negative charge bias is applied, the silicon ions have a directionality and can be moved, and only the silicon ions are moved to the wafer through the movement to move the epitaxial silicon layer 10. Form. In order to form the epitaxial silicon layer 10, only silicon ions must be selectively moved to the wafer surface. In this way, only silicon ions are moved to form a ground bias by installing a mesh under the plasma formation. Alternatively, a significantly lower bias than the wafer portion is applied to hinder the movement of the neutral particles as a whole and to move only silicon ions. In addition, by removing the O 2 component used as the source gas when forming the oxide film in the current equipment to create a plasma of Si + ions and Si * ions, if a bias is applied in this state, silicon without mesh The movement of ions is possible, and by moving to a state with low energy, for example 50 to 150 eV, in this movement, it is possible to continuously grow silicon ions without damaging the actual surface.
즉, 에피텍셜 실리콘층(10)은 고온의 퍼니스(furnace) 대신에 저온에서 진행이 가능한 고밀도 플라즈마를 이용하여 실리콘 이온을 만들며, 플라즈마 증가형 화학기상증착(PE-CVD) 방식으로 형성한다. 이때, 실리콘 이온(Si+)을 콘택홀(4) 저면을 이루는 접합부(2) 표면으로 이동시키기 위해, 바이어스를 인가하여 공정을 진행하는데, 공정 진행시 인가되는 에너지는 50 내지 150eV로 하고, 웨이퍼의 뒷면 부분에 고주파(RF) 혹은 직류 전력(DC power)을 인가한다. 한편, 이러한 공정 진행시 플라즈마 영역과 웨이퍼 부분 사이에 메쉬를 설치하고, 메쉬 부분에 접지 바이어스 혹은 웨이퍼 부분보다 상대적으로 현저히 낮은 바이어스를 인가하여 실리콘 이온만을 이동하게 할 수 있다.That is, the epitaxial silicon layer 10 makes silicon ions using a high-density plasma that can proceed at a low temperature instead of a high-temperature furnace, and is formed by a plasma enhanced chemical vapor deposition (PE-CVD) method. At this time, in order to move the silicon ions (Si + ) to the surface of the junction portion 2 forming the bottom of the contact hole 4, a process is applied by applying a bias, the energy applied during the process is 50 to 150 eV, the wafer Apply a high frequency (RF) or DC power (DC power) to the back of the part. Meanwhile, during the process, a mesh may be provided between the plasma region and the wafer portion, and only the silicon ions may be moved by applying a ground bias or a significantly lower bias than the wafer portion to the mesh portion.
도 1b를 참조하면, 저면에 에피텍셜 실리콘층(10)을 갖는 콘택홀(4)을 포함한 층간 절연막(3) 상에 접착층(5A) 및 확산 방지층(5B)을 순차적으로 형성하여 장벽 금속층(5)을 형성한다.Referring to FIG. 1B, a barrier metal layer 5 is formed by sequentially forming an adhesive layer 5A and a diffusion barrier layer 5B on an interlayer insulating film 3 including a contact hole 4 having an epitaxial silicon layer 10 on a bottom surface thereof. ).
상기에서, 접착층(5A)은 물리기상증착(PVD)법, 화학기상증착(CVD)법 또는 이온화 금속 물리기상증착(Ionized Metal PVD; IMP)법 적용하여 타이타늄(Ti)을 10 내지 500Å의 두께로 증착하여 형성한다. 확산 방지층(5B)은 주로 타이타늄나이트라이드(TiN)가 널리 적용되며, 화학기상증착법으로 100 내지 500Å의 두께로 증착하여 형성된다.In the above-described adhesive layer 5A, titanium (Ti) is applied in a thickness of 10 to 500 kPa by applying physical vapor deposition (PVD), chemical vapor deposition (CVD), or ionized metal PVD (IMP). By vapor deposition. Titanium nitride (TiN) is widely applied, and the diffusion barrier layer 5B is formed by depositing a thickness of 100 to 500 kPa by chemical vapor deposition.
도 1c를 참조하면, 장벽 금속층(5)을 상에 금속층(6)을 형성한 후, 패터닝하여 금속 배선을 형성하는데, 콘택홀(4) 저면에 형성된 금속-실리사이드층(50)은 장벽 금속층(5)을 형성한 후에 열처리하거나, 금속층(6)을 형성한 후에 실시되는 열공정에 의해 형성된다.Referring to FIG. 1C, after the metal layer 6 is formed on the barrier metal layer 5, the metal layer 6 is patterned to form metal wires. The metal silicide layer 50 formed on the bottom surface of the contact hole 4 is formed of a barrier metal layer ( 5) is formed by heat treatment after forming, or by a thermal process performed after forming the metal layer 6.
상기에서, 금속-실리사이드층(50)은 접착층(5A)의 금속이 하부층인 에피텍셜 실리콘층(10)의 실리콘과 반응하여 형성된다. 이와 같이 접착층(5A)의 금속이 에피텍셜 실리콘층(10)의 실리콘과 반응하므로 인하여 그 하부층인 접합부(2)의 실리콘과는 반응이 억제된다. 금속층(6) 상에 텅스텐(W) 또는 알루미늄(Al) 등과 같은 금속을 이용하여 형성된다.In the above, the metal-silicide layer 50 is formed by reacting the metal of the epitaxial silicon layer 10 with the metal of the adhesive layer 5A being a lower layer. As described above, since the metal of the adhesive layer 5A reacts with the silicon of the epitaxial silicon layer 10, the reaction with the silicon of the bonding portion 2, which is its lower layer, is suppressed. It is formed on the metal layer 6 using a metal such as tungsten (W) or aluminum (Al).
상술한 바와 같이, 본 발명은 금속 배선 형성시에 접착층 및 금속 이온 확산 방지층 역할을 하는 배리어 금속층을 형성하기 전에 콘택홀 저면을 이루는 접합부 표면에 저온의 고밀도 플라즈마에 의해 형성된 실리콘 이온을 이용하여 에피텍셜 실리콘층을 형성하고, 이후 배리어 금속층 형성 및 후속 열공정에 의해 금속-실리사이드층을 형성하므로써, 열공정 동안 배리어 금속층의 금속이 에피텍셜 실리콘층의 실리콘과 반응하여 균일한 두께 및 농도를 갖는 금속-실리사이드층이 형성되므로 인해 기존 공정과 같이 접합부의 실리콘 이온과의 반응이 억제되고, 또한 저온에서 실리콘층이 형성되기 때문에, 접합부에서 금속-실리사이드층이 과도하게 형성되거나 응집 현상이 발생하므로 인한 콘택 저항 증가 및 접합부의 누설 전류 증가 등의 문제를 해결할 수 있어, 소자의 신뢰성 향상 및 소자의 고집적화, 초고속화를 실현시킬 수 있다.As described above, the present invention is epitaxial using silicon ions formed by low-temperature, high-density plasma on the junction surface forming the bottom of the contact hole before forming the barrier metal layer serving as the adhesive layer and the metal ion diffusion barrier layer when forming the metal wiring. By forming a silicon layer and then forming a metal-silicide layer by barrier metal layer formation and subsequent thermal process, the metal of the barrier metal layer reacts with the silicon of the epitaxial silicon layer during the thermal process to have a uniform thickness and concentration. Due to the formation of the silicide layer, the reaction with the silicon ions of the junction is suppressed as in the conventional process, and since the silicon layer is formed at a low temperature, the contact resistance due to excessive formation of the metal-silicide layer or the aggregation phenomenon at the junction. Solve problems such as increased and increased leakage current at junction It can, high integration of devices and improve the reliability of the device, it is possible to realize a high-speed screen.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023926A KR100313417B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a wiring in a seminconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019990023926A KR100313417B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a wiring in a seminconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20010003573A KR20010003573A (en) | 2001-01-15 |
| KR100313417B1 true KR100313417B1 (en) | 2001-11-05 |
Family
ID=19594867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019990023926A KR100313417B1 (en) | 1999-06-24 | 1999-06-24 | Method of forming a wiring in a seminconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100313417B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100460065B1 (en) * | 2002-07-12 | 2004-12-04 | 주식회사 하이닉스반도체 | method for manufacturing bit line in semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030054019A (en) * | 2001-12-24 | 2003-07-02 | 주식회사 하이닉스반도체 | Method for manufacturing of semiconductor device |
-
1999
- 1999-06-24 KR KR1019990023926A patent/KR100313417B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100460065B1 (en) * | 2002-07-12 | 2004-12-04 | 주식회사 하이닉스반도체 | method for manufacturing bit line in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20010003573A (en) | 2001-01-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6903462B2 (en) | Chemical vapor deposition of titanium | |
| JP3358328B2 (en) | Method of forming high melting point metal film | |
| TWI289328B (en) | Nickel silicide with reduced interface roughness | |
| US5397744A (en) | Aluminum metallization method | |
| US7402512B2 (en) | High aspect ratio contact structure with reduced silicon consumption | |
| JPH04257227A (en) | Forming method for wiring | |
| US6524951B2 (en) | Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon | |
| US6221760B1 (en) | Semiconductor device having a silicide structure | |
| US6433434B1 (en) | Apparatus having a titanium alloy layer | |
| US5731226A (en) | Low temperature method of manufacturing epitaxial titanium silicide | |
| KR100313417B1 (en) | Method of forming a wiring in a seminconductor device | |
| KR100443353B1 (en) | Method for forming barrier metal layer of semiconductor device to embody thermal stability and prevent contact resistance from being increased by high temperature heat treatment | |
| KR0124489B1 (en) | Forming method of titanium nitride film for semiconductor device | |
| US6597042B1 (en) | Contact with germanium layer | |
| KR100333358B1 (en) | A method of forming contact in semiconductor device | |
| Taguwa et al. | Low contact resistance metallization for gigabit scale DRAM's using fully-dry cleaning by Ar/H/sub 2/ECR plasma | |
| JP2871943B2 (en) | Method for manufacturing semiconductor device | |
| JPH11288923A (en) | Trench forming method and manufacture thereof | |
| JP3225696B2 (en) | Film formation method | |
| KR100691935B1 (en) | Method of forming a metal wiring in a semiconductor device | |
| KR100255518B1 (en) | Method of fabricating tungsten polycide of semiconductor device | |
| CN112687611A (en) | Interconnect structure and method of forming the same | |
| KR20000041873A (en) | Formation method of metal distribution | |
| KR100187675B1 (en) | Method of forming barrier metal layer in a semiconductor device | |
| KR20060032919A (en) | Chemical vapor deposition methods of forming an ohmic layer and a barrier metal layer in a semiconductor device using plasma |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20090922 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |