CN112687611A - Interconnect structure and method of forming the same - Google Patents
Interconnect structure and method of forming the same Download PDFInfo
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- CN112687611A CN112687611A CN201910999275.3A CN201910999275A CN112687611A CN 112687611 A CN112687611 A CN 112687611A CN 201910999275 A CN201910999275 A CN 201910999275A CN 112687611 A CN112687611 A CN 112687611A
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Abstract
The application discloses an interconnection structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein a metal layer is formed in the substrate; forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening, and the opening exposes the metal layer; forming an amorphous silicon layer on the side wall of the opening, wherein the amorphous silicon layer is exposed out of the surface of the metal layer; forming a conductive connecting layer in the opening by taking the metal layer as a growth substrate; and after the conductive connecting layer is formed, annealing treatment is carried out, so that the amorphous silicon layer reacts with the material on the side wall surface of the conductive connecting layer to form a silicide adhesion layer. The application also discloses an interconnection structure. The interconnect structure and the method of forming the same disclosed herein improve the performance of the interconnect structure.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to an interconnect structure and a method for forming the same.
Background
With the development of semiconductor technology, the integration level of very large scale integrated circuit chips has reached the scale of billions or even billions of devices, and multilayer metal interconnection technology is widely used. With the continuous reduction of the process size, the copper interconnection process is widely used, but the diffusion of copper can cause the toxic effect of the device, so that the tungsten metal with excellent step coverage rate and filling property can be gradually used as the filling metal in the contact holes of the source, drain and gate regions.
There is also a need for improved methods of forming interconnect structures to increase adhesion between metal fillers and dielectric layers.
Disclosure of Invention
In view of the above-described shortcomings of the prior art, it is an object of the present application to provide an interconnect structure and a method of forming the same that improves the performance of the interconnect structure.
One aspect of the present application provides a method of forming an interconnect structure, including: providing a substrate, wherein a metal layer is formed in the substrate; forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening, and the opening exposes the metal layer; forming an amorphous silicon layer on the side wall of the opening, wherein the amorphous silicon layer is exposed out of the surface of the metal layer; forming a conductive connecting layer in the opening by taking the metal layer as a growth substrate; and after the conductive connecting layer is formed, annealing treatment is carried out, so that the amorphous silicon layer reacts with the material on the side wall surface of the conductive connecting layer to form a silicide adhesion layer.
Optionally, the temperature of the annealing treatment is 400 ℃ to 600 ℃.
Optionally, the annealing treatment has an annealing time of 5 minutes to 10 minutes.
Optionally, the method of forming the amorphous silicon layer includes: forming an amorphous silicon material layer on the side wall and the bottom of the opening; and removing the amorphous silicon material layer at the bottom of the opening to form the amorphous silicon layer.
Optionally, a process of forming the amorphous silicon material layer is a physical vapor deposition process or a chemical vapor deposition process.
Optionally, the process of removing the amorphous silicon material layer at the bottom of the opening includes: and carrying out ion bombardment on the amorphous silicon material layer positioned at the bottom of the opening.
Optionally, the ions used for the ion bombardment are inert gas ions, and the inert gas ions include Ar ions.
Optionally, in the step of forming the amorphous silicon layer, the amorphous silicon layer is in contact with the dielectric layer; after the silicide adhesion layer is formed, the silicide adhesion layer is in contact with the dielectric layer.
Optionally, the material of the conductive connection layer comprises tungsten, and the material of the silicide adhesion layer comprises tungsten silicide.
Optionally, the process of forming the conductive connection layer is a selective chemical vapor deposition process.
Optionally, the thickness of the amorphous silicon layer is 1 nm to 3 nm.
Optionally, the silicide adhesion layer has a thickness of 1 nm to 5 nm.
Optionally, the material of the conductive connection layer comprises cobalt or tungsten.
The present invention also provides an interconnect structure comprising: a substrate having a metal layer therein; a dielectric layer on the substrate, the dielectric layer having an opening therethrough; a conductive connection layer in the opening, a bottom surface of the conductive connection layer being in contact with the metal layer; and the silicide adhesion layer is positioned between the conductive connecting layer and the dielectric layer and is in contact with the side wall of the conductive connecting layer.
Optionally, the material of the conductive connection layer comprises tungsten, and the material of the silicide adhesion layer comprises tungsten silicide.
Optionally, the silicide adhesion layer has a thickness of 1 nm to 5 nm.
Optionally, the silicide adhesion layer is in contact with the dielectric layer.
The technical scheme of the invention has the following beneficial effects:
according to the forming method of the interconnection structure, the metal layer is used as a growth substrate, the conductive connecting layer is formed in the opening, and the material of the conductive connecting layer grows from the bottom of the opening to the top of the opening, so that premature sealing of the opening in the forming process of the conductive connecting layer is avoided, and the quality of the conductive connecting layer is improved. Before forming the conductive connecting layer, forming an amorphous silicon layer on the side wall of the opening, and after forming the conductive connecting layer, carrying out annealing treatment to enable the amorphous silicon layer to react with the material on the side wall surface of the conductive connecting layer to form a silicide adhesion layer. The material of the silicide adhesion layer is formed by the reaction of the material of the side wall surface of the conductive connecting layer and the amorphous silicon layer, so that the adhesion between the silicide adhesion layer and the conductive connecting layer is greatly improved. Based on better adhesiveness between the amorphous silicon layer and the dielectric layer and between the silicide adhesion layer and the conductive connection layer, the gap defect between the conductive connection layer and the dielectric layer is avoided, and the performance of the interconnection structure is improved.
Further, in the step of forming the amorphous silicon layer, the amorphous silicon layer is in contact with the dielectric layer; after the silicide adhesion layer is formed, the silicide adhesion layer is in contact with the dielectric layer. Because the metal layer is used as a growth substrate to form the conductive connecting layer in the opening, the process of forming the conductive connecting layer on the metal layer does not depend on an adhesion layer with larger resistance, and further provides a process foundation for the contact of the amorphous silicon layer and the dielectric layer. Because the silicide adhesion layer is in direct contact with the dielectric layer and the resistance of the silicide adhesion layer is low, the adhesion layer with high resistance between the dielectric layer and the conductive connecting layer is avoided, so that the resistance of the interconnection structure is reduced, and the RC delay effect is reduced.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a method of forming an interconnect structure;
FIG. 2 is a flow chart of a method of forming an interconnect structure according to an embodiment of the present application;
fig. 3 to 8 are schematic structural diagrams illustrating a process of forming an interconnect structure according to an embodiment of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
As shown in fig. 1, a method for forming an interconnect structure includes: providing a semiconductor substrate 1, wherein the semiconductor substrate 1 is provided with a metal layer 3; forming a dielectric layer 2 on a semiconductor substrate 1, wherein the dielectric layer 2 is provided with an opening penetrating through the dielectric layer 2; forming an adhesion layer 5 on the side and bottom of the opening; the conductive connection layer 4 on the adhesion layer 5 is formed in the opening.
In the above method, the conductive connection layer 4 is made of tungsten, the conductive connection layer 4 is made of titanium nitride by a chemical vapor deposition process, and it is necessary to form the adhesion layer 5, and if the adhesion layer 5 is not formed, the conductive connection layer 4 cannot be directly formed on the metal layer 3 by the chemical vapor deposition process.
Since the adhesion layer 5 is also formed on the sidewall of the opening, the space reserved for the conductive connection layer 4 is affected, and thus the opening is sealed too early in the process of forming the conductive connection layer 4, and the quality of the conductive connection layer 4 is reduced. Secondly, the adhesion layer 5 is made of titanium nitride, so that the resistance is high, and the RC delay effect of the interconnection structure is aggravated.
In another method, a selective epitaxial growth process is adopted to directly form a conductive connecting layer on the surface of the metal layer, and the conductive connecting layer is formed by growing the material from bottom to top, so that the premature sealing of an opening in the forming process of the conductive connecting layer is avoided, and the quality of the conductive connecting layer is improved. And secondly, the conductive connecting layer formed by the adhesion layer of the titanium nitride material can be avoided.
However, since the material of the conductive connection layer grows from bottom to top, after the conductive connection layer is formed, a gap is easily formed between the sidewall of the conductive connection layer and the dielectric layer, and the adhesion between the sidewall of the conductive connection layer and the dielectric layer is poor, so that the conductive connection layer is easily corroded by some solutions in the subsequent process or is filled by byproducts in the subsequent process, resulting in poor performance of the interconnection structure.
In order to solve the above problem, an embodiment of the present invention provides an interconnect structure forming method, as shown in fig. 2, including the following steps:
step S11: providing a substrate, wherein a metal layer is formed in the substrate;
step S12: forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening, and the opening exposes the metal layer;
step S13: forming an amorphous silicon layer on the side wall of the opening, wherein the amorphous silicon layer is exposed out of the surface of the metal layer;
step S14: forming a conductive connecting layer in the opening by taking the metal layer as a growth substrate;
step S15: and after the conductive connecting layer is formed, annealing treatment is carried out, so that the amorphous silicon layer reacts with the material on the side wall surface of the conductive connecting layer to form a silicide adhesion layer.
The above steps are described in detail with reference to fig. 3 to 8. It should be noted that methods that perform the above and below steps in other orders also fall within the scope of the present disclosure.
As shown in fig. 3, a substrate 100 is provided, the substrate 100 having a metal layer 102 formed therein.
The substrate 100 may be silicon (Si), germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials, such as gallium arsenide and other III-V compounds. The material of the substrate 100 may be one of monocrystalline silicon, polycrystalline silicon, and amorphous silicon. The material of the substrate 100 may also be a silicon germanium compound. The substrate 100 may also be a silicon-on-insulator structure or a silicon-on-epitaxial layer structure. In the substrate 100, a semiconductor device (not shown), such as a metal oxide semiconductor device having a gate, a source, and a drain, may be formed.
The metal layer 102 formed in the substrate 100 may be tungsten (W), cobalt (Co), or other metal material suitable for selectively growing a conductive connection layer thereon. In the present embodiment, the material of the metal layer 102 includes cobalt. The metal layer 102 may be formed in the trench of the substrate 100 by a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), or the like. The trenches may be formed by various etching processes.
As shown in fig. 4, a dielectric layer 200 is formed on the substrate 100, the dielectric layer 200 has an opening 202 therein, and the opening 202 exposes the metal layer 102.
The dielectric layer 200 may be silicon oxide, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, or the like. In this embodiment, the dielectric layer 200 may be silicon oxide (SiO)2). The dielectric layer 200 may have a thickness of 100 nm to 4000 nm. The dielectric layer 200 may be formed by physical vapor deposition, chemical vapor deposition, or the like. Optionally, in some embodiments, the thickness of the dielectric layer 200 may be 800 nm to 900 nm.
The forming method of the opening 202 may be spin-coating a photoresist on the surface of the dielectric layer 200, forming an opening pattern in the photoresist after an exposure and development process, then etching to form the opening 202, introducing oxygen plasma after etching, and ashing to remove the remaining photoresist.
Next, an amorphous silicon layer is formed on the sidewall of the opening 202, and the amorphous silicon layer exposes the surface of the metal layer 102.
The amorphous silicon layer (α -Si) is used to react with the material of the sidewall surface of the conductive connection layer to be filled into the opening 202 in the subsequent annealing treatment to form a silicide adhesion layer, so as to stabilize the conductive connection layer in the opening 202, and simultaneously prevent a gap from occurring between the conductive connection layer and the dielectric layer 200, thereby improving the performance of the interconnection structure. In the present embodiment, in the step of forming the amorphous silicon layer, the amorphous silicon layer is in contact with the dielectric layer 200. Since the conductive connection layer is formed in the opening 202 by using the metal layer 102 as a growth substrate, the process of forming the conductive connection layer on the metal layer 102 is not dependent on an adhesion layer with a large resistance, thereby providing a process basis for contacting the amorphous silicon layer with the dielectric layer 200.
In this embodiment, the step of forming the amorphous silicon layer 301 may include: referring to fig. 5, a layer 300 of amorphous silicon material is formed on the sidewalls and bottom of the opening 202; referring to fig. 6, the amorphous silicon material layer 300 at the bottom of the opening 202 is removed to form an amorphous silicon layer 301.
In the present embodiment, the amorphous silicon material layer 300 may be formed by physical vapor deposition or chemical vapor deposition. In this embodiment, the thickness of the amorphous silicon layer 301 may be 1 nm to 3 nm.
In this embodiment, in the step of forming the amorphous silicon layer 301, the amorphous silicon layer 301 is in contact with the dielectric layer 200.
In this embodiment, the process of removing the amorphous silicon material layer 300 at the bottom of the opening 202 includes: the layer of amorphous silicon material 300 at the bottom of the opening 202 is ion bombarded. The ion bombardment process is a process of bombarding the surface of a solid with particles (ions or neutral atoms, molecules) with certain energy, so that the atoms or molecules near the surface of the solid obtain enough energy to finally escape from the surface of the solid. The bombarding particles used in the ion bombardment process may be inert gas ions. In this embodiment, ion bombardment may be performed using argon (Ar) ions. For example, in a plasma processing apparatus which performs ion bombardment, the power of the first high-frequency power source may be set to 150W, and the power of the second high-frequency power source may be set to 300W. In this embodiment, in the ion bombardment process, the movement direction of the bombarding particles is perpendicular to the surface of the substrate 100. In this embodiment, the amorphous silicon material layer 300 is also formed on the top surface of the dielectric layer 200, and in the process of removing the amorphous silicon material layer 300 at the bottom of the opening 202, the amorphous silicon material layer 300 on the top surface of the dielectric layer 200 is also removed.
As shown in fig. 7, a conductive connection layer 400 is formed in the opening 202 by using the metal layer 102 as a growth substrate.
The material of the conductive connection layer 400 may be cobalt or tungsten. In this embodiment, the material of the conductive connection layer 400 includes tungsten. In the present embodiment, the process of forming the conductive connection layer 400 is a selective chemical vapor deposition process. In some embodiments, the conductive connection layer 400 at least fills the opening 202.
The metal layer 102 is used as a growth substrate, a conductive connection layer is formed in the opening 202, and the material of the conductive connection layer 400 is grown from the bottom of the opening 202 to the top of the opening 202, so that premature sealing of the opening 202 in the forming process of the conductive connection layer 400 is avoided, and the quality of the conductive connection layer 400 is improved. As shown in fig. 8, after the conductive connection layer 400 is formed, an annealing process is performed to react the amorphous silicon layer 301 with the material of the sidewall surface of the conductive connection layer 400 to form the silicide adhesion layer 302. In the present embodiment, the material of the conductive connection layer 400 includes tungsten, and the material of the silicide adhesion layer 302 includes tungsten silicide. In some embodiments, the silicide adhesion layer 302 may comprise tungsten disilicide.
The thickness of the silicide adhesion layer 302 may be 1 nm to 5 nm.
The annealing treatment may be Rapid Thermal Processing (RTP), which can complete the steps of the annealing treatment in a shorter time.
The temperature of the annealing treatment is 400 ℃ to 1300 ℃. In this embodiment, the temperature of the annealing treatment is 400 ℃ to 600 ℃. The annealing time of the annealing treatment may be 1 minute to 15 minutes. In the present embodiment, the annealing time of the annealing treatment is 5 minutes to 10 minutes. It should be noted that other combinations of annealing temperatures and annealing times are within the scope of the present application, as long as the combination enables the amorphous silicon layer 301 to react with the material of the sidewall surface of the conductive connection layer 400 to form the silicide adhesion layer 302. After the silicide adhesion layer 302 is formed, the silicide adhesion layer 302 is in direct contact with the dielectric layer 200. Since the silicide adhesion layer 302 is in direct contact with the dielectric layer 200 and the resistance of the silicide adhesion layer 302 is low, an adhesion layer with high resistance between the dielectric layer 200 and the conductive connection layer 400 is avoided, so that the resistance of the interconnection structure is reduced and the RC delay effect is reduced.
Since the material of the silicide adhesion layer 302 is formed by the reaction of the material of the sidewall surface of the conductive connection layer 400 and the amorphous silicon layer 301, the adhesion between the silicide adhesion layer 302 and the conductive connection layer 400 is greatly improved. Based on the good adhesion between the amorphous silicon layer 301 and the dielectric layer 200 and the good adhesion between the silicide adhesion layer 302 and the conductive connection layer 400, the gap defect between the conductive connection layer 400 and the dielectric layer 200 is avoided, and the performance of the interconnection structure is improved.
Accordingly, the present application also provides an interconnect structure (see fig. 8). The interconnect structure includes: a substrate 100, the substrate 100 having a metal layer 102 therein; a dielectric layer 200 on the substrate 100, the dielectric layer 200 having an opening 202 therethrough; a conductive connection layer 400 located in the opening 202, a bottom surface of the conductive connection layer 400 being in contact with the metal layer 102; and a silicide adhesion layer 302, the silicide adhesion layer 302 being between the conductive connection layer 400 and the dielectric layer 200 and being in contact with a sidewall of the conductive connection layer 400.
In some embodiments, the material of the conductive connection layer 400 comprises tungsten and the material of the silicide adhesion layer 302 comprises tungsten silicide. In some embodiments, the silicide adhesion layer 302 has a thickness of 1 nm to 5 nm. In some embodiments, the silicide adhesion layer 302 is in contact with the dielectric layer 200.
The silicide adhesion layer 302 has good adhesion with the dielectric layer 200 and the conductive connection layer 400, so that the gap defect between the conductive connection layer 400 and the dielectric layer 200 is avoided, and the performance of the interconnection structure is improved. Moreover, the resistance of the silicide adhesion layer 302 is low, so that the resistance of the interconnection structure is reduced, and the RC delay effect is reduced.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
Claims (17)
1. A method for forming an interconnect structure, comprising:
providing a substrate, wherein a metal layer is formed in the substrate;
forming a dielectric layer on the substrate, wherein the dielectric layer is provided with an opening, and the opening exposes the metal layer;
forming an amorphous silicon layer on the side wall of the opening, wherein the amorphous silicon layer is exposed out of the surface of the metal layer;
forming a conductive connecting layer in the opening by taking the metal layer as a growth substrate; and
and after the conductive connecting layer is formed, annealing treatment is carried out, so that the amorphous silicon layer reacts with the material on the side wall surface of the conductive connecting layer to form a silicide adhesion layer.
2. The method of claim 1, wherein the annealing is performed at a temperature of 400 ℃ to 600 ℃.
3. The method of claim 1, wherein the annealing is performed for an annealing time of 5 minutes to 10 minutes.
4. The method of forming an interconnect structure of claim 1, wherein forming the amorphous silicon layer comprises:
forming an amorphous silicon material layer on the side wall and the bottom of the opening; and
and removing the amorphous silicon material layer at the bottom of the opening to form the amorphous silicon layer.
5. The method of claim 4, wherein the process of forming the amorphous silicon material layer is a physical vapor deposition process or a chemical vapor deposition process.
6. The method for forming an interconnect structure according to claim 4, wherein the process for removing the amorphous silicon material layer at the bottom of the opening comprises: and carrying out ion bombardment on the amorphous silicon material layer positioned at the bottom of the opening.
7. The method of claim 6, wherein the ions used for the ion bombardment are inert gas ions, and the inert gas ions comprise Ar ions.
8. The method of forming an interconnect structure according to claim 1, wherein in the step of forming the amorphous silicon layer, the amorphous silicon layer is in contact with the dielectric layer; after the silicide adhesion layer is formed, the silicide adhesion layer is in contact with the dielectric layer.
9. The method of claim 1, wherein the conductive link layer comprises tungsten and the silicide adhesion layer comprises tungsten silicide.
10. The method of claim 1, wherein the process of forming the conductive connection layer is a selective chemical vapor deposition process.
11. The method of claim 1, wherein the amorphous silicon layer has a thickness of 1 nm to 3 nm.
12. The method of claim 1, wherein the silicide adhesion layer has a thickness of 1 nm to 5 nm.
13. The method of claim 1, wherein a material of the conductive connection layer comprises cobalt or tungsten.
14. An interconnect structure, comprising:
a substrate having a metal layer therein;
a dielectric layer on the substrate, the dielectric layer having an opening therethrough;
a conductive connection layer in the opening, a bottom surface of the conductive connection layer being in contact with the metal layer; and
and the silicide adhesion layer is positioned between the conductive connecting layer and the dielectric layer and is in contact with the side wall of the conductive connecting layer.
15. The interconnect structure of claim 14 wherein said conductive link layer material comprises tungsten and said silicide adhesion layer material comprises tungsten silicide.
16. The interconnect structure of claim 14 wherein said silicide adhesion layer has a thickness of 1 nm to 5 nm.
17. The interconnect structure of claim 14 wherein said silicide adhesion layer is in contact with said dielectric layer.
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| EP0257948A2 (en) * | 1986-08-25 | 1988-03-02 | AT&T Corp. | Conductive via plug for CMOS devices |
| CA1282189C (en) * | 1988-06-15 | 1991-03-26 | Vu Quoc Ho | Use of adherent layer for filling contact holes for semiconductor devices |
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| US5510296A (en) * | 1995-04-27 | 1996-04-23 | Vanguard International Semiconductor Corporation | Manufacturable process for tungsten polycide contacts using amorphous silicon |
| US6331480B1 (en) * | 1999-02-18 | 2001-12-18 | Taiwan Semiconductor Manufacturing Company | Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material |
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