CN102237492A - Formation method for phase-change memory unit - Google Patents
Formation method for phase-change memory unit Download PDFInfo
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- CN102237492A CN102237492A CN2010101688716A CN201010168871A CN102237492A CN 102237492 A CN102237492 A CN 102237492A CN 2010101688716 A CN2010101688716 A CN 2010101688716A CN 201010168871 A CN201010168871 A CN 201010168871A CN 102237492 A CN102237492 A CN 102237492A
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Abstract
The invention provides a formation method for a phase-change memory unit. The method comprises the following steps: providing a semiconductor substrate on which a first metal layer is formed, wherein a first interlayer dielectric layer which is formed on the semiconductor substrate covers on the first metal layer, a barrier layer and a second interlayer dielectric layer cover on the surface of the first interlayer dielectric layer, an opening is formed among the second interlayer dielectric layer, the barrier layer and the first interlayer dielectric layer and exposes out of the first metal layer; forming adhesion layers on the side wall and the bottom of the opening; filling in the opening by using a second metal layer; etching the second metal layer in the opening to flush with the barrier layer; etching the adhesion layer so that the etched adhesion layer is higher than the etched second metal layer; and filling the opening by using a phase-change material layer. The phase-change memory unit formed by the method in the invention has the advantage of excellent performances.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of phase-changing memory unit formation method.
Background technology
Semiconductor memory is the basis of information technology, has the market of hundreds billion of U.S. dollars in the world.Candidate as follow-on nonvolatile semiconductor memory, phase transition storage (Phase ChangeRandom Access Memory, PCRAM) because read at a high speed, high erasable number of times, non-volatile, advantages such as component size is little, strong motion low in energy consumption, anti-and radioresistance, paid close attention to widely.
Phase transition storage is a kind of semiconductor memory based on phase-change material, and described phase-change material is exactly the material that can carry out the electricity conversion between amorphous state and polycrystalline attitude.The phase transition storage basic principle is to utilize electric impulse signal to act on the device cell, make phase-change material between amorphous state and polycrystalline attitude, reversible transition take place, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude realizes the operation that writes, wipes and read of information.In being 1506973 Chinese patent, publication number can find more information relevant with PCRAM.
The structure of the unit of existing phase transition storage as shown in Figure 1, comprise: the Semiconductor substrate 100 that is formed with the first metal layer 140, for prevent that the first metal layer 140 from spreading in Semiconductor substrate 100, the bottom of described the first metal layer 140 and sidewall are formed with first adhesion layer 141; Be formed on Semiconductor substrate 100 surface successively and cover first interlayer dielectric layer 110, barrier layer 120 and second interlayer dielectric layer 130 of described the first metal layer 140; Be formed in first interlayer dielectric layer 110 and the barrier layer 120 and second metal level 150 that is electrically connected with the first metal layer 140; For prevent that second metal level from spreading in first interlayer dielectric layer 110, described second metal level, 150 bottoms and sidewall are formed with second adhesion layer 151; Be formed in second interlayer dielectric layer 130 and barrier layer 120 and the phase-change material layers that is electrically connected with second metal level 150.
The concrete manufacture process of the phase-change material layers of the unit of existing phase transition storage is as described below usually: form the first metal layer 140 and first adhesion layer 141 that is formed on the first metal layer 140 bottoms and sidewall in Semiconductor substrate 100 earlier, form first interlayer dielectric layer 110 then successively, the barrier layer 120 and second interlayer dielectric layer 130, described second interlayer dielectric layer 130 of etching successively again, the barrier layer 120 and first interlayer dielectric layer 110 form opening (not shown), second adhesion layer 151 is formed on sidewall and bottom at described opening, adopt second metal level 150 to fill and lead up described opening then, afterwards, adopt etching technics etching second metal level 150 until the barrier layer, adopt etching technics etching second adhesion layer 151 until flushing then, adopt phase-change material to fill and lead up described opening at last with second metal level 150.
But, etching second adhesion layer 151 until with technology that second metal level 150 flushes in, because existing etching technics defective, please refer to Fig. 2, second adhesion layer 151 of Fig. 2 and second metal level 150 with phase-change material interface location (a position among Fig. 2), second adhesion layer 151 after the etching can be lower than second metal level 150, form above-mentioned pattern former because: stop that second metal level 150 spreads to interlayer dielectric layer because existing second adhesion layer 151 act as, usually thickness is thinner, be about 20 nanometer to 100 nanometers, in etching during than second adhesion layer 151 of minimal thickness, existing employing CF
4Etching technics be difficult to accurately control etching precision, behind intact second adhesion layer 151 of etching, usually second adhesion layer 151 after the etching can be lower than second metal level 150, can be formed with the space in a position, when follow-up filling phase-change material layers, the space of a position is difficult to be filled into phase-change material layers, and above-mentioned space can make the phase-changing memory unit job insecurity, causes the reliability decrease of phase transition storage.
Summary of the invention
The technical problem that the present invention solves provides a kind of phase-changing memory unit formation method, prevents from the space to occur between adhesion layer and the metal level.
For addressing the above problem, the invention provides a kind of phase-changing memory unit formation method, comprise: the Semiconductor substrate that is formed with the first metal layer is provided, described Semiconductor substrate is formed with first interlayer dielectric layer that covers the first metal layer, the described first interlayer dielectric layer surface coverage has the barrier layer and second interlayer dielectric layer, is formed in second interlayer dielectric layer, barrier layer and first interlayer dielectric layer and exposes the opening of the first metal layer; Adhesion layer is formed on sidewall and bottom at described opening; Adopt second metal level to fill up described opening; Second metal level in the etching opening flushes with the barrier layer; The etching adhesion layer also makes adhesion layer after the etching be higher than second metal level after the etching; Adopt phase-change material layers to fill up described opening.
The invention provides a kind of unit formation method of phase transition storage, form the phase-changing memory unit that adhesion layer is higher than second metal level, thereby can not form the space at the interface at the adhesion layer and second metal level, avoid the softening space that is filled into of phase-change material layers to cause the uncontrollable phenomenon of phase-change material layers resistance variations to occur, improve the reliability of phase transition storage; Further, the present invention adopts the etching technics of the high fluoro-gas of carbon amount, and optimizes Cl
2And BCl
3Mist and the ratio of fluoro-gas, etching technics provided by the invention is adopted in the difficult control of speed when avoiding the adhesion layer etching, can form the adhesion layer that is higher than second metal level.
Description of drawings
Fig. 1 is the structural representation of existing phase-changing memory unit;
Fig. 2 is the structural representation that is formed with the phase-changing memory unit in space between adhesion layer and the metal level;
Fig. 3 is the schematic flow sheet of the phase-changing memory unit formation method of one embodiment of the present of invention;
Fig. 4 to Fig. 9 is the process schematic diagram of the phase-changing memory unit formation method of one embodiment of the present of invention.
Embodiment
By the background technology analysis as can be known, existing phase-changing memory unit is owing to form the defective of technology, with reference to figure 2, second adhesion layer 151 that forms can be lower than second metal level 150, when filling phase-change material layers, can second adhesion layer 151 and second metal level 150 form the space with phase-change material interface location (a position shown in Figure 2), job insecurity causes the reliability decrease of phase transition storage.
The present inventor is through a large amount of experiments, find because in phase-changing memory unit work, reversible transition takes place in phase-change material layers (the particularly germanium antimony tellurium alloy phase-change material that extensively adopts) between amorphous state and polycrystalline attitude, low-resistance when high resistant during by the resolution amorphous state and polycrystalline attitude, writing of realization information, the operation of wiping and reading, but ruckbildung can appear in phase-change material layers in the reversible transition process, in the phase-changing memory unit in space is arranged, softening phase-change material layers is filled in the space, thereby make and the space occurs in the phase-change material layers, the resistance of the low-resistance phase-change material layers when making high resistant when amorphous state was clearly arranged originally and polycrystalline attitude is owing to difficult phenomenon appears differentiating in the existence that the space is arranged, concrete is having under the situation in space, the resistance of phase-change material layers also shows high-impedance state during the polycrystalline attitude, make that the resistance variations of the amorphous state of phase-changing memory unit and polycrystalline attitude is unreliable, low-resistance when high resistant during amorphous state and polycrystalline attitude can't be differentiated, thereby causes phase-changing memory unit to lose efficacy.
For this reason, the present inventor provides a kind of phase-changing memory unit formation method of optimization, can not form the space between metal level and adhesion layer, avoids because the phase-changing memory unit that defective workmanship causes lost efficacy.
Fig. 3 is the schematic flow sheet of the phase-changing memory unit formation method of one embodiment of the present of invention, and Fig. 4 to Fig. 9 is the process schematic diagram of the phase-changing memory unit formation method of one embodiment of the present of invention.
Please refer to Fig. 3, phase-changing memory unit of the present invention forms method step and comprises:
Step S101 provides the Semiconductor substrate that is formed with the first metal layer;
Step S102 forms first interlayer dielectric layer, barrier layer and second interlayer dielectric layer that covers described the first metal layer successively at described substrate surface;
Step S103 forms opening in described first interlayer dielectric layer, barrier layer and second interlayer dielectric layer, described opening exposes the first metal layer;
Step S104 forms adhesion layer in the sidewall and the bottom of described opening;
Step S105 adopts second metal level to fill up described opening;
Step S106, described second metal level of etching flushes with the barrier layer until second metal level;
Step S107, the etching adhesion layer also makes adhesion layer after the etching be higher than second metal level after the etching;
Step S108 adopts phase-change material layers to fill up described opening.
Particularly, with reference to figure 4, Semiconductor substrate 200 is provided, the material of described Semiconductor substrate 200 can be a kind of in monocrystalline silicon, the amorphous silicon, the material of described Semiconductor substrate 200 also can be a silicon Germanium compound, and described Semiconductor substrate 200 can also be an epitaxial layer structure on silicon-on-insulator (SOI, Silicon On Insulator) structure or the silicon, it is also to be noted that described Semiconductor substrate 200 can also be to adopt the semiconductor FEOL to be formed with the silicon substrate of semiconductor unit.
Continuation is with reference to figure 4, with the Semiconductor substrate 200 that is formed with dielectric layer is example, in Semiconductor substrate 200, form the first metal layer 210, the material of described the first metal layer 210 can be aluminium, copper, tungsten or nickel, in order to prevent that the first metal layer 210 from spreading in Semiconductor substrate 200, can also be the barrier layer of titanium nitride at the sidewall and the bottom formation material of described the first metal layer 210.
Described the first metal layer 210 is used for providing electric impulse signal to phase-changing memory unit, the formation technology of described first metal 210 is specially: adopt etching technics to form a contact hole (not shown) in described Semiconductor substrate 200, on the barrier layer that titanium nitride is formed on the sidewall and the bottom of described contact hole, adopt tungsten to fill and lead up described contact hole and form the first metal layer 210.
With reference to figure 5, adopt chemical vapor deposition method at described Semiconductor substrate 200 surface depositions first interlayer dielectric layer 220, described first interlayer dielectric layer 220 covers described the first metal layer 210, the material of described first interlayer dielectric layer 220 can be selected from the silica of silica or doping, for example the boron-doping silica, mix the silica of phosphor silicon oxide or boron-doping phosphorus.
Continuation is with reference to figure 5, adopt chemical vapor deposition method to form barrier layer 230 on first interlayer dielectric layer, 220 surfaces, described barrier layer 230 is used for the etching barrier layer as subsequent etching technology, the material on described barrier layer 230 is selected from the material that has the selective etch ratio with second interlayer dielectric layer 240 of follow-up formation, for example silicon nitride or silicon oxynitride, consider that based on interlayer film matching and reduction interlayer film k value preferred material is a silicon oxynitride.
Continuation is with reference to figure 5,230 surfaces form second interlayer dielectric layer 240 on the barrier layer to adopt chemical vapor deposition method, described second interlayer dielectric layer 240 is used for each metal level of electric separating phase transformation memory cell, the material of described second interlayer dielectric layer 240 can be selected from the silica of silica or doping, for example the boron-doping silica, mix the silica of phosphor silicon oxide or boron-doping phosphorus.
With reference to figure 6, adopt etching technics in described second interlayer dielectric layer 240, barrier layer 230 and first interlayer dielectric layer 220, to form opening 241, described opening 241 exposes the first metal layer 210.
Particularly, the formation step of described opening 241 comprises: form photoresist layer (not shown) on described second interlayer dielectric layer 240 surfaces, described photoresist layer can adopt spin coating proceeding to form; Adopt exposure imaging technology that the opening figure on the opening mask is transferred on the photoresist layer, form photoresist figure (not shown); With described photoresist figure is mask, the using plasma etching technics is described first interlayer dielectric layer 220 of etching successively, barrier layer 230 forms the first opening 241a until exposing first interlayer dielectric layer 220, adopts cineration technics to remove the photoresist figure after etching is finished.
Form side wall layer 242 at the sidewall of described opening 241a, the formation technology of side wall layer 242 is depositing operation, and the material of side wall layer 242 is selected from silicon nitride, and described side wall is used to limit the live width of second opening of follow-up formation, the auxiliary littler opening of size that forms.
Along the first opening 241a that is formed with side wall layer 242 second interlayer dielectric layer 240 is carried out etching,, form the second opening 241b until exposing the first metal layer 210; In to second interlayer dielectric layer, 240 etchings, adopt selective etch technology, can etching side wall layer 242 when making etching second interlayer dielectric layer 240, thus make side wall layer 242 limit the size of the second opening 241b.
With reference to figure 7, adopt depositing operation to form adhesion layer 250 in the sidewall and the bottom of described opening 241, described adhesion layer 250 materials are selected from titanium nitride or tantalum nitride, and described adhesion layer 250 prevents that second metal level 260 of follow-up formation from spreading in first interlayer dielectric layer 220.
Continuation is with reference to figure 7, in described opening 241 (with reference to figure 6), insert second metal level 260, described second metal layer material 260 is selected from aluminium, copper, tungsten or nickel, and described second metal level is electrically connected the first metal layer, for phase-changing memory unit provides electric impulse signal.
Inserting second metal level 260, can adopt etching technics that second unnecessary metal level 260 and adhesion layer 250 are removed,, making second metal level 260 and adhesion layer 250 flush with second interlayer dielectric layer 240 until exposing second interlayer dielectric layer 240.
With reference to figure 8, etching second metal level 260 flushes with barrier layer 230 until second metal level 260, and using plasma etching technics etching second metal level 260 is selected different etching technics parameters for use for second metal layer material 260 of selecting different materials for use.
In the present embodiment, be that tungsten is done exemplary illustrated with second metal level 260, concrete etching technics parameter is: etching cavity pressure is 10～15 millitorrs, bias power 500W～700W, power 30W～60W, oxygen flow are 15～35SCCM, SF
6Flow is 80～120SCCM, N
2Flow is 5～15SCCM, adopts above-mentioned etching technics, and etching second metal level 260 flushes with barrier layer 230 until second metal level 260.
Continuation is with reference to figure 8, second metal level 260 of etching adhesion layer 250 after described adhesion layer 250 is higher than etching, the inventor is through a large amount of experiments, find that existing etching technics etching is too fast, when etching adhesion layer 250, be easier to over etching, and the material of described adhesion layer 250 also is electric conducting material, if adhesion layer 250 etchings are not enough, adhesion layer 250 makes phase transition storage remain at conducting state, the low-resistance when high resistant in the time of can't differentiating amorphous state and polycrystalline attitude.
Through further research of the present invention, when finding high 0 nanometer to 50 nanometer of described adhesion layer 250 to the second metal levels 260, the best performance of phase-changing memory unit, but existing processes can't reach high etching precision like this.
For this reason, the present inventor adopts the etching technics of optimizing when etching adhesion layer 250, be that titanium nitride is an example with adhesion layer 250 materials, adopts Cl
2With BCl
3Mist (Cl
2With BCl
3Volume ratio be 2: 1) with high fluoro-gas such as the C of phosphorus content
4F
8, C
5F
8Or C
4F
6As etching gas, wherein fluoro-gas that phosphorus content is high and Cl
2With BCl
3Mist satisfy certain proportion, thereby reach the speed of accurate control etching adhesion layer 250.
Concrete, select C for use
4F
8As etching gas, Cl
2With BCl
3Mist and C
4F
8Volume ratio be 0.8～5; Select C for use
4F
6As etching gas, Cl
2With BCl
3Mist and C
4F
6Volume ratio be 1.1～10; Select C for use
5F
8As etching gas, Cl
2With BCl
3Mist and C
5F
8Volume ratio be 1～10.
As an embodiment, the etching technics parameter is: etching cavity pressure is 10 millitorrs, bias power 325W, power 48W, BCl
3Flow is 15SCCM, Cl
2Flow is 30SCCM, C
4F
8Flow is 10SCCM, and etching adhesion layer 250 is higher than second metal level 260 until described adhesion layer 250.
With reference to figure 9, adopt phase-change material layers 270 to fill up described opening 241.
Described phase-change material layers 270 is selected from the germanium antimony tellurium alloy phase-change material, by etch step before as can be known, adhesion layer 250 is higher than second metal level 260, because adhesion layer 250 is relatively thin and adhesion layer 250 sticks to the sidewall of opening, do not have the space between second metal level 260 and the adhesion layer 250, when filling phase-change material layers 270, phase-change material layers 270 is the described opening 241 of complete filling easily, be difficult for forming and fill the space, thereby the phase-changing memory unit performance that forms is more excellent.
The invention provides a kind of phase-changing memory unit formation method, form the phase-changing memory unit that adhesion layer is higher than second metal level, thereby can adhesion layer and the space of formation at the interface of second metal level, avoiding phase-change material is to be filled into the uncontrollable phenomenon of resistance variations that the space causes in work, improves the phase transition storage reliability; Further, the present invention adopts the etching technics of optimization, and etching technics provided by the invention is adopted in the difficult control of speed when avoiding the adhesion layer etching, can form the adhesion layer that is higher than second metal level.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (10)
1. a phase-changing memory unit formation method is characterized in that, comprising:
The Semiconductor substrate that is formed with the first metal layer is provided, described Semiconductor substrate is formed with first interlayer dielectric layer that covers the first metal layer, the described first interlayer dielectric layer surface coverage has the barrier layer and second interlayer dielectric layer, is formed in second interlayer dielectric layer, barrier layer and first interlayer dielectric layer and exposes the opening of the first metal layer;
Adhesion layer is formed on sidewall and bottom at described opening;
Adopt second metal level to fill up described opening;
Second metal level in the etching opening flushes with the barrier layer;
The etching adhesion layer also makes adhesion layer after the etching be higher than second metal level after the etching;
Adopt phase-change material layers to fill up described opening.
2. phase-changing memory unit formation method as claimed in claim 1 is characterized in that, described adhesion layer is higher than second metal level, 0 nanometer to 50 nanometer.
3. phase-changing memory unit formation method as claimed in claim 1 is characterized in that, the etching technics of described adhesion layer is for adopting Cl
2With BCl
3Mist and the high fluoro-gas of phosphorus content carry out etching as etching gas.
4. phase-changing memory unit formation method as claimed in claim 3 is characterized in that Cl
2With BCl
3Volume ratio be 2: 1.
5. phase-changing memory unit formation method as claimed in claim 3 is characterized in that, the fluoro-gas that described carbon amount is high is C
4F
8, C
5F
8Perhaps C
4F
6
6. phase-changing memory unit formation method as claimed in claim 5 is characterized in that, selects C for use
4F
8As etching gas, Cl
2And BCl
3Mist and C
4F
8Volume ratio be 0.8～5.
7. phase-changing memory unit formation method as claimed in claim 5 is characterized in that, selects C for use
4F
6As etching gas, Cl
2And BCl
3Mist and C
4F
6Volume ratio be 1.1～10.
8. phase-changing memory unit formation method as claimed in claim 5 is characterized in that, selects C for use
5F
8As etching gas, Cl
2And BCl
3Mist and C
5F
8Volume ratio be 1～10.
9. phase-changing memory unit formation method as claimed in claim 1 is characterized in that, phase-change material layers is the germanium antimony tellurium alloy phase-change material.
10. phase-changing memory unit formation method as claimed in claim 1 is characterized in that, barrier material is titanium nitride or tantalum nitride.
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| CN103840077A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Methods for manufacturing phase change memory |
| CN103972383A (en) * | 2013-02-01 | 2014-08-06 | 厦门博佳琴电子科技有限公司 | Phase change memory with diode selection element array structure and manufacturing method thereof |
| CN103972385A (en) * | 2013-02-01 | 2014-08-06 | 厦门博佳琴电子科技有限公司 | Embedded phase change memory and manufacture method thereof |
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| CN103840077A (en) * | 2012-11-27 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Methods for manufacturing phase change memory |
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| CN103972383A (en) * | 2013-02-01 | 2014-08-06 | 厦门博佳琴电子科技有限公司 | Phase change memory with diode selection element array structure and manufacturing method thereof |
| CN103972383B (en) * | 2013-02-01 | 2016-10-05 | 厦门博佳琴电子科技有限公司 | The Ovonics unified memory of diode selecting element arrays structure and manufacture method |
| CN103972384B (en) * | 2013-02-01 | 2016-12-28 | 厦门博佳琴电子科技有限公司 | Ovonics unified memory material transition region manufacture method and Ovonics unified memory |
| CN103972385B (en) * | 2013-02-01 | 2017-06-20 | 厦门博佳琴电子科技有限公司 | A kind of embedded phase change memory and its manufacture method |
| CN104282797A (en) * | 2013-07-08 | 2015-01-14 | 中芯国际集成电路制造(上海)有限公司 | Forming method for film adjustable in reflectivity |
| CN105449101A (en) * | 2014-09-01 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method of forming phase change random access memory (PCRAM) cell |
| CN105449101B (en) * | 2014-09-01 | 2018-06-01 | 中芯国际集成电路制造(上海)有限公司 | The forming method of phase-changing memory unit |
| CN105870053A (en) * | 2015-01-22 | 2016-08-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN106159085A (en) * | 2015-04-01 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | Phase-change memory cell and preparation method thereof |
| CN105609631A (en) * | 2015-11-09 | 2016-05-25 | 宁波时代全芯科技有限公司 | Phase change storage device and manufacture method thereof |
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