CN102237492B - Formation method for phase-change memory unit - Google Patents

Formation method for phase-change memory unit Download PDF

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CN102237492B
CN102237492B CN 201010168871 CN201010168871A CN102237492B CN 102237492 B CN102237492 B CN 102237492B CN 201010168871 CN201010168871 CN 201010168871 CN 201010168871 A CN201010168871 A CN 201010168871A CN 102237492 B CN102237492 B CN 102237492B
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layer
phase change
etching
metal layer
change memory
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CN102237492A (en
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张翼英
洪中山
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Abstract

一种相变存储器单元形成方法,包括:提供形成有第一金属层的半导体衬底,所述半导体衬底形成有覆盖第一金属层的第一层间介质层,所述第一层间介质层表面覆盖有阻挡层和第二层间介质层,形成在第二层间介质层、阻挡层和第一层间介质层内并暴露出第一金属层的开口;在所述开口的侧壁和底部形成粘附层;采用第二金属层填满所述开口;刻蚀开口内的第二金属层与阻挡层齐平;刻蚀粘附层并使得刻蚀后的粘附层高于刻蚀后的第二金属层;采用相变材料层填满所述开口。 A phase change memory cell forming method, comprising: providing a semiconductor substrate having a first metal layer, the semiconductor substrate is formed a first interlayer dielectric layer covering the first metal layer, a first interlayer dielectric the surface layer is covered with the barrier layer and the second interlayer dielectric layer formed in the second interlayer dielectric layer, barrier layer and the first interlayer dielectric layer and an opening to expose the first metal layer; sidewall of the opening forming an adhesive layer and a bottom; with a second metal layer fills said opening; a second metal layer and the etching barrier layer in an opening flush; and etching such that the adhesive layer adhered to the etched engraving storey after etching the second metal layer; uses phase change material layer fills the opening. 本发明形成的相变存储器单元性能较优。 Phase change memory cell of the present invention is formed of performance better.

Description

相变存储器单元形成方法 The method of forming a phase change memory cell

技术领域 FIELD

[0001] 本发明涉及半导体制造领域,特别涉及一种相变存储器单元形成方法。 [0001] The present invention relates to semiconductor manufacture, and particularly to a method of forming a phase change memory cell.

背景技术 Background technique

[0002] 半导体存储器是信息技术的基础,在全球范围内具有数千亿美金的市场。 [0002] The semiconductor memory is the basis of information technology, having hundreds of billions of dollars in the market worldwide. 作为下一代的非易失性半导体存储器的候选者,相变存储器(Phase ChangeRandom AccessMemory, PCRAM)由于高速读取、高可擦写次数、非易失性、元件尺寸小、功耗低、抗强震动和抗辐射等优点,得到广泛的关注。 As a candidate for the nonvolatile semiconductor memory of the next generation, phase change memory (Phase ChangeRandom AccessMemory, PCRAM) due to the high-speed reading, rewritable high frequency nonvolatile small element size, low power consumption, anti shock and anti-radiation, etc., to get attention.

[0003] 相变存储器是一种基于相变材料的半导体存储器,所述相变材料就是在非晶态和多晶态之间可以进行电转换的材料。 [0003] The phase change memory is a semiconductor memory based on the phase change material, the phase change material is between amorphous and polycrystalline materials can be electrically switchable. 相变存储器基本原理是利用电脉冲信号作用于器件单元上,使相变材料在非晶态与多晶态之间发生可逆相变,通过分辨非晶态时的高阻与多晶态时的低阻,实现信息的写入、擦除和读出的操作。 The basic principle of a phase change memory using electric pulse signal is applied to a device unit, the phase change material in the amorphous state a reversible phase change between the crystalline state and the occurrence of multiple, distinguished by high resistance when an amorphous polycrystalline state low resistance to achieve writing, erasing and readout operations. 在公开号为1506973的中国专利中可以发现更多与PCRAM有关的信息。 In Chinese Patent Publication No. 1506973 More information can be found in the PCRAM related.

[0004] 现有的相变存储器的单元的结构如图1所示,包括:形成有第一金属层140的半导体衬底100,为防止第一金属层140向半导体衬底100内扩散,所述第一金属层140的底部和侧壁形成有第一粘附层141 ;依次形成在半导体衬底100表面并覆盖所述第一金属层140的第一层间介质层110、阻挡层120和第二层间介质层130 ;形成在第一层间介质层110和阻挡层120内并与第一金属层140电连接的第二金属层150 ;为防止第二金属层向第一层间介质层110内扩散,所述第二金属层150底部和侧壁形成有第二粘附层151 ;形成在在第二层间介质层130和阻挡层120内并与第二金属层150电连接的相变材料层。 The structural unit [0004] The conventional phase change memory shown in Figure 1, comprising: a first metal layer 140 is formed with a semiconductor substrate 100, diffused into the semiconductor substrate 140 to prevent the first metal layer 100, the said bottom and sidewalls of the first metal layer 140 is formed with a first adhesive layer 141; 100 are sequentially formed on the surface of the semiconductor substrate and covering the first layer of the interlayer dielectric layer 140 of the first metal layer 110, barrier layer 120 and the second interlayer dielectric layer 130; a second metal layer 150 formed on the first interlayer dielectric layer 110 and barrier layer 120 and electrically connected to the first metal layer 140; to prevent the second metal layer to the first interlayer dielectric diffusion layer 110, a second adhesive layer 151 of the second side wall 150 and a bottom metal layer is formed; formed in and electrically connected to the second metal layer 150 in the second interlayer dielectric layer 130 and barrier layer 120 phase change material layer.

[0005] 现有的相变存储器的单元的相变材料层具体制造过程通常如下所述:在半导体衬底100内先形成第一金属层140和形成在第一金属层140底部和侧壁的第一粘附层141,然后依次形成第一层间介质层110、阻挡层120和第二层间介质层130,再依次刻蚀所述第二层间介质层130、阻挡层120和第一层间介质层110形成开口(未图示),在所述开口的侧壁和底部形成第二粘附层151,然后采用第二金属层150填平所述开口,之后,采用刻蚀工艺刻蚀第二金属层150直至阻挡层,然后采用刻蚀工艺刻蚀第二粘附层151直至与第二金属层150齐平,最后采用相变材料填平所述开口。 [0005] The phase change material layer unit of a conventional phase change memory manufacturing process of the concrete are generally as follows: first the semiconductor substrate 100 is formed in a first metal layer 140 and 140 formed on the bottom and sidewalls of the first metal layer, the first adhesive layer 141, followed by forming a first interlayer dielectric layer 110, barrier layer 120 and the second interlayer dielectric layer 130, and then sequentially etching the second interlayer dielectric layer 130, barrier layer 120 and the first the interlayer dielectric layer 110 is formed an opening (not shown), a second adhesive layer 151 is formed on the sidewalls and bottom of the opening, and then using a second metal layer 150 to fill the opening, after the etching process using engraved etching the second metal layer until the barrier layer 150, and then etched using an etching process until the second adhesive layer 151 and the second metal layer 150 is flush Finally, the phase change material fill opening.

[0006] 但是,在刻蚀第二粘附层151直至与第二金属层150齐平的工艺中,由于现有的刻蚀工艺缺陷,请参考图2,在图2的第二粘附层151和第二金属层150的与相变材料界面位置(图2中的a位置),刻蚀后的第二粘附层151会低于第二金属层150,形成上述形貌的原因为:由于现有第二粘附层151作用为阻挡第二金属层150向层间介质层扩散,通常厚度比较薄,约为20纳米至100纳米,在刻蚀较薄厚度的第二粘附层151时,现有的采用CF4的刻蚀工艺很难精确控制刻蚀精度,在刻蚀完第二粘附层151后,通常刻蚀后的第二粘附层151会低于第二金属层150,在a位置会形成有空隙,在后续填充相变材料层时,a位置的空隙很难填充进相变材料层,上述空隙会使得相变存储器单元工作不稳定,导致相变存储器的可靠性下降。 [0006] However, in the process of etching the second adhesive layer 151 and the second metal layer 150 until it is flush, since the defects in the conventional etching process, please refer to FIG. 2, the second adhesive layer 2 of FIG. 151 and causes the second metal layer (a position in FIG. 2) phase change material interface position, a second adhesive layer 151 will be less than 150 after etching a second metal layer 150, forming the topography of: Since the conventional second adhesive layer 151 functions as a barrier metal layer 150 to the second diffusion layer, an interlayer dielectric, typically relatively thin thickness of about 20 nm to 100 nm, the second adhesive layer 151 is etched thin thickness , the conventional etching process using CF4 difficult to precisely control the etching accuracy, after etching the second adhesive layer 151, second adhesive layer 151 will typically after etching the second metal layer is less than 150 It will form a gap at a position, while in a subsequent filling phase change material layer, the void is difficult to position a phase change material layer filled into the void so that phase change memory cell will be unstable, leading to the reliability of phase change memory decline. 发明内容 SUMMARY

[0007] 本发明解决的技术问题是提供一种相变存储器单元形成方法,防止粘附层与金属层之间出现空隙。 [0007] The present invention solves the technical problem is to provide a method of forming a phase change memory cell, to prevent a gap occurs between the adhesive layer and the metal layer.

[0008] 为解决上述问题,本发明提供一种相变存储器单元形成方法,包括:提供形成有第一金属层的半导体衬底,所述半导体衬底形成有覆盖第一金属层的第一层间介质层,所述第一层间介质层表面覆盖有阻挡层和第二层间介质层,形成在第二层间介质层、阻挡层和第一层间介质层内并暴露出第一金属层的开口;在所述开口的侧壁和底部形成粘附层;采用第二金属层填满所述开口;刻蚀开口内的第二金属层与阻挡层齐平;刻蚀粘附层并使得刻蚀后的粘附层高于刻蚀后的第二金属层;采用相变材料层填满所述开口。 [0008] In order to solve the above problems, the present invention provides a method of forming a phase change memory cell, comprising: providing a semiconductor substrate having a first metal layer, formed on the semiconductor substrate a first metal layer covering the first layer, interlayer dielectric layer, the first layer with a surface of the interlayer dielectric layer covers the barrier layer and the second interlayer dielectric layer formed on the second interlayer dielectric layer, the barrier layer and the first interlayer dielectric layer and exposing the first metal opening layer; forming the adhesive layer on the sidewalls and bottom of the opening; with a second metal layer fills said opening; a second metal layer and the etching barrier layer in an opening flush; and etching the adhesion layer storey such that the adhesive on the etched second metal layer after etching; using phase change material layer fills the opening.

[0009] 本发明提供一种相变存储器的单元形成方法,形成粘附层高于第二金属层的相变存储器单元,从而在粘附层与第二金属层的界面处不会形成空隙,避免相变材料层软化填充进空隙导致相变材料层电阻变化不可控现象出现,提高相变存储器的可靠性;进一步的,本发明采用碳量高的含氟气体的刻蚀工艺,并优化Cl2和BCl3的混合气体与含氟气体的比例,避免粘附层刻蚀时速率较难控制,采用本发明提供的刻蚀工艺,能够形成高于第二金属层的粘附层。 [0009] The present invention provides a method of forming a phase change memory cell is formed on the second metal layer adhered storey phase change memory cell, thereby forming voids at the interface of the adhesive layer and the second metal layer, phase change material layer to avoid softening filled into the voids cause the phase change material layer uncontrolled variable resistance phenomenon, improve the reliability of the phase change memory; further, the present invention uses an etching process of a high carbon content of the fluorine-containing gas, and optimize Cl2 and the ratio of a mixed gas of BCl3 and fluorine-containing gas, avoid the adhesive layer is difficult to control etching rate, the etching process using the present invention provides, the adhesive layer can be formed over the second metal layer.

附图说明 BRIEF DESCRIPTION

[0010] 图1是现有的相变存储器单元的结构示意图; [0010] FIG. 1 is a schematic structural diagram of a conventional phase change memory cell;

[0011] 图2是粘附层与金属层之间形成有空隙的相变存储器单元的结构示意图; [0011] FIG. 2 is a schematic structural diagram of a phase change memory cell gap is formed between the adhesive layer and the metal layer;

[0012] 图3是本发明的一个实施例的相变存储器单元形成方法的流程示意图; [0012] FIG. 3 is a flowchart of an embodiment of a phase change memory cell of the present invention is a method of forming a schematic view;

[0013] 图4至图9为本发明的一个实施例的相变存储器单元形成方法的过程示意图。 During a phase change memory embodiment [0013] FIGS. 4 to 9 of the present invention is a method of forming a schematic units.

具体实施方式 Detailed ways

[0014] 由背景技术分析可知,现有的相变存储器单元由于形成工艺的缺陷,参考图2,形成的第二粘附层151会低于第二金属层150,在填充相变材料层时,会在第二粘附层151和第二金属层150的与相变材料界面位置(图2所示的a位置)形成空隙,工作不稳定,导致相变存储器的可靠性下降。 When the [0014] analysis shows a background art, the conventional phase change memory cells due to the formation of defects in the process, with reference to FIG. 2, a second adhesive layer 151 formed below the second metal layer 150, phase change material layer filling It will be the second adhesive layer 151 and the second metal layer 150 and the phase change material interface position (a position shown in FIG. 2) to form voids, unstable, resulting in decreased reliability of phase change memory.

[0015] 本发明的发明人经过大量的实验,发现由于在相变存储器单元工作中,相变材料层(特别是广泛采用的锗锑碲合金相变材料)在非晶态与多晶态之间发生可逆相变,通过分辨非晶态时的高阻与多晶态时的低阻,实现信息的写入、擦除和读出的操作,但是在可逆相变过程中相变材料层会出现软化现象,在有空隙的相变存储器单元中,软化的相变材料层填充至空隙内,从而使得相变材料层内出现空隙,使得原来有清晰的非晶态时的高阻与多晶态时的低阻相变材料层的电阻由于有空隙的存在而出现分辨困难现象,具体的在有空隙的情况下,多晶态时相变材料层的电阻也表现出高阻状态,,使得相变存储器单元的非晶态和多晶态的电阻变化不可靠,非晶态时的高阻与多晶态时的低阻无法分辨,从而导致相变存储器单元失效。 [0015] The inventors of the present invention after a large number of experiments and found that since the phase change memory cell work, the phase change material layer (germanium antimony tellurium alloy used widely, in particular phase change material) in the amorphous state of the polycrystalline state reversible phase change occurs between, distinguished by low resistance when the high impedance state when the polycrystalline amorphous achieve writing, erasing and readout operations, but the reversible phase transformation phase change material layer may softening occurs, the phase change memory cell voids, the softening of phase change material layer filled into the void, so that voids occur within the phase change material layer, so that the high resistance amorphous state that there is a clear polycrystalline when the low resistance state resistance of the phase change material layer due to the presence of voids is difficult to distinguish the phenomenon occurs, particularly in the case where a gap, polycrystalline phase change resistance material layer also exhibits high-impedance state such that ,, variable resistance amorphous and polycrystalline phase change memory cell is not reliable, when the high resistance amorphous state and low resistance polycrystalline state when not distinguished, resulting in a phase change memory cell failure.

[0016] 为此,本发明的发明人提供一种优化的相变存储器单元形成方法,不会在金属层与粘附层之间形成空隙,避免由于工艺缺陷导致的相变存储器单元失效。 [0016] To this end, the present invention provides an optimized method of forming a phase change memory cell, a gap is not formed between the metal layer and the adhesive layer, since the phase change memory cell to avoid process failure due to a defect. [0017] 图3是本发明的一个实施例的相变存储器单元形成方法的流程示意图,图4至图9为本发明的一个实施例的相变存储器单元形成方法的过程示意图。 [0017] FIG. 3 is a schematic flow diagram of the present invention, a phase change memory cell forming method of the embodiment, during a phase change memory cell embodiment of FIG. 4 to FIG. 9 of the present invention, a method of forming a schematic view.

[0018] 请参考图3,本发明的相变存储器单元形成方法步骤包括: [0018] Please refer to FIG. 3, the phase change memory cell forming method of the present invention comprises the step of:

[0019] 步骤S101,提供形成有第一金属层的半导体衬底; [0019] In step S101, the providing a semiconductor substrate having a first metal layer;

[0020] 步骤S102,在所述衬底表面依次形成覆盖所述第一金属层的第一层间介质层、阻挡层和第二层间介质层; [0020] step S102, sequentially formed on the substrate surface a first interlayer dielectric layer covering the first metal layer, the barrier layer and the second interlayer dielectric layer;

[0021] 步骤S103,在所述第一层间介质层、阻挡层和第二层间介质层内形成开口,所述开 [0021] In step S103, the opening formed in said first interlayer dielectric layer, barrier layer and the second interlayer dielectric layer, said opening

口暴露出第一金属层; Opening exposing the first metal layer;

[0022] 步骤S104,在所述开口的侧壁和底部形成粘附层; [0022] In step S104, the adhesive layer is formed on the sidewalls and bottom of the opening;

[0023] 步骤S105,采用第二金属层填满所述开口; [0023] In step S105, using the second metal layer fills said opening;

[0024] 步骤S106,刻蚀所述第二金属层直至第二金属层与阻挡层齐平; [0024] In step S106, etching the second metal layer until the second metal layer is flush with the barrier layer;

[0025] 步骤S107,刻蚀粘附层并使得刻蚀后的粘附层高于刻蚀后的第二金属层; [0025] step S107, and the adhesive layer is etched so that the etched storey adhered to the etched second metal layer;

[0026] 步骤S108,采用相变材料层填满所述开口。 [0026] Step S108, using the phase change material layer fills the opening.

[0027] 具体地,参考图4,提供半导体衬底200,所述半导体衬底200的材质可以是单晶硅、非晶硅中的一种,所述半导体衬底200的材质也可以是硅锗化合物,所述半导体衬底200还可以是绝缘体上娃(SOI, Silicon On Insulator)结构或娃上外延层结构,还需要注意的是,所述半导体衬底200还可以`是采用半导体前段工艺形成有半导体单元的硅衬底。 [0027] In particular, with reference to Figure 4, there is provided a semiconductor substrate 200, a material of the semiconductor substrate 200 may be a single crystal silicon, amorphous silicon, a material of the semiconductor substrate 200 may be silicon germanium compounds, the semiconductor substrate 200 also may be an insulator on the baby (SOI, Silicon on insulator) structure or the epitaxial layer structure on a baby, is also noted that the semiconductor substrate 200 may be a semiconductor front-end process is the use of ` a silicon substrate formed with a semiconductor unit.

[0028] 继续参考图4,以形成有介质层的半导体衬底200为例,在半导体衬底200内形成第一金属层210,所述第一金属层210的材料可以为铝、铜、钨或者镍,为了防止第一金属层210向半导体衬底200内扩散,还可以在所述第一金属层210的侧壁和底部形成材料为氮化钛的阻挡层。 [0028] With continued reference to FIG. 4, Example 200 to form the dielectric layer of the semiconductor substrate, a first metal layer 210 is formed in the semiconductor substrate 200, the first metal layer material 210 may be aluminum, copper, tungsten, , or nickel, for preventing diffusion of the first metal layer 200 to the semiconductor substrate 210, the material may also be a barrier layer of titanium nitride is formed on the sidewalls and bottom of the first metal layer 210.

[0029] 所述第一金属层210用于向相变存储器单兀提供电脉冲信号,所述第一金属210的形成工艺具体为:采用刻蚀工艺在所述半导体衬底200内形成一个接触孔(未图示),在所述接触孔的侧壁和底部形成氮化钛的阻挡层,采用金属钨填平所述接触孔形成第一金属层210。 [0029] The first metal layer 210 for providing an electrical pulse signal to the single phase change memory Wu, the process of forming a first metal 210 is specifically: using an etching process for forming a contact in the semiconductor substrate 200 holes (not shown), to form a titanium nitride barrier layer on the sidewalls and bottom of the contact hole, tungsten metal layer, a first metal 210 is formed to fill the contact hole.

[0030] 参考图5,米用化学气相沉积工艺在所述半导体衬底200表面沉积第一层间介质层220,所述第一层间介质层220覆盖所述第一金属层210,所述第一层间介质层220的材料可以选自氧化硅或者掺杂的氧化硅,例如掺硼氧化硅、掺磷氧化硅或者掺硼磷的氧化硅。 [0030] Referring to FIG 5, m is deposited by a chemical vapor deposition process, a first interlayer dielectric layer 220 on a surface of the semiconductor substrate 200, the first interlayer dielectric layer 220 covering the first metal layer 210, the material of the first interlayer dielectric layer 220 may be selected from silicon oxide or doped silicon oxide, for example, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron oxide or phosphorus-doped silicon.

[0031] 继续参考图5,采用化学气相沉积工艺在第一层间介质层220表面形成阻挡层230,所述阻挡层230用于作为后续刻蚀工艺的刻蚀阻挡层,所述阻挡层230的材料选自与后续形成的第二层间介质层240具有选择性刻蚀比的材料,例如氮化硅或者氮氧化硅,基于层间薄膜匹配性和降低层间薄膜k值考虑,优选材料为氮氧化硅。 [0031] With continued reference to FIG. 5, barrier layer 230 is formed by a chemical vapor deposition process on the surface of the first interlayer dielectric layer 220, the barrier layer 230 as an etch barrier layer for subsequent etching process, the barrier layer 230 the second material is selected from the interlayer dielectric layer 240 is formed of a material having a subsequent selective etching ratio such as silicon nitride or silicon oxynitride, matching the interlayer film and reduce the value of k considered interlayer film, preferably a material based on silicon oxynitride.

[0032] 继续参考图5,采用化学气相沉积工艺在阻挡层230表面形成第二层间介质层240,所述第二层间介质层240用于电隔离相变存储器单元的各金属层,所述第二层间介质层240的材料可以选自氧化硅或者掺杂的氧化硅,例如掺硼氧化硅、掺磷氧化硅或者掺硼磷的氧化硅。 [0032] With continued reference to FIG. 5, a chemical vapor deposition process for forming a second interlayer dielectric layer 240 on the surface of the barrier layer 230, the second interlayer dielectric layer 240 for electrically isolating the phase change memory cell of the metal layers, the material of said second interlayer dielectric layer 240 may be selected from silicon oxide or doped silicon oxide, for example, boron-doped silicon oxide, phosphorus-doped silicon oxide, boron oxide or phosphorus-doped silicon.

[0033] 参考图6,采用刻蚀工艺在所述第二层间介质层240、阻挡层230和第一层间介质层220内形成开口241,所述开口241暴露出第一金属层210。 [0033] Referring to FIG 6, an etching process using the second interlayer dielectric layer 240, barrier layer 230 and the first interlayer dielectric layer 220 is formed an opening 241, 241 of the first metal layer 210 to expose the opening.

[0034] 具体地,所述开口241的形成步骤包括:在所述第二层间介质层240表面形成光刻胶层(未图示),所述光刻胶层可以采用旋涂工艺形成;采用曝光显影工艺将开口掩膜版上的开口图形转移至光刻胶层上,形成光刻胶图形(未图示);以所述光刻胶图形为掩膜,采用等离子体刻蚀工艺依次刻蚀所述第一层间介质层220,阻挡层230直至暴露出第一层间介质层220,形成第一开口241a,刻蚀完成后采用灰化工艺去除光刻胶图形。 [0034] In particular, the step of forming the opening 241 comprises: forming a photoresist layer (not shown), the photoresist layer may be formed using a spin coating process on a surface of the second interlayer dielectric layer 240; the exposure and development process using the openings in the mask pattern transferred to the photoresist layer, forming a photoresist pattern (not shown); to the photoresist pattern as a mask, plasma etching process successively etching the first interlayer dielectric layer 220, barrier layer 230 is exposed until the first interlayer dielectric layer 220, a first opening 241a is formed, after the completion of the etching resist pattern is removed using an ashing process.

[0035] 在所述开口241a的侧壁形成侧墙层242,侧墙层242的形成工艺为沉积工艺,侧墙层242的材料选自氮化硅,所述侧墙用于限定后续形成的第二开口的线宽,辅助形成尺寸更小的开口。 [0035] The side wall 241a of the spacer layer 242 is formed an opening process of forming the spacer layer 242 is a deposition process, a material selected from silicon nitride spacer layer 242, the spacer used to define the subsequent formation of the line width of the second opening, the secondary opening is formed smaller in size.

[0036] 沿形成有侧墙层242的第一开口241a对第二层间介质层240进行刻蚀,直至暴露出第一金属层210,形成第二开口241b ;在对第二层间介质层240刻蚀的时候采用选择性刻蚀工艺,使得刻蚀第二层间介质层240的同时不会刻蚀侧墙层242,从而使得侧墙层242限定第二开口241b的大小。 [0036] A first opening is formed along a sidewall 242 of layer 241a of the second interlayer dielectric layer 240 is etched until exposing the first metal layer 210, a second opening 241b is formed; in the second interlayer dielectric layer 240 when etching selective etching process, such etching the second interlayer dielectric layer 240 while not etching the spacer layer 242, so that the spacer layer 242 defines the size of the second opening 241b.

[0037] 参考图7,采用沉积工艺在所述开口241的侧壁和底部形成粘附层250,所述粘附层250材料选自氮化钛或者氮化钽,所述粘附层250防止后续形成的第二金属层260向第一层间介质层220内扩散。 [0037] Referring to Figure 7, a deposition process using the adhesive layer 250 is formed in the sidewall and a bottom opening 241, the adhesion layer 250 material is selected from titanium nitride or tantalum nitride, the adhesion layer 250 prevented the second metal layer 260 is formed subsequent diffusion into the first interlayer dielectric layer 220.

[0038] 继续参考图7,在所述开口241(参考图6)内填入第二金属层260,所述第二金属层材料260选自铝、铜、钨或者镍,所述第二金属层电连接第一金属层,为相变存储器单元提供电脉冲信号。 [0038] With continued reference to FIG. 7, the opening 241 (refer to FIG. 6) filled in the second metal layer 260, the second metal layer 260 material is selected from aluminum, copper, tungsten, or nickel, the second metal a first layer of metal layer is electrically connected to provide an electrical pulse signal is a phase change memory cells.

[0039] 在填入第二金属层260,可以采用刻蚀工艺将多余的第二金属层260和粘附层250去除,直至暴露出第二层间介质层240,使得第二金属层260和粘附层250与第二层间介质层240齐平。 [0039] filled into the second metal layer 260, an etching process may be employed excess second metal layer 260 and an adhesive layer 250 is removed until exposing the second interlayer dielectric layer 240, such that the second metal layer 260 and a second adhesive layer 250 and the interlayer dielectric layer 240 are flush.

[0040] 参考图8,刻蚀第二金属层260直至第二金属层260与阻挡层230齐平,采用等离子体刻蚀工艺刻蚀第二金属层260,对于选用不同材料的第二金属层材料260选用不同的刻蚀工艺参数。 [0040] Referring to Figure 8, the second metal layer 260 is etched until the second metal layer 260 is flush with the barrier layer 230 using a plasma etching process for etching the second metal layer 260, the second metal layer for use different materials material 260 use different etching parameters.

[0041] 在本实施例中,以第二金属层260为钨做示范性说明,具体刻蚀工艺参数为:刻蚀腔体压力为10〜15毫托,偏置功率500W〜700W,电源功率30W〜60W,氧气流量为15〜35SCCM,SF6流量为80〜120SCCM,N2流量为5〜15SCCM,采用上述的刻蚀工艺,刻蚀第二金属层260直至第二金属层260与阻挡层230齐平。 [0041] In the present embodiment, the second metal layer 260 is made of tungsten exemplary illustration, specific etch process parameters: an etching chamber pressure was 10 ~ 15 mTorr, a bias power 500W~700W, Power 30W~60W, flow rate of oxygen 15~35SCCM, SF6 flow 80~120SCCM, N2 flow 5~15SCCM, the above-described etching process, etching the second metal layer 260 until the second metal layer 260 and barrier layer 230 together level.

[0042] 继续参考图8,刻蚀粘附层250直至所述粘附层250高于刻蚀后的第二金属层260,发明人经过大量实验,发现现有的刻蚀工艺刻蚀过快,在刻蚀粘附层250时较容易过刻蚀,并且所述粘附层250的材料也为导电材料,如果粘附层250刻蚀不够的话,粘附层250使得相变存储器始终保持在导通状态,无法分辨非晶态时的高阻与多晶态时的低阻。 [0042] With continued reference to FIG. 8, the adhesive layer 250 is etched until the adhesive layer 250 than the second metal layer 260 is etched, after a lot of experiments the inventors found that a conventional etching process for etching the excessive when the adhesive layer 250 is etched through the etching is easier, and the adhesive material layer 250 is also an electrically conductive material, if the adhesive layer 250 is etched is not enough, so that the adhesive layer 250 remains in a phase change memory conductive state, can not distinguish between high resistance and low resistance at the time of the polycrystalline amorphous.

[0043] 经过本发明的进一步研究,发现所述粘附层250比第二金属层260高O纳米至50纳米时,相变存储器单元的性能最优,但现有的工艺无法达到如此高的刻蚀精度。 [0043] Upon further study of the present invention found that the adhesion layer 250 is higher than the second metal layer is so high O 260 nm to 50 nm when the phase-change memory cell optimum performance, but the conventional technology can not be achieved etching accuracy.

[0044] 为此,本发明的发明人在刻蚀粘附层250时采用优化的刻蚀工艺,以粘附层250材料为氮化钛为例,采用Cl2与BCl3的混合气体(Cl2与BCl3的体积比为2 : I)与含碳量高的含氟气体如C4F8X5F8或C4F6作为刻蚀气体,其中含碳量高的含氟气体与Cl2与BCl3的混合气体满足一定比例,从而达到精确控制刻蚀粘附层250的速度。 [0044] To this end, the inventors of the present invention in the adhesive layer 250 is etched using the etching process optimization, the adhesive layer 250 is a titanium nitride material, for example, using a mixed gas of BCl3 and Cl2 (Cl2 and BCl3 the volume ratio of 2: I) with a high carbon content of the fluorine-containing gas such as C4F6 as an etching gas or C4F8X5F8, wherein the high carbon content fluorine-containing gas and a mixed gas of Cl2 and BCl3 to meet a certain percentage, so as to achieve precise control the etching rate of the adhesive layer 250.

[0045] 具体的,选用C4F8作为刻蚀气体,Cl2与BCl3的混合气体与C4F8的体积比为O. 8〜5 ;选用C4F6作为刻蚀气体,Cl2与BCl3的混合气体与C4F6的体积比为1.1〜10 ;选用C5F8作为刻蚀气体,Cl2与BCl3的混合气体与C5F8的体积比为I〜10。 [0045] In particular, the choice of C4F8 as an etching gas, a mixed gas of BCl3 and Cl2 C4F8 volume ratio O. 8~5; is selected C4F6 as an etching gas, a mixed gas of BCl3 and Cl2 and the volume ratio of C4F6 1.1~10; selection C5F8 as an etching gas, a mixed gas of BCl3 and Cl2 C5F8 volume ratio I~10.

[0046] 作为一实施例,刻蚀工艺参数为:刻蚀腔体压力为10毫托,偏置功率325W,电源功率48W,BCl3流量为15SCCM,Cl2流量为30SCCM,C4F8流量为10SCCM,刻蚀粘附层250直至所述粘附层250高于第二金属层260。 [0046] As an example, an etching process parameters: an etching chamber pressure of 10 mTorr, 325W bias power, source power 48W, BCl3 flow rate of 15SCCM, Cl2 flow rate of 30 SCCM, a flow rate of 10 SCCM C4F8, etch the adhesive layer 250 until the adhesive layer 250 is higher than the second metal layer 260.

[0047] 参考图9,采用相变材料层270填满所述开口241。 [0047] Referring to FIG 9, a phase change material layer 270 fills the opening 241.

[0048] 所述相变材料层270选自锗锑碲合金相变材料,由之前刻蚀步骤可知,粘附层250高于第二金属层260,由于粘附层250比较薄且粘附层250粘附在开口的侧壁,第二金属层260和粘附层250之间不存在空隙,在填充相变材料层270时,相变材料层270较易完全填充所述开口241,不易形成填充空隙,从而形成的相变存储器单元性能较优。 [0048] The phase change material layer 270 is selected from GST alloy phase change material, seen from the previous etching step, the adhesion layer 250 is higher than the second metal layer 260, since the thin adhesive layer 250 and adhesive layer adhering sidewalls of the opening 250, there is no gap between the second metal layer 260 and an adhesive layer 250, the filling phase change material layer 270, phase change material layer 270 easier to completely fill the opening 241, not easy to form fill the void, the performance of phase change memory cells formed thereby is better.

[0049] 本发明提供一种相变存储器单元形成方法,形成粘附层高于第二金属层的相变存储器单元,从而不会粘附层与第二金属层的界面处形成空隙,避免相变材料在工作是填充进空隙导致的电阻变化不可控现象,提高相变存储器可靠性;进一步的,本发明采用优化的刻蚀工艺,避免粘附层刻蚀时速率较难控制,采用本发明提供的刻蚀工艺,能够形成高于第二金属层的粘附层。 [0049] The present invention provides a method of forming a phase change memory cell, forming an adherent metal layer on the second storey phase change memory cell, so that the adhesive layer at the interface without the second metal layer for forming a void, to avoid phase change the variable resistance material is filled into the working gap caused by uncontrollable phenomenon, improve the reliability of phase change memory; further, the present invention uses an optimized etching process, when the adhesive layer to avoid difficult to control etching rate, the present invention etching process provided the adhesive layer can be formed over the second metal layer.

[0050] 虽然本发明已以较佳实施例披露如上,但本发明并非限定于此。 [0050] While the present invention has been disclosed above with reference to preferred embodiments, but the present invention is not limited thereto. 任何本领域技术人员,在不脱离本发明的精神和范围内,均可作各种更动与修改,因此本发明的保护范围应当以权利要求所限定的范围为准。 Anyone skilled in the art, without departing from the spirit and scope of the present invention, various changes or modifications may be made, and therefore the scope of the present invention reference should be made to the scope defined by the claims.

Claims (9)

1. 一种相变存储器单元形成方法,其特征在于,包括:提供形成有第一金属层的半导体衬底,所述半导体衬底形成有覆盖第一金属层的第一层间介质层,所述第一层间介质层表面覆盖有阻挡层和第二层间介质层,形成在第二层间介质层、阻挡层和第一层间介质层内并暴露出第一金属层的开口;在所述开口的侧壁和底部形成粘附层;采用第二金属层填满所述开口;刻蚀开口内的第二金属层与阻挡层齐平;刻蚀粘附层并使得刻蚀后的粘附层高于刻蚀后的第二金属层;采用相变材料层填满所述开口。 1. A phase change memory cell forming method comprising: providing a semiconductor substrate having a first metal layer, the semiconductor substrate is formed with a first interlayer dielectric layer covering the first metal layer, the said surface of the first interlayer dielectric layer is covered with the barrier layer and the second interlayer dielectric layer formed on the second interlayer dielectric layer, an inner barrier layer and the first interlayer dielectric layer and exposing the openings of the first metal layer; in after such etching and etching the adhesion layer; forming the opening sidewall and a bottom adhesive layer; using a second metal layer fills said opening; a second metal layer and the etching barrier layer in an opening flush storey adhered to the second metal layer after etching; using phase change material layer fills the opening.
2.如权利要求1所述的相变存储器单元形成方法,其特征在于,所述粘附层高于第二金属层O纳米至50纳米。 2. The phase change memory cells formed according to claim 1, characterized in that said metal layer is adhered to the second storey O nm to 50 nm.
3.如权利要求1所述的相变存储器单元形成方法,其特征在于,所述粘附层的刻蚀工艺为采用Cl2与BCl3的混合气体和含碳量高的含氟气体作为刻蚀气体进行刻蚀,所述碳量高的含氟气体为C4F8、C5F8或者C4F6。 3. The phase change memory cells formed according to claim 1, characterized in that the adhesive layer is an etching process employing a mixed gas of high carbon content and the fluorine-containing gas of BCl3 and Cl2 as an etching gas etching, high-carbon content of the fluorine-containing gas is C4F8, C5F8 or C4F6.
4.如权利要求3所述的相变存储器单元形成方法,其特征在于,Cl2与BCl3的体积比为2 :1。 4. The phase change memory cells formed according to claim 3, characterized in that, Cl2 and BCl3 volume ratio of 2: 1.
5.如权利要求3所述的相变存储器单元形成方法,其特征在于,选用C4F8作为刻蚀气体,Cl2和BCl3的混合气体与C4F8的体积比为O. 8〜5。 5. A phase change memory according to claim 3 forming unit, characterized in that the selection of C4F8 as an etching gas, a mixed gas of BCl3 and Cl2, and the volume ratio of C4F8 O. 8~5.
6.如权利要求3所述的相变存储器单元形成方法,其特征在于,选用C4F6作为刻蚀气体,Cl2和BCl3的混合气体与C4F6的体积比为1.1〜10。 6. A phase change memory according to claim 3 forming unit, characterized in that the selection of C4F6 as an etching gas, and a volume ratio of a mixed gas of BCl3 and Cl2 C4F6 is 1.1~10.
7.如权利要求3所述的相变存储器单元形成方法,其特征在于,选用C5F8作为刻蚀气体,Cl2和BCl3的混合气体与C5F8的体积比为I〜10。 7. A phase change memory according to claim 3 forming unit, characterized in that the selection of C5F8 as an etching gas, a mixed gas of BCl3 and Cl2, and the volume ratio of C5F8 I~10.
8.如权利要求1所述的相变存储器单元形成方法,其特征在于,相变材料层为锗锑碲合金相变材料。 8. The phase change memory cells formed according to claim 1, characterized in that the phase change material layer is a GST alloy phase change material.
9.如权利要求1所述的相变存储器单元形成方法,其特征在于,阻挡层材料为氮化钛或者氮化钽。 9. The phase change memory cells formed according to claim 1, characterized in that the barrier layer material is titanium nitride or tantalum nitride.
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