CN103972383B - The Ovonics unified memory of diode selecting element arrays structure and manufacture method - Google Patents
The Ovonics unified memory of diode selecting element arrays structure and manufacture method Download PDFInfo
- Publication number
- CN103972383B CN103972383B CN201310040154.9A CN201310040154A CN103972383B CN 103972383 B CN103972383 B CN 103972383B CN 201310040154 A CN201310040154 A CN 201310040154A CN 103972383 B CN103972383 B CN 103972383B
- Authority
- CN
- China
- Prior art keywords
- layer
- unified memory
- type diffused
- ovonics unified
- diffused layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Memories (AREA)
Abstract
The Ovonics unified memory manufacture method of the open diode selecting element arrays structure of the present invention, on the basis of diode selecting element arrays structure, forms metal level on the tungsten plug of corresponding second p type diffused layer position and on the contact point electrode of N trap；Cushion, dielectric layer, low-temperature nitride and insulating barrier is sequentially formed on the insulating barrier of shallow isolation trench；It is positioned on the tungsten plug on n type diffused layer formation Ovonics unified memory material, Ovonics unified memory material is formed metal level, thus forms the Ovonics unified memory of diode selecting element arrays structure.This manufacturing approach craft is simple, requires relatively low to substrate surface, saves manufacturing cost；Formed the Ovonics unified memory of diode selecting element arrays structure by the method, cost is relatively low, and quality is preferable.
Description
Technical field
The present invention relates to technical field of semiconductors, refer in particular to the Ovonics unified memory of diode selecting element arrays structure
And manufacture method.
Background technology
Phase-change random access memory has high reading speed, low-power, high power capacity, high-reliability, height write wiping number of times, low work
The characteristic such as voltage/current and low cost, is suitable for being combined with CMOS technology, is used as the stand alone type of higher density or Embedded
Memory application.
Phase change random access memory devices include having phase change layer memory node, be connected to this memory node transistor and
PN junction diode with transistor.According to being applied to voltage thereon, phase change layer becomes non-crystalline from crystalline state, or and this
On the contrary.When the voltage applied is for arranging voltage, and phase change layer becomes crystalline state from non-crystalline.When the voltage applied is for resetting
Voltage, phase change layer becomes non-crystalline from crystalline transformation.
But, in prior art phase-change random access memory manufacturing process, PN junction diode is by epitaxial silicon or selective epitaxial
Silicon is formed, as it is shown in figure 1, the PN-junction diode structure 10 of prior art phase-change random access memory, at P-type semiconductor substrate 101
Interior injection N-type ion, forms buried N trap 102；Then, P-type semiconductor substrate 101 forms N-type epitaxy layer 103；In N-type
Epitaxial layer 103 surface doping p-type ion, forms p type diffused layer 104.
Prior art forms the PN junction diode in phase-change random access memory and uses epitaxial silicon or selective epitaxial silicon conduct
Material, manufacturing cost is expensive；Further, since the depositing temperature of epitaxial silicon or selective epitaxy silicon is high, substrate surface is required height, makes
Manufacture the complex process of PN junction diode, spend the time long；Meanwhile, PN junction diode uses in substrate surface stack manner shape
Becoming, there is material quality problem in it.
Phase-change random access memory (PRAM) is by applying different size of special burst, causing phase-change material regional area
Amorphous state and crystalline state is produced because of different temperatures.The superiority of phase transition storage reaches nanoscale in size can body to greatest extent
Existing.The preparation of nanoscale electronics is mainly by technologic restriction, such as exposure technique, lithographic technique etc..In prior art, receive
Meter level phase transition storage manufacturing process is complex process, cost intensive.Cannot be with convenient and succinct method prepares nanometer
The contact surface of level, thus improve the response speed of device, reduce power consumption.
Summary of the invention
It is an object of the invention to provide Ovonics unified memory and the manufacture method of diode selecting element arrays structure, should
Manufacturing approach craft is simple, requires relatively low to substrate surface, saves manufacturing cost；Diode selecting element battle array is formed by the method
The Ovonics unified memory of array structure, cost is relatively low, and quality is preferable.
For reaching above-mentioned purpose, the solution of the present invention is:
The Ovonics unified memory manufacture method of diode selecting element arrays structure, comprises the following steps:
Step one, on P-type semiconductor substrate, interval forms shallow isolation trench, forms idiosome post, wherein between shallow isolation trench
One of for P tie idiosome post, remaining for N knot idiosome post；
Step 2, fills up insulating barrier in shallow isolation trench；
Step 3, forms N trap on P-type semiconductor substrate；
Step 4, buries the first p type diffused layer on N trap upper strata；
Step 5, ties at the N being positioned at the first p type diffused layer upper strata and forms n type diffused layer on idiosome post, on n type diffused layer
Layer forms tungsten plug, and tungsten plug is connected formation diode the first pole with n type diffused layer；At the P being positioned at the first p type diffused layer upper strata
Extending on knot idiosome post and form the second p type diffused layer, the second p type diffused layer upper strata forms tungsten plug, tungsten plug and the second p-type and expands
Dissipate layer and connect formation diode the second pole；Upper strata, N trap side forms n type diffused layer, and n type diffused layer upper strata forms tungsten plug, tungsten
Connector is connected the contact point electrode forming N trap with n type diffused layer；
Step 6, is sequentially depositing cushion and dielectric layer on tungsten plug and insulating barrier, deposits one layer of light on dielectric layer
Resistance layer, and Ovonics unified memory region is opened in corresponding n type diffused layer position on photoresist layer；
Step 7, successively by dielectric layer and the etch buffer layer in Ovonics unified memory region, makes tungsten plug expose；
Step 8, deposits one layer of nitride, fills up Ovonics unified memory region and cover on dielectric layer；
Step 9, performs nitride etch, makes tungsten plug expose, and is formed " tiltedly in Ovonics unified memory region side walls simultaneously
Ramp shaped " side wall；
Step 10, deposits one layer of Ovonics unified memory material, fills up change memory area, contact with tungsten plug；
Step 11, grinds Ovonics unified memory material, makes Ovonics unified memory material flush with dielectric layer；In phase change
Deposit one layer of low-temperature nitride on storage material, and in low-temperature nitride, deposit a layer insulating；
Step 12, expands corresponding second p-type by the insulator layer etch of corresponding Ovonics unified memory positions of materials, meanwhile
Dissipate the insulator layer etch of layer position, make low-temperature nitride expose, form metal layer region；
Step 13, successively by low-temperature nitride and the dielectric layer etching of corresponding second p type diffused layer position, makes cushion
Expose, form metal level contact hole region；
Step 14, by the cushion of corresponding second p type diffused layer position and corresponding Ovonics unified memory positions of materials
Low-temperature nitride etches, and makes the tungsten plug of Ovonics unified memory material and corresponding second p type diffused layer position expose；
Step 15, deposits layer of metal layer, by the metal level contact hole region of corresponding second p type diffused layer position and right
The metal layer region answering Ovonics unified memory positions of materials is filled up.
Further, in step 3, use N trap mask, exposure, developing process that N well region is opened；With mode is ion implanted
N-type is ion implanted N well region, performs N trap and drive in formation N trap, make the idiosome post between shallow isolation trench be diluted to doped with P type
Diffusion layer or lightly doped n type diffusion layer.
Further, N-type ion is one or both of phosphonium ion or arsenic ion, and dosage is 1E12-1E14cm-2, energy divides
Wei 10Kev-200Kev or 200Kev-800Kev.
Further, in step 4, use bury, expose, developing process opens the first territory, p type diffusion region；Plant with ion
Enter mode and p-type is ion implanted territory, p type diffusion region, form the first p type diffused layer.
Further, p-type ion is boron ion, and dosage is 5E14-5E15 cm-2, energy is 25Kev-150Kev.
Further, after step 2, it is additionally included on P-type semiconductor substrate formation deep isolation trench step；Deep isolation trench
The degree of depth, more than the degree of depth of shallow isolation trench, fills up insulating barrier in deep isolation trench, and the height of insulating barrier is equal to the height of deep isolation trench；
Deep isolation trench is positioned at the contact point electrode side of N trap.
Further, in step 6, cushion is nitride, and dielectric layer is silicon dioxide, and the thickness of nitride is 50-200
, the thickness of silicon dioxide is 200-1000 (angstrom).
Further, in step 10, Ovonics unified memory material is a kind of Ge-Sb-Te chalkogenide, at Ovonics unified memory material
One layer of tantalum nitride or the protective layer of titanium nitride is formed bottom material.
Further, in step 11, low-temperature nitride thickness is 50-150, and temperature is 350-400；Insulating barrier is boron
Phosphorosilicate glass or boron-phosphorosilicate glass hydrochlorate or low temperature chemical vapor deposition silicon oxide, thickness is 500-3000.
Further, step 15 is additionally included in upper strata, N trap side and forms shape on the tungsten plug of n type diffused layer correspondence position
Become metal level step.
The Ovonics unified memory of diode selecting element arrays structure, on P-type semiconductor substrate, interval forms shallow isolation
Groove, fills up insulating barrier in shallow isolation trench, make to be formed between shallow isolation trench idiosome post, and one of them ties idiosome post for P, and remaining is N
Knot idiosome post；Form N trap in P-type semiconductor substrate center position, bury the first p type diffused layer on N trap upper strata；It is being positioned at first
Forming n type diffused layer on the N knot idiosome post on p type diffused layer upper strata, n type diffused layer upper strata forms tungsten plug, and tungsten plug expands with N-type
Dissipate layer and connect formation diode the first pole；Tie to extend on idiosome post at the P being positioned at the first p type diffused layer upper strata and form the second p-type
Diffusion layer, the second p type diffused layer upper strata forms tungsten plug, tungsten plug and the second p type diffused layer and connects formation diode the second pole；
Upper strata, N trap side forms n type diffused layer, and n type diffused layer upper strata forms tungsten plug, and tungsten plug is connected formation N trap with n type diffused layer
Contact point electrode；Metal level is formed on the tungsten plug of corresponding second p type diffused layer position and on the contact point electrode of N trap；Shallow
Cushion, dielectric layer, low-temperature nitride and insulating barrier is sequentially formed on the insulating barrier of isolation channel；It is positioned on n type diffused layer
Form Ovonics unified memory material on tungsten plug, Ovonics unified memory material is formed metal level.
Further, Ovonics unified memory material is in " horn mouth " shape.
Further, P-type semiconductor substrate also forms deep isolation trench；The degree of depth of deep isolation trench is deep more than shallow isolation trench
Degree, fills up insulating barrier in deep isolation trench, and the height of insulating barrier is equal to the height of deep isolation trench；Deep isolation trench is positioned at connecing of N trap
Contact electrode side.
Further, also forming logic circuit on P-type semiconductor substrate, logic circuit is positioned at deep isolation trench side.
After using such scheme, the present invention is spaced formation shallow isolation trench, shape between shallow isolation trench on P-type semiconductor substrate
Becoming idiosome post, one of them ties idiosome post for P, and remaining ties idiosome post for N so that the P knot of diode of the present invention is formed at p-type half
On conductor substrate, meanwhile, the N junction array of diode is also formed on P-type semiconductor substrate, due to the product of P-type semiconductor substrate
Matter purity is high, and therefore, diode quality of the present invention is preferable, the phase change storage of diode selecting element arrays structure the most of the present invention
Device quality is preferable, and cost is relatively low.
And, Ovonics unified memory material is in " horn mouth " shape, and tapering width from top to bottom, reduction phase change stores
Equipment material and the contact area of tungsten plug, being of value to reduction phase change memory cell setting and replacement when electrically operation needs use
Electric current.
Meanwhile, the Ovonics unified memory technique of diode selecting element arrays structure of the present invention is simple, substrate surface
Ask relatively low, save manufacturing cost.
Accompanying drawing explanation
Fig. 1 is prior art PN-junction diode structure schematic diagram；
Fig. 2 is that the present invention forms shallow isolation trench schematic diagram on P-type semiconductor substrate；
Fig. 3 is that the present invention forms deep isolation trench schematic diagram on P-type semiconductor substrate；
Fig. 4 is that the present invention forms N trap schematic diagram on P-type semiconductor substrate；
Fig. 5 is that the present invention buries the first p type diffused layer schematic diagram on P-type semiconductor substrate；
Fig. 6 is diode selecting element arrays structural representation of the present invention；
Fig. 7 is that the present invention forms cushion, dielectric layer and photoresist layer structure in diode selecting element arrays structure and shows
It is intended to；
Fig. 8 is that the present invention forms Ovonics unified memory area schematic；
Fig. 9 is present invention cvd nitride thing schematic diagram on Ovonics unified memory region；
Figure 10 is that the present invention forms side wall schematic diagram in Ovonics unified memory region；
Figure 11 is that sedimentary facies of the present invention changes storage material schematic diagram；
Figure 12 is that the present invention sequentially forms low-temperature nitride and insulating barrier schematic diagram；
Figure 13 to Figure 15 is that the present invention forms metal layer region schematic diagram；
Figure 16 is that the present invention forms metal level schematic diagram；
Figure 17 is pcram structure schematic diagram of the present invention.
Label declaration
PN-junction diode structure 10
P-type semiconductor substrate 101 N trap 102
N-type epitaxy layer 103 p type diffused layer 104
P-type semiconductor substrate 1 shallow isolation trench 11
Idiosome post 12 deep isolation trench 13
N trap 14 first p type diffused layer 15
Logic gate 16 n type diffused layer 17
Tungsten plug 18 second p type diffused layer 19
Logic circuit 2 cushion 3
Dielectric layer 4 nitride 41
Side wall 42 photoresist layer 5
Ovonics unified memory region 51 Ovonics unified memory material 6
Low-temperature nitride 7 metal layer region 71
Metal level contact hole region 72 metal level 73
Insulating barrier 8.
Detailed description of the invention
Below in conjunction with drawings and the specific embodiments, the present invention is elaborated.
Refering to shown in Fig. 2 to Figure 16, a kind of diode selecting element arrays structure making process that the present invention discloses, including
Following steps:
As shown in Figure 2, it is provided that P-type semiconductor substrate 1, on P-type semiconductor substrate 1, interval forms shallow isolation trench 11, its
Perform step and be included on P-type semiconductor substrate 1 formation silicon oxide layer or silicon nitride layer, perform lithography step and comprise employing isolation
Mask, expose, shallow isolation trench 11 region is opened in development etc., uses anisotropic dry etch mode to perform silicon etching to be formed
Isolation channel 11.Shallow isolation trench 11 be formed as standard processing procedure, do not describe in detail.Idiosome post 12 is formed between shallow isolation trench 11, its
One of for P tie idiosome post, remaining for N knot idiosome post.
As it is shown on figure 3, form deep isolation trench 13 in the structure of Fig. 2, the degree of depth of deep isolation trench 13 is more than shallow isolation trench 11
The degree of depth；Diode selecting element arrays structure is preferably isolated with other circuit.Perform lithography step comprise employing deeply every
From groove 13 mask, expose, deep isolation trench 13 region is opened in development etc., uses anisotropic dry etch mode to perform silicon etching
To form deep isolation trench 13.Deep isolation trench 13 be formed as standard processing procedure, do not describe in detail.
In the structure of Fig. 3, form silicon oxide layer by thermally grown and chemical vapor deposition mode, the thickness of this silicon oxide layer
Exceed the degree of depth of deep isolation trench 13, deep isolation trench 13 and shallow isolation trench 11 are filled up；Perform chemical mechanical milling method silicon oxide
Layer grinds the remaining silicon oxide of relief and just fills up deep isolation trench 13 and shallow isolation trench 11.
As shown in Figure 4, on the architecture basics of Fig. 3, P-type semiconductor substrate 1 forms N trap 14.Perform lithography step
Comprise employing N trap mask, expose, N trap 14 region is opened in development etc.；With the mode that is ion implanted N-type ion such as phosphonium ion and
Arsenic ions etc. implant N trap 14 region, and this N-type ion can comprise one or several ions, and dosage is 1E12 cm-2-1E14 cm-2, energy is respectively the N-type ion that 10Kev-200Kev or 200Kev-800Kev, N trap uses generally 2-4 kind, and energy is big
It is deep that ion is beaten, and its energy is between 200Kev-800Kev；The ratio that the ion that energy is little is beaten is shallower, and its energy exists
Between 10Kev-200Kev.Perform N trap to drive in formation N trap 14, make the idiosome post 12 between shallow isolation trench 11 be diluted to doped with P
Type diffusion layer or lightly doped n type diffusion layer.
As it is shown in figure 5, on the architecture basics of Fig. 4, bury the first p type diffused layer 15 on N trap 14 upper strata.Execution photoetching walks
Suddenly comprise employing p-type diffusion mask, expose, development etc. is opened burying the first p type diffused layer 15 region；With mode is ion implanted
P-type ion such as boron is ion implanted the first p type diffused layer 15 region, and this p-type ion dose is 5E14 cm-2-5E15 cm-2, energy
Amount is 25Kev-150Kev.This is buried the first p type diffused layer 15 and forms buried word line (the Buried Word of memory element
Line)。
As shown in Figure 6, in the structure of Fig. 5, form diode selecting element arrays.Perform step and comprise formation polysilicon
Gridistor is such as grown up gate oxidation, forms polysilicon layer or amorphous silicon layer by chemical vapour deposition mode, uses logic gate to cover
Mould, expose, logic gate 16 region is opened in development etc., uses anisotropic dry etch mode to perform polysilicon etch or non-crystalline silicon
Etching is to form logic gate 16.
Tie at the N being positioned at the first p type diffused layer 15 upper strata and on idiosome post, form n type diffused layer 17, n type diffused layer 17 upper strata
Forming tungsten plug 18, tungsten plug 18 is connected formation diode the first pole with n type diffused layer 17；Upper strata, N trap 14 side also forms N-type
Diffusion layer 17, n type diffused layer 17 upper strata forms tungsten plug 18, and tungsten plug 18 is connected the contact forming N trap 14 with n type diffused layer 17
Point electrode.Formed n type diffused layer 17 comprise employing N-type diffusion mask, expose, n type diffused layer 17 region is opened in development etc.,
By the mode that is ion implanted the N-type ion such as implanted with n-type such as phosphonium ion, arsenic ion diffusion layer 17 region, this N-type ion dose is
1E13 cm-2-5E15 cm-2, energy is 10Kev-100Kev.
Tie to extend on idiosome post at the P being positioned at the first p type diffused layer 15 upper strata and form the second p type diffused layer 19, the second p-type
Diffusion layer 19 upper strata forms tungsten plug 18, and tungsten plug 18 is connected formation diode the second pole with the second p type diffused layer 19.Form the
Two p type diffused layers 19 comprise employing p-type diffusion mask, expose, the second p type diffused layer 19 region is opened in development etc., uses ion
Implantation is ion implanted the second p type diffused layer 19 region p-type ion such as boron, and this p-type ion dose is 1E13 cm-2-5E15
cm-2, energy is 10Kev-100Kev.
Formed tungsten plug 18 comprise employing contact hole mask, expose, contact hole region is opened in development etc., execution metal
Titanium deposit, titanium nitride deposit and tungsten deposit, perform chemical mechanical milling method and the tungsten grinding remaining tungsten of relief just filled up contact
Window is the most contour with the end face of the isolated insulation layer of periphery, i.e. contour with the end face of shallow isolation trench 11 and deep isolation trench 13.
As it is shown in fig. 7, be sequentially depositing buffering on insulating barrier in tungsten plug 18 and shallow isolation trench 11 and deep isolation trench 13
Layer 3 and dielectric layer 4, cushion 3 is buffering nitride, and dielectric layer 4 is silicon dioxide, and the thickness of nitride is 50-200, and
The thickness of silicon dioxide is 200-1000 (angstrom)；Dielectric layer 4 deposits one layer of photoresist layer (Photo Resist) 5, performs
Lithography step comprise employing Ovonics unified memory mask, expose, development etc. is n type diffused layer 17 position corresponding on photoresist layer 5
Open Ovonics unified memory region 51.
As shown in Figure 8, anisotropic dry etch mode is used to perform SiO 2 etch and nitride etch, until phase transformation
The tungsten plug 18 changed in memory area 51 comes out.
As it is shown in figure 9, one layer of nitride 41 of deposition, fill up Ovonics unified memory region 51 and cover on dielectric layer 4.
As shown in Figure 10, anisotropic dry etch mode is used to perform nitride etch, until Ovonics unified memory region
Tungsten plug 18 in 51 comes out, and remains the most etched nitride along silicon dioxide (dielectric layer 4) and buffering nitride
The sidewall of (cushion 3) forms nitride side wall, i.e. forms " ramped shaped " side wall 42 at Ovonics unified memory region 51 sidewall；
This nitride side wall 42 makes the tungsten plug 18 in Ovonics unified memory region 51 and the phase being attached thereto described later
The area that change storage material contacts reduces, and is of value to reduction phase change memory cell and arranges and weight when electrically operation
Put need to electric current.
As shown in figure 11, deposit one layer of Ovonics unified memory material 6, fill up silicon dioxide (dielectric layer 4) and buffering nitridation
Ovonics unified memory region 51 between thing (cushion 3) stacking block, and cover in silicon dioxide and buffering nitride stacking
On block, Ovonics unified memory material 6 contacts with tungsten plug 18；Wherein, Ovonics unified memory material 6 is a kind of chalkogenide thing
Matter, such as Ge-Sb-Te.One layer of tantalum nitride or the protective layer of titanium nitride can be formed bottom Ovonics unified memory material 6.
As shown in figure 12, chemical mechanical milling method (CMP) is performed (slow to silicon dioxide (dielectric layer 4) and buffering nitride
Rush layer 3) stacking block on Ovonics unified memory material 6 grind off completely, and allow adjacent silicon dioxide and buffering nitride stacking
Between block, Ovonics unified memory material 6 is filled up in interval, space, and its end face and adjacent silicon dioxide and buffering nitride stacks
End face between block flushes.Depositing one layer of low-temperature nitride 7 on Ovonics unified memory material 6, its thickness is 50-150, temperature
Degree is 350-400；And in low-temperature nitride 7, deposit a layer insulating 8；Boron-phosphorosilicate glass or boron-phosphorosilicate glass hydrochlorate or low
Temperature chemical gaseous phase cvd silicon oxide, thickness is 500-3000.
As shown in figure 13, use anisotropic dry etch mode by the insulating barrier 8 of corresponding Ovonics unified memory material 6 position
Etching, etches the insulating barrier 8 of corresponding second p type diffused layer 19 position meanwhile, until low-temperature nitride 7 comes out；Use
Metal layer mask, expose, metal layer region 71 is opened in development etc..
As shown in figure 14, use anisotropic dry etch mode successively by the low temperature of corresponding second p type diffused layer 19 position
Nitride 7 and dielectric layer 4 etch, until cushion 3 exposes, use metal layer mask, expose, non-phase change is deposited in development etc.
Memory element metal level contact hole region 72 is opened.
As shown in figure 15, use anisotropic dry etch mode by the cushion 3 of corresponding second p type diffused layer 19 position and
The low-temperature nitride etching 7 of corresponding Ovonics unified memory material 6 position, makes Ovonics unified memory material 6 and corresponding second p-type expand
The tungsten plug 18 dissipating layer 19 position comes out.
As shown in figure 16, layer of metal layer 73 is deposited, by the metal level contact hole district of corresponding second p type diffused layer 19 position
The metal layer region 71 of territory 72 and corresponding Ovonics unified memory material 6 position is filled up.Perform chemical mechanical milling method metal level
73 grind the remaining metal level of relief 73 just fills up metal level contact hole region 72 and metal layer region 71, and insulant
Metal level 73 in district 8 grinds off completely.Meanwhile, as shown in figure 17, the corresponding position of n type diffused layer 17 is formed on upper strata, N trap 14 side
Also metal level 73 is formed on the tungsten plug 18 put.
As shown in figure 17, the phase change storage of the diode selecting element arrays structure formed based on above-mentioned manufacture method
Device, on P-type semiconductor substrate 1, interval forms shallow isolation trench 11, fills up insulating barrier in shallow isolation trench 11, and insulating barrier is oxidation
Silicon, makes to be formed between shallow isolation trench 11 idiosome post 12, and one of them ties idiosome post for P, and remaining ties idiosome post for N.
Form N trap 14 in P-type semiconductor substrate 1 center, bury the first p type diffused layer 15 on N trap 14 upper strata；In place
Forming n type diffused layer 17 on N knot idiosome post in the first p type diffused layer 15 upper strata, n type diffused layer 17 upper strata forms tungsten plug
18, tungsten plug 18 is connected formation diode the first pole with n type diffused layer 17.
Tie to extend on idiosome post at the P being positioned at the first p type diffused layer 15 upper strata and form the second p type diffused layer 19, the second p-type
Diffusion layer 19 upper strata forms tungsten plug 18, and tungsten plug 18 is connected formation diode the second pole with the second p type diffused layer 19.
Upper strata, N trap 14 side forms n type diffused layer 17, and n type diffused layer 17 upper strata forms tungsten plug 18, tungsten plug 18 and N
Type diffusion layer 17 connects the contact point electrode forming N trap 14.
Metal level 73 is formed on the tungsten plug 18 of corresponding second p type diffused layer 19 position and on the contact point electrode of N trap 14；
Cushion 3, dielectric layer 4, low-temperature nitride 7 and insulating barrier 8 is sequentially formed on the insulating barrier of shallow isolation trench 11；It is positioned at N-type diffusion
Form Ovonics unified memory material 6 on tungsten plug 18 on layer 17, Ovonics unified memory material 6 is formed metal level 73.Phase
Change storage material 6 is in " horn mouth " shape, and tapering width from top to bottom, reduces Ovonics unified memory material 6 and tungsten is inserted
The contact area of plug 18, be of value to reduce phase change memory cell arrange when electrically operation and reset need to electric current.
The Ovonics unified memory of diode selecting element arrays structure of the present invention, is also formed deep on P-type semiconductor substrate 1
Isolation channel 13；The degree of depth of deep isolation trench 13, more than the degree of depth of shallow isolation trench 11, fills up insulating barrier, insulating barrier in deep isolation trench 13
For silicon oxide layer, the height of insulating barrier is equal to deep isolation, the height of 13；Deep isolation trench 13 is positioned at the contact point electrode one of N trap 14
Side.
The Ovonics unified memory of diode selecting element arrays structure of the present invention, is also formed on P-type semiconductor substrate 1 and patrols
Collecting circuit 2, logic circuit 2 is positioned at deep isolation trench 13 side.Diode circuit is separated by deep isolation trench 13 with logic circuit 2.Patrol
Collecting circuit 2 concrete structure is custom circuit, and its manufacture method is conventional processing procedure, does not describes in detail.
The foregoing is only presently preferred embodiments of the present invention, not the restriction to this case design, all designs according to this case are closed
The equivalent variations that key is done, each falls within the protection domain of this case.
Claims (14)
1. the Ovonics unified memory manufacture method of diode selecting element arrays structure, it is characterised in that: comprise the following steps:
Step one, on P-type semiconductor substrate, interval forms shallow isolation trench, forms idiosome post between shallow isolation trench, one of them
Tying idiosome post for P, remaining ties idiosome post for N；
Step 2, fills up insulating barrier in shallow isolation trench；
Step 3, forms N trap on P-type semiconductor substrate；
Step 4, buries the first p type diffused layer on N trap upper strata；
Step 5, ties at the N being positioned at the first p type diffused layer upper strata and forms n type diffused layer, n type diffused layer upper strata shape on idiosome post
Becoming tungsten plug, tungsten plug is connected formation diode the first pole with n type diffused layer；Embryo is tied at the P being positioned at the first p type diffused layer upper strata
Extending on scapus and form the second p type diffused layer, the second p type diffused layer upper strata forms tungsten plug, tungsten plug and the second p type diffused layer
Connect and form diode the second pole；Upper strata, N trap side forms n type diffused layer, and n type diffused layer upper strata forms tungsten plug, tungsten plug
The contact point electrode forming N trap it is connected with n type diffused layer；
Step 6, is sequentially depositing cushion and dielectric layer on tungsten plug and insulating barrier, deposits one layer of photoresist layer on dielectric layer,
And Ovonics unified memory region is opened in corresponding n type diffused layer position on photoresist layer；
Step 7, successively by dielectric layer and the etch buffer layer in Ovonics unified memory region, makes tungsten plug expose；
Step 8, deposits one layer of nitride, fills up Ovonics unified memory region and cover on dielectric layer；
Step 9, performs nitride etch, makes tungsten plug expose, and forms " ramped shaped " in Ovonics unified memory region side walls simultaneously
Side wall；
Step 10, deposits one layer of Ovonics unified memory material, fills up change memory area, contact with tungsten plug；
Step 11, grinds Ovonics unified memory material, makes Ovonics unified memory material flush with dielectric layer；Store in phase change
One layer of low-temperature nitride of device deposited on materials, and in low-temperature nitride, deposit a layer insulating；
Step 12, by the insulator layer etch of corresponding Ovonics unified memory positions of materials, meanwhile, by corresponding second p type diffused layer
The insulator layer etch of position, makes low-temperature nitride expose, and forms metal layer region；
Step 13, successively by low-temperature nitride and the dielectric layer etching of corresponding second p type diffused layer position, makes cushion sudden and violent
Dew, forms metal level contact hole region；
Step 14, by cushion and the low temperature of corresponding Ovonics unified memory positions of materials of corresponding second p type diffused layer position
Nitride etch, makes the tungsten plug of Ovonics unified memory material and corresponding second p type diffused layer position expose；
Step 15, deposits layer of metal layer, by metal level contact hole region and the corresponding phase of corresponding second p type diffused layer position
The metal layer region of change storage material position is filled up.
2. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: in step 3, use N trap mask, exposure, developing process that N well region is opened；With mode is ion implanted, N-type ion is planted
Enter N well region, perform N trap and drive in formation N trap, make the idiosome post between shallow isolation trench be diluted to doped with P type diffusion layer or light
Doped N-type diffusion layer.
3. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 2, its feature exists
In: N-type ion is one or both of phosphonium ion or arsenic ion, and dosage is 1E12-1E14cm-2, energy is respectively 10Kev-
200Kev or 200Kev-800Kev.
4. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: in step 4, use bury, expose, developing process opens the first territory, p type diffusion region；Be ion implanted mode p-type from
Son implants territory, p type diffusion region, forms the first p type diffused layer.
5. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 4, its feature exists
In: p-type ion is boron ion, and dosage is 5E14-5E15 cm-2, energy is 25Kev-150Kev.
6. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: after step 2, it is additionally included on P-type semiconductor substrate formation deep isolation trench step；The degree of depth of deep isolation trench more than shallow every
From the degree of depth of groove, filling up insulating barrier in deep isolation trench, the height of insulating barrier is equal to the height of deep isolation trench；Deep isolation trench is positioned at
The contact point electrode side of N trap.
7. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: in step 6, cushion is nitride, and dielectric layer is silicon dioxide, and the thickness of nitride is 50-200, silicon dioxide
Thickness is 200-1000.
8. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: in step 10, Ovonics unified memory material is a kind of Ge-Sb-Te chalkogenide, forms one bottom Ovonics unified memory material
Layer tantalum nitride or the protective layer of titanium nitride.
9. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: in step 11, low-temperature nitride thickness is 50-150, and temperature is 350 DEG C-400 DEG C；Insulating barrier be boron-phosphorosilicate glass or
Low temperature chemical vapor deposition silicon oxide, thickness is 500-3000.
10. the Ovonics unified memory manufacture method of diode selecting element arrays structure as claimed in claim 1, its feature exists
In: step 15 is additionally included in upper strata, N trap side and forms formation metal level step on the tungsten plug of n type diffused layer correspondence position
Suddenly.
The Ovonics unified memory of 11. diode selecting element arrays structures, it is characterised in that: it is spaced on P-type semiconductor substrate
Forming shallow isolation trench, fill up insulating barrier in shallow isolation trench, make to be formed between shallow isolation trench idiosome post, one of them ties idiosome for P
Post, remaining ties idiosome post for N；Form N trap in P-type semiconductor substrate center position, bury the first p type diffused layer on N trap upper strata；
Tying at the N being positioned at the first p type diffused layer upper strata and form n type diffused layer on idiosome post, n type diffused layer upper strata forms tungsten plug, tungsten
Connector is connected formation diode the first pole with n type diffused layer；Tie at the P being positioned at the first p type diffused layer upper strata and extend on idiosome post
Forming the second p type diffused layer, the second p type diffused layer upper strata forms tungsten plug, tungsten plug and the second p type diffused layer and connects formation two
Pole pipe the second pole；Upper strata, N trap side forms n type diffused layer, and n type diffused layer upper strata forms tungsten plug, tungsten plug and n type diffused layer
Connect the contact point electrode forming N trap；Shape on the tungsten plug of corresponding second p type diffused layer position and on the contact point electrode of N trap
Become metal level；Cushion, dielectric layer, low-temperature nitride and insulating barrier is sequentially formed on the insulating barrier of shallow isolation trench；It is positioned at N-type to expand
Dissipate and on the tungsten plug on layer, form Ovonics unified memory material, Ovonics unified memory material is formed metal level.
The Ovonics unified memory of 12. diode selecting element arrays structures as claimed in claim 11, it is characterised in that: phase transformation
Change storage material in " horn mouth " shape.
The Ovonics unified memory of 13. diode selecting element arrays structures as claimed in claim 11, it is characterised in that: at P
Deep isolation trench is also formed in type Semiconductor substrate；The degree of depth of deep isolation trench, more than the degree of depth of shallow isolation trench, is filled out in deep isolation trench
Full insulating barrier, the height of insulating barrier is equal to the height of deep isolation trench；Deep isolation trench is positioned at the contact point electrode side of N trap.
The Ovonics unified memory of 14. diode selecting element arrays structures as claimed in claim 11, it is characterised in that: at P
Also forming logic circuit in type Semiconductor substrate, logic circuit is positioned at deep isolation trench side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310040154.9A CN103972383B (en) | 2013-02-01 | 2013-02-01 | The Ovonics unified memory of diode selecting element arrays structure and manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310040154.9A CN103972383B (en) | 2013-02-01 | 2013-02-01 | The Ovonics unified memory of diode selecting element arrays structure and manufacture method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103972383A CN103972383A (en) | 2014-08-06 |
| CN103972383B true CN103972383B (en) | 2016-10-05 |
Family
ID=51241658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310040154.9A Expired - Fee Related CN103972383B (en) | 2013-02-01 | 2013-02-01 | The Ovonics unified memory of diode selecting element arrays structure and manufacture method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103972383B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604728A (en) * | 2008-06-13 | 2009-12-16 | 财团法人工业技术研究院 | Phase-change memorizer device and manufacture method thereof |
| CN102024839A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory, isolation structure for memory unit and manufacturing method thereof |
| CN102237492A (en) * | 2010-04-29 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Formation method for phase-change memory unit |
| CN102412179A (en) * | 2010-09-21 | 2012-04-11 | 中国科学院上海微系统与信息技术研究所 | Preparation method for epitaxial diode array isolated by double shallow trenches |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100052300A (en) * | 2008-11-10 | 2010-05-19 | 주식회사 하이닉스반도체 | Phase change memory device and method for manufacturing the same |
| JP2012222114A (en) * | 2011-04-07 | 2012-11-12 | Elpida Memory Inc | Semiconductor device and manufacturing method of the same |
-
2013
- 2013-02-01 CN CN201310040154.9A patent/CN103972383B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604728A (en) * | 2008-06-13 | 2009-12-16 | 财团法人工业技术研究院 | Phase-change memorizer device and manufacture method thereof |
| CN102024839A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Phase change memory, isolation structure for memory unit and manufacturing method thereof |
| CN102237492A (en) * | 2010-04-29 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Formation method for phase-change memory unit |
| CN102412179A (en) * | 2010-09-21 | 2012-04-11 | 中国科学院上海微系统与信息技术研究所 | Preparation method for epitaxial diode array isolated by double shallow trenches |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103972383A (en) | 2014-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9941299B1 (en) | Three-dimensional ferroelectric memory device and method of making thereof | |
| CN110785851B (en) | Three-dimensional memory device employing direct source contact and hole current detection and method of fabricating the same | |
| US9728551B1 (en) | Multi-tier replacement memory stack structure integration scheme | |
| EP3642877B1 (en) | Three-dimensional memory device having discrete direct source strap contacts and method of making thereof | |
| US10242994B2 (en) | Three-dimensional memory device containing annular etch-stop spacer and method of making thereof | |
| CN107996000B (en) | Epitaxial source regions for uniform threshold voltage of vertical transistors in 3D memory devices | |
| US9805805B1 (en) | Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof | |
| US9991277B1 (en) | Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof | |
| US10991721B2 (en) | Three-dimensional memory device including liner free molybdenum word lines and methods of making the same | |
| US9666281B2 (en) | Three-dimensional P-I-N memory device and method reading thereof using hole current detection | |
| US11631691B2 (en) | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | |
| CN104022121B (en) | Three-dimensional semiconductor device and manufacturing method thereof | |
| EP3707749A1 (en) | Three-dimensional memory device with annular blocking dielectrics and method of making thereof | |
| CN110088905A (en) | Bulb-shaped memory heap stack structure for source contact direct in three dimensional memory device | |
| CN106847854B (en) | Highly integrated semiconductor memory device and its manufacturing method | |
| US20160329343A1 (en) | Three dimensional memory device with hybrid source electrode for wafer warpage reduction | |
| US20200194668A1 (en) | Interfacial resistive memory gate stack transistor cell and methods of manufacturing the same | |
| CN114334969A (en) | Semiconductor structure and manufacturing method thereof | |
| CN103972383B (en) | The Ovonics unified memory of diode selecting element arrays structure and manufacture method | |
| CN103972384B (en) | Ovonics unified memory material transition region manufacture method and Ovonics unified memory | |
| CN103151458B (en) | Embedded phase change memory array and manufacturing method | |
| CN103151366B (en) | A kind of phase change holder array and manufacture method | |
| CN103972172B (en) | A kind of diode selecting element arrays structure and manufacture method | |
| CN103839892B (en) | A kind of semiconductor structure and manufacture method thereof | |
| CN103972385B (en) | A kind of embedded phase change memory and its manufacture method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190424 Address after: Miaoli City, Miaoli County, Taiwan, China, is adjacent to No. 25 Linsen Street, No. 6 Shuiyuan Li, Miaoli City, Taiwan Patentee after: Chen Qiufeng Address before: Room 205, Unit 201, 39 Wanhai Road, No. 2, Xiamen Software Park, Fujian Province, 361000 Patentee before: Xiamen Bojiaqin Electronic Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20161005 Termination date: 20200201 |