CN104979468A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
CN104979468A
CN104979468A CN201410143549.6A CN201410143549A CN104979468A CN 104979468 A CN104979468 A CN 104979468A CN 201410143549 A CN201410143549 A CN 201410143549A CN 104979468 A CN104979468 A CN 104979468A
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CN
China
Prior art keywords
described
tube
carbon nano
hole
bottom electrode
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CN201410143549.6A
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Chinese (zh)
Inventor
张城龙
王冬江
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中芯国际集成电路制造(上海)有限公司
中芯国际集成电路制造(北京)有限公司
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Priority to CN201410143549.6A priority Critical patent/CN104979468A/en
Publication of CN104979468A publication Critical patent/CN104979468A/en

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate, and forming a first metal electrode in the interlayer dielectric layer; forming a through hole for filling a bottom electrode in the interlayer dielectric layer, wherein the through hole exposes a part of upper surface of the first metal electrode; and forming a carbon nano-tube for fully filling the through hole, wherein the carbon nano-tube serves as the bottom electrode. According to the semiconductor device and the manufacturing method thereof, under the condition that a deposition process window reaches critical limit, the formed carbon nano-tube can meet the requirement of expected performance index of the bottom electrode, thereby improving the qualified rate of the device.

Description

A kind of semiconductor device and manufacture method thereof

Technical field

The present invention relates to semiconductor fabrication process, in particular to a kind of manufacture method and the phase change random access memory devices with the bottom electrode adopting the method to make of the bottom electrode for phase change random access memory devices.

Background technology

Phase transition storage (PCM) is a kind of memory with high read/write speed, and it is widely used in integrated circuit.The committed step of integrated phase transition storage forms the bottom electrode (Bottom Electrode) for being communicated with metal electrode and phase-change material layers, and bottom electrode is from the bottom contact phase-change material layers of phase-change material (GST) layer.When the electric current of some strength is through bottom electrode, bottom electrode produces Joule heat to change the transition of phase-change material layers, thus control the operating state of phase transition storage, namely phase-change material layers by amorphous state to the function of write data realizing phase transition storage during crystalline state, phase-change material layers by crystalline state to the function of sense data realizing phase transition storage during amorphous state.

In order to reduce the driving power consumption of phase change random access memory devices, the contact area of bottom electrode and phase-change material layers should be reduced.Therefore, prior art is used as bottom electrode by forming the electrode with little lateral dimension, and when a weak current is through bottom electrode, bottom electrode just can produce enough large Joule heat.

Existing technique is adopted to make the processing step of above-mentioned bottom electrode as follows: first, as shown in Figure 1A, be formed with its lower end of metal electrode 102(wherein and be communicated with the circuit element (comprising switching device) be formed in Semiconductor substrate) interlayer dielectric layer 101 on successively deposition form hard mask stack structure and there is the photoresist layer 106 of top pattern 107 of metal electrode 102, described hard mask stack structure comprises stacked resilient coating 103 from bottom to top, first hard mask layer 104 and the second hard mask layer 105, resilient coating 103, the constituent material of the first hard mask layer 104 and the second hard mask layer 105 can be respectively the oxide that using plasma strengthens chemical vapor deposition method formation, silicon oxynitride and using plasma strengthen the oxide that chemical vapor deposition method is formed, then, as shown in Figure 1B, with photoresist layer 106 for mask, be etched in the first hard mask layer 104 and the second hard mask layer 105 form the first through hole 107 ' by implementing first, expose resilient coating 103, then remove photoresist layer 106 by cineration technics, then, as shown in Figure 1 C, in hard mask stack structure, deposition forms spacer material layer 108, covers sidewall and the bottom of the first through hole 107 ', then, as shown in figure ip, implement the second etching etched side walling bed of material 108, while exposing resilient coating 103, make the spacer material layer 108 of the sidewall of covering first through hole 107 ' be configured for the pattern 109 of second through hole of filling bottom electrode, then, as referring to figure 1e, with the spacer material layer 108 through described second etching for mask, implementing the 3rd etching etch buffer layers 103, while exposing metal electrode 102, forming the second through hole 109 ' for filling bottom electrode, then, as shown in fig. 1f, deposited bottom electrode material layer 110, to fill the second through hole 109 ' completely, then performs cmp until expose the second hard mask layer 105 and spacer material layer 108, then, as shown in Figure 1 G, etch-back bottom electrode material layer 110, completes the making of described bottom electrode.Next, the stacked phase-change material layers being communicated with bottom electrode material layer 110 and another metal electrode is formed from bottom to top.

In above-mentioned technical process, usually select tungsten as the constituent material of bottom electrode material layer 110, this is because the bottom electrode that tungsten is formed has the yield of the realization write data function more than 99%.But, along with the continuous reduction of semiconductor fabrication process node, the opening size of the second through hole 109 ' also constantly reduces thereupon, result through depositing operation filling tungsten and reach critical limit in the process window of the second through hole 109 ', and then cause the performance index of the bottom electrode of formation not reach the requirement of expection, cause the decline of yield of devices.

Therefore, need to propose a kind of method, to solve the problem.

Summary of the invention

For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, be formed with interlayer dielectric layer on the semiconductor substrate, in described interlayer dielectric layer, be formed with the first metal electrode; The through hole for filling bottom electrode is formed, the upper surface of the first metal electrode described in described through hole exposed portion in described interlayer dielectric layer; Form the carbon nano-tube of filling described through hole completely, described carbon nano-tube is as described bottom electrode.

Further, adopt chemical vapor deposition method to form described carbon nano-tube, depositing temperature is lower than 400 DEG C.

Further, before implementing described depositing operation, at sidewall and the bottom formation cobalt-base catalyst of described through hole.

Further, after implementing described depositing operation, the height of the described carbon nano-tube of formation is higher than the degree of depth of described through hole.

Further, after implementing described depositing operation, also comprise the step performing cmp, after implementing described grinding, the height of described carbon nano-tube equals the degree of depth of described through hole.

Further, before implementing described grinding, also comprise sacrificial material layer to cover the step of described carbon nano-tube; After implementing described grinding, described sacrificial material layer is completely removed.

Further, after implementing described grinding, also comprise the step forming phase-change material layers and the second metal electrode successively, phase-change material layers described in the upper-end contact making the bottom electrode be made up of described carbon nano-tube.

Further, described semiconductor device is phase transition storage, and the lower end of described first metal electrode is communicated with the electronic component be formed in described Semiconductor substrate, and the upper end of described first metal electrode is communicated with the lower end of described bottom electrode.

The present invention also provides a kind of semiconductor device adopting the either method in above-mentioned manufacture method to be formed, and the bottom electrode in described semiconductor device is made up of carbon nano-tube.

According to the present invention, when depositing operation window reaches critical limit, the carbon nano-tube of formation can meet the requirement of the estimated performance index for bottom electrode, thus the yield of boost device.

Accompanying drawing explanation

Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.

In accompanying drawing:

The schematic cross sectional view of device of Figure 1A-Fig. 1 G for making the step implemented successively for the bottom electrode of phase change random access memory devices according to prior art and obtaining respectively;

The schematic cross sectional view of the device that Fig. 2 A-Fig. 2 H obtains respectively for method is implemented successively according to an exemplary embodiment of the present invention step;

Fig. 3 is the flow chart of step implemented successively of method according to an exemplary embodiment of the present invention.

Embodiment

In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.

In order to thoroughly understand the present invention, by in following description, detailed step is proposed, to explain the manufacture method of the bottom electrode for phase change random access memory devices that the present invention proposes and there is the phase change random access memory devices of the bottom electrode adopting the method to make.Obviously, the specific details that the technical staff that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.

Should be understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.

[exemplary embodiment]

Below, describe method according to an exemplary embodiment of the present invention with reference to Fig. 2 A-Fig. 2 H and Fig. 3 and make the detailed step for the bottom electrode of phase change random access memory devices.

With reference to Fig. 2 A-Fig. 2 H, the schematic cross sectional view of the device that the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively obtains respectively.

First, as shown in Figure 2 A, provide Semiconductor substrate 200, the constituent material of Semiconductor substrate 200 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.Exemplarily, in the present embodiment, Semiconductor substrate 200 selects single crystal silicon material to form.In Semiconductor substrate 200, be formed with isolation structure and various trap (well) structure, be formed with circuit element (comprising switching device) on semiconductor substrate 200, in order to simplify, all omitted in diagram.

Be formed with interlayer dielectric layer 201 on semiconductor substrate 200, the lower end being formed with the first metal electrode 202, first metal electrode 202 in interlayer dielectric layer 201 is connected with described circuit element.

Next, the depositing operation adopting those skilled in the art to have the knack of forms hard mask stack structure on interlayer dielectric layer 201, cover interlayer dielectric layer 201 and the first metal electrode 202, described hard mask stack structure comprises stacked resilient coating 203, first hard mask layer 204 and the second hard mask layer 205 from bottom to top.In the present embodiment, the constituent material of resilient coating 203, first hard mask layer 204 and the second hard mask layer 205 can select the oxide, silicon oxynitride and the oxide that are formed by plasma enhanced chemical vapor deposition technique respectively.

Next, described hard mask stack structure is formed the photoresist layer 206 with the top pattern 207 of the first metal electrode 202.The technique forming photoresist layer 206 is had the knack of by those skilled in the art, is no longer repeated at this.

Then, as shown in Figure 2 B, form the first through hole 207 ' in the second hard mask layer 205 in described hard mask stack structure and the first hard mask layer 204, expose resilient coating 203.The processing step forming the first through hole 207 ' comprises: with photoresist layer 206 for mask, implement the first etching and etch the second hard mask layer 205 and the first hard mask layer 204 successively, form the first through hole 207 ' wherein, in the present embodiment, described first etching can adopt C 4f 8, Ar and O 2based on etching gas; Photoresist layer 206 is removed by cineration technics.

Then, as shown in Figure 2 C, described hard mask stack structure deposits spacer material layer 208, fills the first through hole 207 '.In the present embodiment, the constituent material of spacer material layer 208 is silicon nitride.

Then, as shown in Figure 2 D, implement second and be etched with the etched side walling bed of material 208, while exposing resilient coating 203, the spacer material layer 208 of the sidewall of covering first through hole 207 ' is made to be configured for the pattern 209 of second through hole of filling bottom electrode, in the present embodiment, described second etching can adopt CF 4, CHF 3, Ar and O 2based on etching gas.

Then, as shown in Figure 2 E, with the spacer material layer 208 through described second etching for mask, implement the 3rd and be etched with etch buffer layers 203, while exposed portion first metal electrode 202, form the second through hole 209 ' for filling bottom electrode, in the present embodiment, described 3rd etching can adopt C 4f 8, CO, Ar and O 2based on etching gas.

It should be noted that, above-mentioned formation is a kind of example for filling the technical process of the second through hole 209 ' of bottom electrode.Those skilled in the art are understandable that completely, and the technical process that also can be suitable for by implementing other forms the through hole for filling bottom electrode in interlayer dielectric layer 201.

Then, as shown in Figure 2 F, the carbon nano-tube 210 of filling the second through hole 209 ' is completely formed.In the present embodiment, adopt chemical vapor deposition method to form carbon nano-tube 210, depositing temperature is lower than 400 DEG C.Before implementing described depositing operation, form cobalt-base catalyst at the sidewall of the second through hole 209 ' and bottom, decompose when carbonaceous gas contact cobalt-base catalyst surperficial, deposit Formed nanotube.After implementing described depositing operation, the height of the carbon nano-tube 210 of formation is higher than the degree of depth of the second through hole 209 '.

Then, as shown in Figure 2 G, sacrificial material layer 211, with coated carbon nanotube 210, spacer material layer 208 and the second hard mask layer 205.In the present embodiment, the material preferred oxides of sacrificial material layer 211.

Then, as illustrated in figure 2h, cmp is performed, until remove sacrificial material layer 211 completely.After implementing described grinding, the height of carbon nano-tube 210 equals the degree of depth of the second through hole 209 '.Now, carbon nano-tube 210 forms bottom electrode.

So far, complete the processing step that method is according to an exemplary embodiment of the present invention implemented, next, the making of whole semiconductor device can be completed by subsequent technique, comprise: form phase-change material layers and the second metal electrode successively, make the upper-end contact phase-change material layers of the bottom electrode be made up of carbon nano-tube 210.According to the present invention, when depositing operation window reaches critical limit, the carbon nano-tube 210 of formation can meet the requirement of the estimated performance index for bottom electrode, thus the yield of boost device.

With reference to Fig. 3, the flow chart of the step that the method according to an exemplary embodiment of the present invention that illustrated therein is is implemented successively, for schematically illustrating the flow process of whole manufacturing process.

In step 301, provide Semiconductor substrate, be formed with interlayer dielectric layer on a semiconductor substrate, in interlayer dielectric layer, be formed with the first metal electrode;

In step 302, in interlayer dielectric layer, form the through hole for filling bottom electrode, the upper surface of described through hole exposed portion first metal electrode;

In step 303, form the carbon nano-tube of complete filling vias, described carbon nano-tube is as bottom electrode.

The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.

Claims (9)

1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, is formed with interlayer dielectric layer on the semiconductor substrate, in described interlayer dielectric layer, be formed with the first metal electrode;
The through hole for filling bottom electrode is formed, the upper surface of the first metal electrode described in described through hole exposed portion in described interlayer dielectric layer;
Form the carbon nano-tube of filling described through hole completely, described carbon nano-tube is as described bottom electrode.
2. method according to claim 1, is characterized in that, adopt chemical vapor deposition method to form described carbon nano-tube, depositing temperature is lower than 400 DEG C.
3. method according to claim 2, is characterized in that, before implementing described depositing operation, at sidewall and the bottom formation cobalt-base catalyst of described through hole.
4. method according to claim 2, is characterized in that, after implementing described depositing operation, the height of the described carbon nano-tube of formation is higher than the degree of depth of described through hole.
5. method according to claim 4, is characterized in that, after implementing described depositing operation, also comprise the step performing cmp, after implementing described grinding, the height of described carbon nano-tube equals the degree of depth of described through hole.
6. method according to claim 5, is characterized in that, before implementing described grinding, also comprises sacrificial material layer to cover the step of described carbon nano-tube; After implementing described grinding, described sacrificial material layer is completely removed.
7. method according to claim 4, is characterized in that, after implementing described grinding, also comprises the step forming phase-change material layers and the second metal electrode successively, phase-change material layers described in the upper-end contact making the bottom electrode be made up of described carbon nano-tube.
8. method according to claim 1, it is characterized in that, described semiconductor device is phase transition storage, and the lower end of described first metal electrode is communicated with the electronic component be formed in described Semiconductor substrate, and the upper end of described first metal electrode is communicated with the lower end of described bottom electrode.
9. adopt the semiconductor device as the either method in claim 1-8 is formed, it is characterized in that, the bottom electrode in described semiconductor device is made up of carbon nano-tube.
CN201410143549.6A 2014-04-10 2014-04-10 Semiconductor device and manufacturing method thereof CN104979468A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960905A (en) * 2016-01-08 2017-07-18 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method, electronic installation
CN108933171A (en) * 2017-05-24 2018-12-04 清华大学 Semiconductor structure and semiconductor devices

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CN101652873A (en) * 2007-04-05 2010-02-17 美光科技公司 Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
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Publication number Priority date Publication date Assignee Title
CN1448334A (en) * 2002-04-01 2003-10-15 财团法人工业技术研究院 Process for direct low-temperature synthesis of carbon nanotube on substrate material
CN100369205C (en) * 2003-05-01 2008-02-13 三星电子株式会社 Method of forming a conductive line for a semiconductor device using a carbon nanotube and semiconductor device manufactured using the method
US20060076641A1 (en) * 2004-08-23 2006-04-13 Samsung Electronics Co., Ltd. Methods of fabricating phase changeable semiconductor memory devices including multi-plug conductive structures and related devices
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106960905A (en) * 2016-01-08 2017-07-18 中芯国际集成电路制造(上海)有限公司 A kind of semiconductor devices and its manufacture method, electronic installation
CN108933171A (en) * 2017-05-24 2018-12-04 清华大学 Semiconductor structure and semiconductor devices

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