KR960002077B1 - Fabricating method of semiconductor device - Google Patents

Fabricating method of semiconductor device Download PDF

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Publication number
KR960002077B1
KR960002077B1 KR1019920017906A KR920017906A KR960002077B1 KR 960002077 B1 KR960002077 B1 KR 960002077B1 KR 1019920017906 A KR1019920017906 A KR 1019920017906A KR 920017906 A KR920017906 A KR 920017906A KR 960002077 B1 KR960002077 B1 KR 960002077B1
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conductive wiring
spin
glass
forming
insulating layer
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KR1019920017906A
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Korean (ko)
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KR940008014A (en
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최동규
김재갑
고철기
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현대전자산업주식회사
김주용
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The semiconductor device is manufactured by (A) forming a conductive wiring(2) on a semiconductor substrate(1), (B) depositing a 1st insulating layer(3) on the wiring(2), (C) coating the insulating layer(3) with a spin-on-glass(4), which is made of polyimide or polyamide acid and curing it, (D) depositing a 2nd insulating layer(5) on the SOG(4), (E) forming a contact hole exposed by the conductive wiring(2) by etching the 2nd insulating layer, the spin-on-glass and the 1st insulating layer, (F) heating the temperature of chamber up to 100-400 deg.C and lowering the pressure of it to several mTorr, and (G) forming an upper conductive wiring(7) contacted with the lower conductive wiring(2) through the contact hole.

Description

반도체 소자 제조방법Semiconductor device manufacturing method

제1도는 내지 4도는 본 발명에 의하여 하부 도전배선 상부에 층간절연막을 형성하고, 콘택홀을 형성한 다음, 상부 도전배선을 형성하는 공정을 도시한 단면도.1 through 4 are cross-sectional views illustrating a process of forming an interlayer insulating film on an upper conductive wiring, forming a contact hole, and then forming an upper conductive wiring according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘기판 2 : 도전배선1: silicon substrate 2: conductive wiring

3 : 제1절연막 4 : 스핀-온 글래스3: first insulating film 4: spin-on glass

5 : 제2절연막 6 : 포토레지스트 패턴5: second insulating film 6: photoresist pattern

7 : 도전배선7: conductive wiring

본 발명은 반도체소자 제조방법에 관한 것으로 특히, 서브 마이크론 배선 사이의 층간절연막의 중간층에 스핀-온 글래스 막을 도포하고 콘택홀 형성시 노출되는 스핀-온 글래스에서 파티클 또는 수분이 발생되는 것을 제거하기 위해 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to apply a spin-on glass film to an intermediate layer of an interlayer insulating film between sub-micron wirings and to remove particles or moisture from spin-on glass exposed during contact hole formation. A method for manufacturing a semiconductor device.

일반적으로, 반도체소자에서 하부 도전배선과 상부 도전배선 사이에 층간절연막을 형성하는데 이 층간절연막은 먼저 산화막을 증착하고, 그 상부에 스핀-온 글래스(Spin-on-glass)막을 평탄하게 도포하고, 그 상부에 산화막을 증착한다.In general, in the semiconductor device, an interlayer insulating film is formed between the lower conductive wiring and the upper conductive wiring. The interlayer insulating film is first deposited with an oxide film, and a spin-on-glass film is flatly coated thereon. An oxide film is deposited on it.

상기의 층간절연막에 콘택홀을 형성하는 경우에는 층간절연막의 하부층인 산화막을 증착하고 그 상부에 스핀-온 글래스를 도포한 다음, 상기 스핀-온 글래스의 일정 두께를 에치-백하여 콘택홀이 형성될 부분에 있는 스핀- 온 글래스의 두께가 두껍지 않도록 한 다음, 그 상부에 산화막을 형성하는 공정을 사용하였다.In the case of forming a contact hole in the interlayer insulating film, an oxide film, which is a lower layer of the interlayer insulating film, is deposited, spin-on glass is coated on the upper layer, and the contact hole is formed by etching back a predetermined thickness of the spin-on glass. The thickness of the spin-on glass in the portion to be made is not thick, and then an oxide film is formed on the top.

그러나, 상기와 같이 에치-백 공정으로 스핀-온 글래스를 식각할때 불순물 입자가 발생하여 챔버를 오염시키게 되고, 그로 인하여 후속 공정에서 여러가지 문제점을 야기하게 된다.However, as described above, when etching the spin-on glass by the etch-back process, impurity particles are generated to contaminate the chamber, thereby causing various problems in subsequent processes.

따라서, 본 발명은 상기와 같이 스핀-온 글래스의 에치-백 공정에서 발생되는 문제점을 해결하기 위하여 층간절연막으로 산화막, 스핀-온 글래스 및 산화막을 증착한 다음, 상기 층간절연막의 일정부분을 식각하여 콘택홀을 형성하고, 콘택홀의 측벽에서 노출된 스핀-온 글래스에 발생되는 수분 또는 파티클을 제거하도록 하는 반도체소자 제조방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the problems caused in the etch-back process of the spin-on glass as described above, by depositing an oxide film, a spin-on glass and an oxide film as an interlayer insulating film, and then etching a portion of the interlayer insulating film An object of the present invention is to provide a method for forming a contact hole and removing moisture or particles generated in the spin-on glass exposed from the sidewall of the contact hole.

상기한 목적을 달성하기 위하여 하부 도전배선 상부에 층간절연막을 형성하고, 상기 도전배선에 상부 도전배선이 콘택되는 상부 도전배선을 형성하는 방법에 있어서, 반도체기판 상부에 도전배선을 형성하는 단계와, 상기 도전배선 상부에 제1절연막을 증착하고 그 상부에 스핀-온 글래스를 도포하고 경화한 다음, 그 상부에 제2절연막을 증착하는 단계와, 상기 제2절연막, 스핀-온 글래스 및 제1절연막을 식각하여 하부 도전배선이 노출된 콘택홀을 형성하고, 챔버내의 온도를 100-400℃로 높이고 챔버내의 압력을 수 mTorr까지 낮추는 단계와, 상기 콘택홀을 통하여 하부 도전배선에 콘택되는 상부 도전배선을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of forming an interlayer insulating film on an upper conductive wiring and forming an upper conductive wiring on which the upper conductive wiring contacts the conductive wiring, the conductive wiring being formed on the semiconductor substrate. Depositing a first insulating layer on the conductive wiring, applying spin-on glass to the upper portion of the conductive wiring, and curing the second insulating layer on the second insulating layer, the second insulating layer, the spin-on glass, and the first insulating layer. Forming a contact hole exposed to the lower conductive wiring, raising the temperature in the chamber to 100-400 ° C. and lowering the pressure in the chamber to several mTorr, and the upper conductive wiring contacting the lower conductive wiring through the contact hole. It characterized in that it comprises a step of forming.

본 발명에 의하면, 콘택홀의 측벽에서 노출되는 스핀-온 글래스에서 수분이 흘러 나온다고 하여도 고온에 의해 수증기화 되며 챔버의 압력을 낮추게 되면 챔버내의 공기, 개스, 수분이 챔버 밖으로 빠져 나가게 되어 도전배선이 부식되는 등의 문제는 해결된다.According to the present invention, even if moisture flows out of the spin-on glass exposed from the sidewall of the contact hole, water vaporizes due to high temperature, and when the pressure of the chamber is lowered, air, gas, and moisture in the chamber are forced out of the chamber, so that the conductive wiring is reduced. Problems such as corrosion are solved.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제1도 내지 제4도는 본 발명의 실시예에 의해 하부 도전배선, 층간절연막, 콘택홀, 상부 도전배선을 형성하는 단계를 도시한 단면도이다.1 to 4 are cross-sectional views illustrating a step of forming a lower conductive wiring, an interlayer insulating film, a contact hole, and an upper conductive wiring according to an embodiment of the present invention.

제1도는 실리콘기판(또는 하부절연막)(1) 상부에 도전배선(2) 예를들어 폴리실리콘 패턴을 형성한 다음, 상기 실리콘기판(1)과 상기 도전배선(2)의 상부에 제1절연막(3) 예를들어 산화막을 증착하고 그 상부에 스핀-온 글래스(4)를 도포하고 경화시킨 다음, 그 상부에 제2절연막(5) 예를들어 산화막을 증착한 단면도이다.FIG. 1 illustrates a conductive wiring 2, for example, a polysilicon pattern formed on a silicon substrate (or lower insulating layer) 1, and then a first insulating layer on the silicon substrate 1 and the conductive wiring 2. (3) For example, an oxide film is deposited, spin-on glass 4 is applied on top of it, and cured, and then a second insulating film 5, for example, an oxide film is deposited on the top.

여기서, 스핀-온 글래스는 수분의 함량이 많아서 고온에서 잘 플로우되는 특성이 있는데 이 수분을 어느정도 제거하기 위해 경화 공정을 실시하는 것이다.Here, the spin-on glass has a high content of moisture and flows well at high temperature, and a curing process is performed to remove the moisture to some extent.

상기 스핀-온 글래스(4)는 폴리이미드(polyimide) 또는 폴리이미드산(polyamide acid)을 사용할 수 있다.The spin-on glass 4 may use polyimide or polyamide acid.

제2도는 상기 제2절연막(5) 상부에 콘택 마스크용 포토레지스트 패턴(6)을 형성한 다음, 노출된 제2절연막(5)의 일정두께를 습식식각하고 계속하여 남아있는 제2절연막(5)과 스핀-온 글래스(4), 제1절연막(3)을 건식식각하여 도전배선(2)이 노출된 콘택홀을 형성한 단면도이다.FIG. 2 illustrates the formation of the contact mask photoresist pattern 6 on the second insulating film 5, followed by wet etching a predetermined thickness of the exposed second insulating film 5, and the remaining second insulating film 5. ), The spin-on glass 4 and the first insulating film 3 are dry etched to form a contact hole in which the conductive wiring 2 is exposed.

제3도는 상기 포토레지스트 패턴(6)을 제거하고, 콘택홀의 측면에서 노출된 스핀-온 글래스(4)에서 발생되는 수분이나 파티클을 제거한 단면도로서, 상기의 수분은 챔버내를 온도를 100-400℃의 온도로 높히게 되면 증기화 된다. 그리고, 계속하여 챔버안의 압력을 수 mTorr의 압력으로 낮추기 위해 탈개스(Degassing) 공정을 실시하면 챔버내에 있는 개스, 파티클, 증기 등이 제거된다.3 is a cross-sectional view of removing the photoresist pattern 6 and removing moisture or particles generated from the spin-on glass 4 exposed from the side of the contact hole, wherein the moisture is 100-400. If it is raised to a temperature of ℃ it will vaporize. Subsequently, degassing is performed to lower the pressure in the chamber to a pressure of a few mTorr, thereby removing gas, particles, and steam in the chamber.

제4도는 노출된 도전배선(2)에 콘택되는 상부 도전배선(7)을 형성한 단면도이다.4 is a cross-sectional view of the upper conductive wiring 7 formed in contact with the exposed conductive wiring 2.

상기한 본 발명에 의하면, 하부 도전배선에 상부에 제1절연막, 스핀-온 글래스 및 제2절연막을 적층하고, 콘택홀 형성하게 되면 노출되는 콘택홀의 측벽에서 노출된 스핀-온 글래스에서 발생되는 수분이나 파티클이 고온의 온도에서 탈개스 공정에서 완전히 제거된다. 그로 인하여 스핀-온 글래스에서 발생되는 파티클로 인하여 챔버가 오염되는 것이나 수분으로 인하여 도전배선이 부식되는 것을 해결할 수가 있다.According to the present invention described above, the first insulating film, the spin-on glass and the second insulating film are stacked on the lower conductive wiring, and when the contact hole is formed, moisture generated from the exposed spin-on glass from the sidewall of the contact hole is exposed. Or particles are completely removed from the degassing process at high temperatures. Therefore, it is possible to solve the contamination of the chamber due to the particles generated in the spin-on glass or the corrosion of the conductive wiring due to moisture.

Claims (2)

하부 도전배선 상부에 층간절연막을 형성하고, 상기 도전배선에 상부 도전배선이 콘택되는 상부 도전배선을 형성하는 방법에 있어서, 반도체기판 상부에 도전배선을 형성하는 단계와, 상기 도전배선 상부에 제1절연막을 증착하고 그 상부에 스핀-온 글래스를 도포하고 경화한 다음, 그 상부에 제2절연막을 증착하는 단계와, 상기 제2절연막, 스핀-온 글래스 및 제1절연막을 식각하여 하부 도전배선이 노출된 콘택홀을 형성하고, 챔버내의 온도를 100-400℃로 높이고 챔버내의 압력을 수 mTorr까지 낮추는 단계와, 상기 콘택홀을 통하여 하부 도전배선에 콘택되는 상부 도전배선을 형성하는 단계를 포함하는 반도체소자의 제조방법.A method of forming an interlayer insulating film over a lower conductive wiring and forming an upper conductive wiring for contacting an upper conductive wiring on the conductive wiring, the method comprising: forming a conductive wiring on an upper portion of a semiconductor substrate, and forming a first conductive wiring on an upper portion of the conductive wiring; Depositing an insulating film, coating and curing the spin-on glass thereon, and depositing a second insulating layer thereon, and etching the second insulating layer, the spin-on glass and the first insulating layer to form a lower conductive wiring. Forming an exposed contact hole, raising the temperature in the chamber to 100-400 ° C. and lowering the pressure in the chamber to a few mTorr; and forming an upper conductive wiring contacting the lower conductive wiring through the contact hole. Method of manufacturing a semiconductor device. 제1항에 있어서, 상기 스핀-온 글래스는 폴리이미드(Polyimide) 또는 폴리이미드산(Polyamide Acid)로 형성하는 것을 특징으로 하는 반도체소자 제조방법.The method of claim 1, wherein the spin-on glass is formed of polyimide or polyamide acid.
KR1019920017906A 1992-09-30 1992-09-30 Fabricating method of semiconductor device KR960002077B1 (en)

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KR960002077B1 true KR960002077B1 (en) 1996-02-10

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