JPS61172336A - Formation of electrode opening of semiconductor device - Google Patents
Formation of electrode opening of semiconductor deviceInfo
- Publication number
- JPS61172336A JPS61172336A JP1302485A JP1302485A JPS61172336A JP S61172336 A JPS61172336 A JP S61172336A JP 1302485 A JP1302485 A JP 1302485A JP 1302485 A JP1302485 A JP 1302485A JP S61172336 A JPS61172336 A JP S61172336A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- electrode
- electrode opening
- step difference
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 title claims 2
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000002950 deficient Effects 0.000 abstract 2
- 238000007796 conventional method Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体装置電極開口部の形成方法に関し、特
にＬＳＩ（Ｌａｒｇｅ ５ｃａｌｅ Ｉｎｔｅｇｒａｔ
ｉｏｎ−大規模集積回路）において、電極開口部を微細
かつ平坦に形成するための方法に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming an electrode opening in a semiconductor device, and particularly to a method for forming an electrode opening in a semiconductor device.
The present invention relates to a method for forming fine and flat electrode openings in ion (large-scale integrated circuits).
従来例によるこの種、のＬＳＩにおける電極開口部の形
成方法を、第２図（Ａ）ないしくＤ）に工程順。A conventional method of forming electrode openings in this type of LSI is shown in the order of steps in FIGS. 2(A) to 2(D).
かつ模式的に示しである。And it is shown schematically.
すなわち、この従来例方法においては、まず同図（Ａ）
に示すように、シリコン半導体基板１上に絶縁酸化膜２
を形成させ、かつ同絶縁酸化膜２上にフォトレジスト膜
３をパターニング被覆させ、ついで同図ＣＢ）に示すよ
うに、このフォトレジスト膜３をマスクとする選択的エ
ツチングにより、電極開口部４を開口させ、また同図（
Ｃ）に示すように、フォトレジスト膜３を除去したのち
、同図（Ｄ）に示すように、アルミニウムなどの電極、
配線金属層５を形成して、図示しない素子間の電気的接
続をなすのである。That is, in this conventional method, first
As shown in the figure, an insulating oxide film 2 is formed on a silicon semiconductor substrate 1.
A photoresist film 3 is patterned and coated on the insulating oxide film 2, and then the electrode opening 4 is formed by selective etching using the photoresist film 3 as a mask, as shown in CB of the same figure. Open it again (see the same figure)
After removing the photoresist film 3 as shown in C), as shown in FIG.
A wiring metal layer 5 is formed to establish electrical connections between elements (not shown).
こ−で一般的にこの種のＬＳＩにおいては、集積密度向
上の目的で、パターンの可及的微細化が要求されてきて
おり、このため製造時のエツチング操作についても、従
来の湿式エツチングから、被エツチング層となる下地を
７オトレジストとはＣ同形にエツチングし得るところの
９すなわちサイドエツチング量の少ない反応性エツチン
グとか、イオンエツチングなどの乾式エツチングが利用
されるようになってきている。Generally, in this type of LSI, it is required to make the pattern as fine as possible in order to improve the integration density, and for this reason, the etching operation during manufacturing has changed from the conventional wet etching. Dry etching such as reactive etching and ion etching, which can be etched in the same shape as the etching resist, with a small amount of side etching, is now being used to form the underlying layer to be etched.
しかしながら一方、この乾式エツチングにおいては、サ
イドエツチング量が少ない反面、エツチング部分、殊に
こ〜では電極開口部の断面形状が急峻な段差部になって
、同部分に前記の電極、配線金属層５を形成した場合に
は、第２図（Ｄ）に見られる通り、この段差部で電極、
配線材料に“くびれ部分”を生じて、接続不良、断線な
どを誘起し易いという問題点を有するものであった。However, in this dry etching, while the amount of side etching is small, the cross-sectional shape of the electrode opening becomes a steep stepped part in the etched part, especially in this part, and the electrode and wiring metal layer 5 are etched in the same part. When forming an electrode, as shown in FIG.
This has the problem of creating a "necked part" in the wiring material, which tends to cause connection failures, disconnections, etc.
この発明は従来例方法のこのような問題点に鑑み、電極
開口部における段差部の急峻さを緩和して、電極、配線
金属層の接続不良、断線などを解消し得るようにした半
導体装置電極開口部の形成方法を提供することを目的と
している。In view of these problems of the conventional method, the present invention provides a semiconductor device electrode that alleviates the steepness of the stepped portion in the electrode opening and eliminates poor connections and disconnections between electrodes and wiring metal layers. It is an object of the present invention to provide a method for forming an opening.
前記目的を達成するために、この発明方法は、電極開口
部を断面階段状段差部を有する形状に形成させるように
したものである。In order to achieve the above object, the method of the present invention is such that an electrode opening is formed in a shape having a stepped section.
従ってこの発明方法においては、電極開口部を断面階段
状に段差形成させるために、段差部での落差が大幅に緩
和されて、同開口部の微細かつ平坦化を達成できる。Therefore, in the method of the present invention, since the electrode opening is formed with steps in a step-like cross section, the drop at the step is significantly reduced, and the opening can be made fine and flat.
以下この発明に係る半導体装置電極開口部の形成方法の
一実施例につき、第１図（Ａ）ないしくＧ）を参照して
詳綱に説明する。Hereinafter, one embodiment of the method for forming an electrode opening in a semiconductor device according to the present invention will be explained in detail with reference to FIGS. 1(A) to 1(G).
第１Ａ（Ａ）ないしくＧ）はこの実施例方法を工程順に
示すそれぞれ断面図であり、この実施例方法においては
、まず同図（Ａ）に示すように、シリコン半導体基板１
１上に絶縁酸化膜１２を形成させ、かつ同絶縁酸化膜１
２上に第１の２オドレジスト膜１３を、後述する電極開
口部に相当する寸法ａの開口を形成してパターニング被
覆させ、また同図（Ｂ）に示すように、この第１のフォ
トレジスト膜１３上に第２のフォトレジスト膜１４を、
今度は電極開口部よりも大きい寸法すの開口を形成して
パターニング被覆させる。つまり開口部分が階段状にな
るように２層のフォトレジスト膜１３．１４を形成させ
る。こ〜で、これらの各フォトレジスト膜１３．１４は
同一材料、異なる材料の如何を問わない。1A (A) to 1G) are cross-sectional views showing the method of this embodiment in the order of steps. In the method of this embodiment, first, as shown in FIG.
an insulating oxide film 12 is formed on the insulating oxide film 1;
A first photoresist film 13 is patterned and coated on the photoresist film 13 by forming an opening with a size a corresponding to an electrode opening to be described later, and as shown in FIG. A second photoresist film 14 is placed on 13,
Next, an opening with a size larger than the electrode opening is formed and patterned and covered. In other words, two layers of photoresist films 13 and 14 are formed so that the opening portions are stepped. Here, it does not matter whether these photoresist films 13 and 14 are made of the same material or different materials.
ついで同図（Ｃ）に示すように、これらの各フォトレジ
ストｌｌｉ！ １Ｌ１４をエラ手ングマス／ＦＪ−１、
で例えばＣＦ、＋Ｈ２ガスを用いた反応性イオンエツチ
ングにより、前記絶縁酸化膜１２を選択的にエツチング
して、前記第１のフォトレジスト膜１３の開口寸法ｄに
一致、換言すると所定大きさの電極開口部１５を開口さ
せ、続いて同図（Ｄ）に示すように、例えば０２ガスに
よりこれらの各フォトレジスト膜１３．１４をエツチン
グして、ｉｔの７オトレジスト膜１３の露出部分を除去
し、これらの両膜１３．１４の階段状の段差をなくして
、開口の大きさを寸法すに統一させ、電極開口部１５に
絶縁酸化膜１２の一部を露出させる。Then, as shown in the same figure (C), each of these photoresists lli! 1L14 Ela Tengumasu/FJ-1,
Then, the insulating oxide film 12 is selectively etched by reactive ion etching using, for example, CF or +H2 gas to form an electrode having a predetermined size that matches the opening size d of the first photoresist film 13. The opening 15 is opened, and then, as shown in FIG. 1D, each of the photoresist films 13 and 14 is etched using, for example, 02 gas to remove the exposed portion of the IT7 photoresist film 13. By eliminating the step-like difference between these two films 13 and 14, the sizes of the openings are made uniform, and a part of the insulating oxide film 12 is exposed in the electrode opening 15.
次に同図（Ｅ）に示すように、再度、 ＣＦ４＋Ｈ２
ガスを用いた反応性イオンエツチングにより、前記電極
開口部１５の露出された絶縁酸化膜１２を部分的かつ選
択的にエツチングして、この電極開口部１５に前記開口
寸法すに一致する階段状の段差開口部１５ａを形成させ
、さらに同図（Ｆ）に示すように、再度、０２ガスによ
りこれらの残された各フォトレジスト膜１３．１４をす
べてエツチング除去し、このようにして平坦化された断
面階段状の段差部１５ａをもつ電極開口部１５に対し、
同図（Ｇ）に示すように、アルミニウムなどの電極、配
線金属層１６を形成して、図示しない素子間の電気的接
続をなすのである。Next, as shown in the same figure (E), CF4+H2
By reactive ion etching using gas, the exposed insulating oxide film 12 in the electrode opening 15 is partially and selectively etched to form a step-shaped etching in the electrode opening 15 that matches the opening size. Step openings 15a are formed, and as shown in FIG. For the electrode opening 15 having a stepped portion 15a with a stepped cross section,
As shown in FIG. 3G, electrodes such as aluminum and wiring metal layers 16 are formed to establish electrical connections between elements (not shown).
すなわち、この実施例方法においては、電極開口部を階
段状に段差形成させるために、段差部での落差が大幅に
緩和されることになる。That is, in the method of this embodiment, since the electrode opening is formed in a stepped manner, the drop at the stepped portion is significantly reduced.
なお、前記実施例方法においては、エツチングマスクと
してフォトレジストを用いているが、その他、電子線レ
ジスト、Ｘ線レジスト、イオンビームレジストなどであ
ってもよく、また絶縁膜としても、酸化膜以外のアルミ
ナ膜、窒化膜などを用いることができ、さらに電極、配
線金属層についても、アルミニウムのほかにＡｕ、Ｔｉ
Ｗなどの任意の金属であってよい、そしてまた前記実施
例方法の場合には、エツチングマスクを２層に設けて、
電極開口部を２段の階段状に段差形成させているが、よ
り以上複数段の階段状に段差形成させてもよいことは勿
論である。In the method of the above embodiment, a photoresist is used as an etching mask, but it may also be an electron beam resist, an Alumina films, nitride films, etc. can be used, and electrodes and wiring metal layers can also be made of Au, Ti, etc. in addition to aluminum.
It may be any metal such as W, and also in the case of the above embodiment method, the etching mask is provided in two layers,
Although the electrode opening is formed in a two-step shape, it goes without saying that it may be formed in a plurality of steps.
以上詳述したようにこの発明方法によれば、電極開口部
を複数段の階段状に段差形成させるようにしたから、段
差部での落差が大幅に緩和されることになって、この電
極開口部の微細かつ平坦化が容易に達成され、このため
電極開口部に、その後形成される電極、配線金属層に、
従来のような“くびれ部分”などを生ずる慣れがなく、
従って電極、配線の接続不良、断線などを効果的に防止
できるものである。As described in detail above, according to the method of the present invention, the electrode opening is formed with steps in the form of a plurality of steps. This makes it easy to achieve a fine and flattened surface, which allows the electrode opening to be easily formed, as well as to the subsequently formed electrodes and wiring metal layer.
I am not used to creating "neck parts" like in the past,
Therefore, poor connection and disconnection of electrodes and wiring can be effectively prevented.
第１図（Ａ）ないしくＧ）はこの発明に係る電極開口部
の形成方法の一実施例を工程順に示すそれぞれ断面図で
あり、また第２図（Ａ）ないしくＤ）は同上従来例方法
を工程順に示すそれぞれ断面図である。
１１・・・・半導体基板、１２・・・・酸化絶縁膜、１
３および１４・・・・第１および第２の７オトレジスト
ｌ！Ｉ（第１および第２のエツチングマスク）、１５・
・・・電極開口部、１５ａ・・・・電極開口部の階段状
の段差開口部、ＩＢ・・・・電極、配線金属層。
ｗｉ１図
（Ａ）
（Ｃ）
１ｃ；
（Ｅ）
第１図
（Ｆ）
ＣＧ）
ｔａ ２ 図
（Ａ）
ＣＢ）
（Ｃ）
ム
手続補正書（自発）FIGS. 1(A) to 1G) are cross-sectional views showing an example of the method for forming an electrode opening according to the present invention in the order of steps, and FIGS. FIG. 3 is a cross-sectional view showing the method in the order of steps. 11... Semiconductor substrate, 12... Oxide insulating film, 1
3 and 14...first and second 7 otoresist l! I (first and second etching masks), 15.
. . . Electrode opening, 15a . . . Step opening of electrode opening, IB . . . Electrode, wiring metal layer. wi1 Figure (A) (C) 1c; (E) Figure 1 (F) CG) ta Figure 2 (A) CB) (C) Mu procedural amendment (voluntary)
Claims (2)
開口部をエッチング開口させ、この電極開口部に電極、
配線金属層を形成させるようにした半導体装置の製造方
法において、前記電極開口部を少なくとも複数段の階段
状段差部を有する断面形状に形成する工程を含むことを
特徴とする半導体装置電極開口部の形成方法。(1) Electrode openings are selectively etched in the insulating film formed on the semiconductor substrate, and electrodes and
A method of manufacturing a semiconductor device in which a wiring metal layer is formed, comprising the step of forming the electrode opening in a cross-sectional shape having at least a plurality of step-like steps. Formation method.
クを所定開口寸法のパターンで、またこの第１のエッチ
ングマスク上に、第２のエッチングマスクをこれよりも
大きい開口寸法のパターンでそれぞれに形成させ、つい
でこれらの各マスクを利用し、前記絶縁膜を選択的にエ
ッチングして所定寸法の電極開口部を形成させ、続いて
前記第１のエッチングマスクの開口パターンを、第２の
エッチングマスクの開口パターンに一致するまでエッチ
ング除去して、前記電極開口部に絶縁膜の一部を露出さ
せ、さらにこれらの各マスクを利用し、前記露出された
絶縁膜部分を、部分的かつ選択的にエッチング除去して
、前記電極開口部を断面階段状の段差部に形成すること
を特徴とする特許請求の範囲第１項の半導体装置電極開
口部の形成方法。(2) On the insulating film of the semiconductor substrate, a first etching mask is formed in a pattern with a predetermined opening size, and on this first etching mask, a second etching mask is formed in a pattern with a larger opening size. Then, using each of these masks, the insulating film is selectively etched to form an electrode opening of a predetermined size, and then the opening pattern of the first etching mask is etched by a second etching. The insulating film is etched away until it matches the opening pattern of the mask, exposing a portion of the insulating film to the electrode opening, and then using each of these masks, the exposed insulating film portion is partially and selectively removed. 2. The method of forming an electrode opening in a semiconductor device according to claim 1, wherein the electrode opening is etched away to form the electrode opening into a stepped portion having a step-like cross section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1302485A JPS61172336A (en) | 1985-01-25 | 1985-01-25 | Formation of electrode opening of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1302485A JPS61172336A (en) | 1985-01-25 | 1985-01-25 | Formation of electrode opening of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61172336A true JPS61172336A (en) | 1986-08-04 |
Family
ID=11821568
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1302485A Pending JPS61172336A (en) | 1985-01-25 | 1985-01-25 | Formation of electrode opening of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61172336A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61208833A (en) * | 1985-03-13 | 1986-09-17 | Rohm Co Ltd | Manufacture of semiconductor device |
| JPH0637065A (en) * | 1992-05-20 | 1994-02-10 | Internatl Business Mach Corp <Ibm> | Method for manufacture of multistage structure in substrate |
| WO2009154173A1 (en) * | 2008-06-17 | 2009-12-23 | 株式会社アルバック | Method for manufacturing multistep substrate |
| JP2013207006A (en) * | 2012-03-28 | 2013-10-07 | Toppan Printing Co Ltd | Wiring board with through electrode and manufacturing method of the same |
-
1985
- 1985-01-25 JP JP1302485A patent/JPS61172336A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61208833A (en) * | 1985-03-13 | 1986-09-17 | Rohm Co Ltd | Manufacture of semiconductor device |
| JPH0637065A (en) * | 1992-05-20 | 1994-02-10 | Internatl Business Mach Corp <Ibm> | Method for manufacture of multistage structure in substrate |
| WO2009154173A1 (en) * | 2008-06-17 | 2009-12-23 | 株式会社アルバック | Method for manufacturing multistep substrate |
| JP2013207006A (en) * | 2012-03-28 | 2013-10-07 | Toppan Printing Co Ltd | Wiring board with through electrode and manufacturing method of the same |
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