JPH0334319A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0334319A
JPH0334319A JP1169496A JP16949689A JPH0334319A JP H0334319 A JPH0334319 A JP H0334319A JP 1169496 A JP1169496 A JP 1169496A JP 16949689 A JP16949689 A JP 16949689A JP H0334319 A JPH0334319 A JP H0334319A
Authority
JP
Japan
Prior art keywords
film
melting point
point metal
high melting
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1169496A
Other languages
Japanese (ja)
Other versions
JP2778127B2 (en
Inventor
Yasuhiko Ozasa
小笹 康彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1169496A priority Critical patent/JP2778127B2/en
Publication of JPH0334319A publication Critical patent/JPH0334319A/en
Application granted granted Critical
Publication of JP2778127B2 publication Critical patent/JP2778127B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To ravel out a side etching and residue, and to reduce the amount of thinning of the lower insulating film by a method wherein a second high melting point metal film, consisting of the same material as that of a first film, is deposited thicker than the first high melting point metal film, and the flat part of the second high melting point metal film is etched by conducting a reactive ion etching treatment again. CONSTITUTION:An insulating film 2, a first titanium-tungsten film 3 which is a high melting point metal and used as a barrier metal, and an aluminum film 4 are deposited successively on the surface of a silicon substrate 1, and a wiring pattern is formed on a photoresist film 5. Then, an aluminum wiring 4A is formed by etching the aluminum film 4 by conducting a reactive ion etching method using chlorine gas. Then, after the photoresist film 5 has been removed, a second titanium-tungsten film 6 is deposited again. An etching treatment is conducted until the second titanium-tungsten film 6 is removed from its flat part by conducting a reactive ion etching method. At this time, a second titanium-tungsten film 6A is left on the side wall of the aluminum wiring 4A. Then, the first film 3 and the film 6A are etched by conducting an isotropic etching treatment.

Description

【発明の詳細な説明】 ]産業上の利用分野1 本発明は半導体装置の製造方法に関し、特にバリアーメ
タルを有する配線の形成方法に関する。
Detailed Description of the Invention] Industrial Application Field 1 The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a wiring having a barrier metal.

1゛従来の技術j バリアメタルを存するアルミニウム配線の形成方法とし
て、ドライエツチングによる2段階エツチング法が広く
採用されている。
1. Prior Art j A two-step etching method using dry etching is widely used as a method for forming aluminum interconnections containing barrier metal.

はじめに第2図(a>に示すようにシリコン基板1の表
面に、絶縁膜2とバリアメタルとして高融点金属である
チタンタングステンM3とアルミニウム膜Q4を、順次
堆積してからフォトレジスト膜5に配線パターンを形成
する。
First, as shown in FIG. 2 (a), an insulating film 2, titanium tungsten M3, which is a barrier metal, and an aluminum film Q4 are sequentially deposited on the surface of a silicon substrate 1, and then wiring is formed on a photoresist film 5. form a pattern.

つぎに第2図(b)に示ずように、塩素系のガスを用い
た反応性イオンエツチングにより、アルミニウム膜4を
エツチングしてアルミニウム配線4Aを形成する。
Next, as shown in FIG. 2(b), the aluminum film 4 is etched by reactive ion etching using chlorine-based gas to form an aluminum wiring 4A.

つぎに第2図(c)に示すように、ふっ素糸また4i塩
素系のガスを用いた反応性イオンエツチングによりチタ
ンタングステン膜3をエツチングしてアルミニウム配線
4Aの形成を完了する。
Next, as shown in FIG. 2(c), the titanium-tungsten film 3 is etched by reactive ion etching using fluorine thread or 4i chlorine-based gas to complete the formation of the aluminum wiring 4A.

(発明が解決しようとする課題〕 前項に述べた従来の製造方法では、第2図(C)に示す
ように高融点金属膜3のサイドエツチング7が発生する
ことがある。
(Problems to be Solved by the Invention) In the conventional manufacturing method described in the previous section, side etching 7 of the high melting point metal film 3 may occur as shown in FIG. 2(C).

また反応性イオンエッチング0場合、リーク電流の増大
などの原因となる残渣8が残り易く、残渣8を除去する
ためにはオーバーエツチングが必要で下地の絶縁膜2の
膜減り量が大きくなる。
Further, in the case of zero reactive ion etching, the residue 8 that causes an increase in leakage current is likely to remain, and in order to remove the residue 8, over-etching is necessary, which increases the amount of film reduction of the underlying insulating film 2.

本発明の目的は、高融点金属膜のサイドエツチングや残
渣を解消し、下地の絶縁j摸の膜減り量を軽減すること
にある。
An object of the present invention is to eliminate side etching and residue of a high melting point metal film and to reduce the amount of film loss of the underlying insulation layer.

(課題を解決するための手段 本発明の半導体装置の製造方法は、半導体基板表面に絶
縁膜と第1の高融点金属を順次堆積したのち、アルミニ
ウム1模またはアルミニウム合金膜を堆積してから、配
線パターンのフォトレジスト膜をマスクにして、前記ア
ルミニウム膜またはアルミニウム合金膜を反応性イオン
エツチングしてから7オトレジス1へ膜を除去し、さら
に前記第1の高融点金属膜と同一材質からなる第2の高
融点金属膜を前記第1の高融点金属膜より厚く堆積し、
再度反応性イオンエツチングにより前記第2グ)高融点
金属膜の平坦部をエツチングすることにより、前記第1
の高融点金属膜および既にパターニングされている前記
アルミニウム1模またはアルミニウム合金膜の配線の側
壁に残った第2の高融点金属膜を等方性エツチングする
ことから楢成されている。
(Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention includes sequentially depositing an insulating film and a first high melting point metal on the surface of a semiconductor substrate, and then depositing an aluminum 1 model or an aluminum alloy film. Using the photoresist film of the wiring pattern as a mask, the aluminum film or aluminum alloy film is subjected to reactive ion etching, and then the film is removed to the photoresist 1. depositing a second high melting point metal film thicker than the first high melting point metal film;
By etching the flat part of the high melting point metal film (G) again by reactive ion etching, the first film is etched.
The layer is formed by isotropically etching the high melting point metal film and the second high melting point metal film remaining on the side wall of the wiring of the aluminum 1 pattern or aluminum alloy film that has already been patterned.

[実施例」 つぎに本発明について、図面を参照して説明する。[Example" Next, the present invention will be explained with reference to the drawings.

はじめに第1図(a)に示すように、シリコン基板1の
表面に絶縁膜2、バリアメタルとして高融点金属である
第1のチタンタングステン膜3(厚さ0.1μm〉およ
びアルミニウム膜4(厚さ0.8μ+n )を順次堆積
し、フォトレジスト膜5に配線パターンを形成する。
First, as shown in FIG. 1(a), an insulating film 2 is formed on the surface of a silicon substrate 1, a first titanium tungsten film 3 (thickness: 0.1 μm), which is a high melting point metal, and an aluminum film 4 (thickness: A wiring pattern is formed on the photoresist film 5 by sequentially depositing 0.8μ+n.

つぎに第1図(b)に示すように、塩素系のガス(例え
ばBCe、またはCC!!4>を用いた反応性イオンエ
ツチングにより、アルミニウム膜4をエツチングしてア
ルミニウム配線4Aを形成する。
Next, as shown in FIG. 1(b), the aluminum film 4 is etched by reactive ion etching using a chlorine-based gas (for example, BCe or CC!!4) to form an aluminum wiring 4A.

つき′に第1 I21(c )に示すように、フオl・
レジスト膜5を除去したのち、再び第2のチタンタング
ステン膜6(厚さ0.2μxn )を堆積する。第2の
チタンタングステン膜6は、第1のチタンタングステン
膜3よりも厚くしなければならない。
As shown in 1st I21(c),
After removing the resist film 5, a second titanium-tungsten film 6 (thickness: 0.2 μxn) is deposited again. The second titanium tungsten film 6 must be thicker than the first titanium tungsten film 3.

つぎに第1図(d)に示すように、ふっ素糸ガス(例え
ばCF、または5F6)を用いた反応性イオンエツチン
グにより、平坦部の第2のチタンタングステン膜もがな
くなるまでエツチングする。二のときアルミニウム配線
4Aの側壁には第2のチタンタングステン膜6Aが残る
Next, as shown in FIG. 1(d), the second titanium-tungsten film on the flat portion is etched by reactive ion etching using a fluorine thread gas (for example, CF or 5F6) until the second titanium-tungsten film is also completely removed. In the second case, the second titanium-tungsten film 6A remains on the side wall of the aluminum wiring 4A.

このとき第1のチタンタングステン膜3!3Aが残って
いなければならないことから、第2のチタンタングステ
ン膜6は第1のチタンタングステン1摸3Aよりも厚く
なければならないということがわかる。
Since the first titanium-tungsten film 3!3A must remain at this time, it can be seen that the second titanium-tungsten film 6 must be thicker than the first titanium-tungsten film 1!3A.

−)ぎに第1図(e)に示すように、等方性エツチング
(例えばH2O2を用いたウエットエ・ソチング、また
はCF4+02ガスを用いたプラズマエツチング)によ
り第1のチタンタングステン膜3とアルミニウム配線4
Aの側壁の第2のチタンタングステン膜6Aをエツチン
グする。
-) Next, as shown in FIG. 1(e), the first titanium-tungsten film 3 and the aluminum wiring 4 are etched by isotropic etching (for example, wet etching using H2O2 or plasma etching using CF4+02 gas).
The second titanium tungsten film 6A on the side wall of A is etched.

高融点金属膜3および6としては、チタンタングステン
膜の替りにチタン膜または窒化チタン膜で置き代えるこ
とも可能である。
As the high melting point metal films 3 and 6, it is also possible to replace the titanium tungsten film with a titanium film or a titanium nitride film.

一ヒ述の実施例で用いたアルミニウム膜の代りに、アル
ミニウムき金膜で置き代えることも可能である。
It is also possible to replace the aluminum film used in the first embodiment with an aluminum-plated gold film.

(発明の効果〕 以上説明したように本発明は、アルミニウム配線4Aの
側壁の第2のチタンタングステン膜6Aを等方性エツチ
ングで除去することにより、サイドエツチング7や残渣
8がなく、また下地の絶縁膜2の膜減り量も少なくでき
る効果がある。
(Effects of the Invention) As explained above, the present invention removes the second titanium tungsten film 6A on the side wall of the aluminum wiring 4A by isotropic etching, thereby eliminating the side etching 7 and the residue 8, and removing the underlying layer. This has the effect of reducing the amount of film loss in the insulating film 2.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜<e)は本発明の実施例を工程順に示す
断面図、第2図(a)〜(C)は従来の技術を工程順に
示す断面図である。 ■・・シリコン基板、2・・・絶縁膜、3・・・チタン
タングステン膜、3A・・・第1のチタンタングステン
膜、4・・・アルミニウム1模、4A・・・アルミニウ
ム配線、5・・・フォ1〜レジスト膜、b・・・第2の
チタンタングステン膜、6A・・・側壁の第2のチタン
タングステン膜、7・・・サイドエツチング、8・・・
残渣。 代理入 弁理士 内 原  昔 第 ! 図
FIGS. 1(a) to <e) are sectional views showing an embodiment of the present invention in the order of steps, and FIGS. 2(a) to 2(C) are sectional views showing the conventional technique in the order of steps. ■...Silicon substrate, 2...Insulating film, 3...Titanium tungsten film, 3A...First titanium tungsten film, 4...Aluminum 1 model, 4A...Aluminum wiring, 5...・F1~Resist film, b...Second titanium tungsten film, 6A...Second titanium tungsten film on side wall, 7...Side etching, 8...
Residue. Acting Patent Attorney Uchihara Mukashidai! figure

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表面に絶縁膜と第1の高融点金属を順次堆積
したのち、アルミニウム膜またはアルミニウム合金膜を
堆積してから、配線パターンのフォトレジスト膜をマス
クにして、前記アルミニウム膜またはアルミニウム合金
膜を反応性イオンエッチングしてからフォトレジスト膜
を除去し、さらに前記第1の高融点金属膜と同一材質か
らなる第2の高融点金属膜を前記第1の高融点金属膜よ
り厚く堆積し、再度反応性イオンエッチングにより前記
第2の高融点金属膜の平坦部をエッチングすることによ
り、前記第1の高融点金属膜および既にパターニングさ
れている前記アルミニウム膜またはアルミニウム合金膜
の配線の側壁に残った第2の高融点金属膜を等方性エッ
チングすることを特徴とする半導体装置の製造方法。
After sequentially depositing an insulating film and a first high-melting point metal on the surface of a semiconductor substrate, an aluminum film or an aluminum alloy film is deposited, and then the aluminum film or aluminum alloy film is deposited using a photoresist film of a wiring pattern as a mask. After reactive ion etching, the photoresist film is removed, and a second high melting point metal film made of the same material as the first high melting point metal film is deposited to be thicker than the first high melting point metal film, and then the photoresist film is removed again. By etching the flat part of the second high melting point metal film by reactive ion etching, the remaining portions of the wiring of the first high melting point metal film and the already patterned aluminum film or aluminum alloy film are removed. A method for manufacturing a semiconductor device, comprising isotropically etching a second high melting point metal film.
JP1169496A 1989-06-29 1989-06-29 Method for manufacturing semiconductor device Expired - Lifetime JP2778127B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1169496A JP2778127B2 (en) 1989-06-29 1989-06-29 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1169496A JP2778127B2 (en) 1989-06-29 1989-06-29 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0334319A true JPH0334319A (en) 1991-02-14
JP2778127B2 JP2778127B2 (en) 1998-07-23

Family

ID=15887601

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1169496A Expired - Lifetime JP2778127B2 (en) 1989-06-29 1989-06-29 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2778127B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187262A (en) * 1997-09-03 1999-03-30 Toshiba Corp Semiconductor device and manufacture thereof
JP2007500445A (en) * 2003-07-25 2007-01-11 ユニティブ・インターナショナル・リミテッド Method of forming a conductive structure including a titanium-tungsten base layer and related structures

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1187262A (en) * 1997-09-03 1999-03-30 Toshiba Corp Semiconductor device and manufacture thereof
JP2007500445A (en) * 2003-07-25 2007-01-11 ユニティブ・インターナショナル・リミテッド Method of forming a conductive structure including a titanium-tungsten base layer and related structures

Also Published As

Publication number Publication date
JP2778127B2 (en) 1998-07-23

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