KR100190376B1 - Forming method for metal wiring in semiconductor device - Google Patents
Forming method for metal wiring in semiconductor device Download PDFInfo
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- KR100190376B1 KR100190376B1 KR1019950006555A KR19950006555A KR100190376B1 KR 100190376 B1 KR100190376 B1 KR 100190376B1 KR 1019950006555 A KR1019950006555 A KR 1019950006555A KR 19950006555 A KR19950006555 A KR 19950006555A KR 100190376 B1 KR100190376 B1 KR 100190376B1
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- conductive layer
- tungsten
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 title claims description 18
- 239000002184 metal Substances 0.000 title claims description 18
- 239000004065 semiconductor Substances 0.000 title description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 30
- 239000010937 tungsten Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000007789 gas Substances 0.000 claims abstract 12
- 229910000838 Al alloy Inorganic materials 0.000 claims description 16
- 238000001020 plasma etching Methods 0.000 claims description 5
- 238000009832 plasma treatment Methods 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 3
- 239000001301 oxygen Substances 0.000 claims 3
- 229910052760 oxygen Inorganic materials 0.000 claims 3
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 229910001930 tungsten oxide Inorganic materials 0.000 description 4
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- VVRQVWSVLMGPRN-UHFFFAOYSA-N oxotungsten Chemical class [W]=O VVRQVWSVLMGPRN-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 텅스텐층(14), 전도층(15)을 차례로 형성하는 단계; 상기 전도층(15)의 예정된 부위를 제거하는 단계를 포함하는 소자간 콘택방법에 있어서, SF6, O2, WF6개스를 포함하는 혼합개스를 이용하여 상기 텅스텐층(14)의 노출된 부위를 식각하는 것을 특징으로 하며 텅스텐층(14)의 언더커트현상의 발생을 방지하고 이에따라 소자의 제조 수율 및 전기적 특성을 향상시킬 수 있는 소자간 콘택방법에 관한 것이다.The present invention comprises the steps of sequentially forming the tungsten layer 14, the conductive layer 15; In a device-to-device contact method comprising removing a predetermined portion of the conductive layer 15, the exposed portion of the tungsten layer 14 using a mixed gas including SF 6 , O 2 , and WF 6 gases. Etching and to prevent the under-cut phenomenon of the tungsten layer 14 and to improve the manufacturing yield and electrical properties of the device according to the present invention.
Description
제1도는 종래기술에 따라 형성된 다층 금속배선 단면도.1 is a cross-sectional view of a multilayer metallization formed in accordance with the prior art.
제2A도 내지 2D도는 본 발명의 일실시예에 따른 다층 금속배선 형성 공정도.2A to 2D are multi-layered metallization process diagrams according to one embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 전도층 12 : 절연층11 conductive layer 12 insulating layer
13 : 장벽금속층 14 : 텅스텐층13 barrier metal layer 14 tungsten layer
15 : 알루미늄 합금층 16 : 감광층15 aluminum alloy layer 16 photosensitive layer
17 : 폴리머 18 : 텅스텐 산화물17 polymer 18 tungsten oxide
본 발명은 반도체 기술에 관한 것으로 특히 반도체 소자의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor technology, and more particularly to a method for forming metal wiring in a semiconductor device.
제1도는 종래기술에 따라 형성된 다층 금속배선을 도시한 단면도로서, 이하 이를 참조하여 종래기술을 살펴본다.1 is a cross-sectional view illustrating a multilayer metal wiring formed according to the prior art, and looks at the prior art with reference to the following.
우선, 전도층(1) 상부에 절연층(2)을 형성하고, 예정된 부위에 콘택홀을 형성한 다음, 장벽금속층(barrier metal layer)(3)(예를들어, Ti/TiN),텅스텐층(4), 알루미늄 합금층(5)을 차례로 증착한다. 이어서, 알루미늄 합금층(5) 상부에 금속배선 형성을 위한 감광막 패턴(6)을 형성하고 이를 식각 마스크로 사용하여 알루미늄 합금층(5), 텅스텐층(4) 및 장벽금속층(3)을 선택 식각한다.First, an insulating layer 2 is formed on the conductive layer 1, a contact hole is formed in a predetermined portion, and then a barrier metal layer 3 (for example, Ti / TiN) and a tungsten layer is formed. (4) and aluminum alloy layer 5 are deposited one after another. Subsequently, the photoresist pattern 6 for forming metal wirings is formed on the aluminum alloy layer 5, and the aluminum alloy layer 5, the tungsten layer 4, and the barrier metal layer 3 are selectively etched using the photoresist pattern 6 as an etching mask. do.
이때, 텅스텐층(4)의 선택 식각은 SF6가스를 사용한다.In this case, the selective etching of the tungsten layer 4 uses SF 6 gas.
그러나, 전술한 종래기술에서 텅스텐층 식각을 위하여 사용하는 SF6가스는 등방성 식각 특성을 갖기 때문에 도시된 바와 같은 텅스텐층의 언더컷(undercut)현상을 유발시키는 문제점을 초래한다.However, since the SF 6 gas used for the tungsten layer etching in the above-described prior art has an isotropic etching property, it causes a problem of causing undercut of the tungsten layer as shown.
따라서, 본 발명은 텅스텐층을 포함하는 적층 구조의 금속배선 패터닝시 텅스텐층의 언더컷 현상을 방지할 수 있는 금속배선 형성방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring that can prevent the undercut phenomenon of the tungsten layer during patterning of the metal wiring of the laminated structure including the tungsten layer.
상기 목적을 달성하기 위하여 본 발명은 텅스텐층을 포함하는 적층 구조의 금속배선 형성방법에 있어서, 소정의 하부층 상에 상기 텅스텐층 및 전도층을 차례로 형성하는 단계; 상기 전도층을 선택 식각하는 단계; 및 노출된 상기 텅스텐층을 선택 식각하되 SF6가스, O2가스 및 WF6가스를 포함하는 혼합가스를 사용하여 플라즈마 식각하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method of forming a metal wiring structure of a laminated structure including a tungsten layer, comprising: sequentially forming the tungsten layer and the conductive layer on a predetermined lower layer; Selectively etching the conductive layer; And selectively etching the exposed tungsten layer, and plasma etching using a mixed gas including SF 6 gas, O 2 gas, and WF 6 gas.
본 발명은 텅스텐층을 포함하는 적층 구조의 금속배선 패터닝시 SF6+ O2+ WF6가스를 적절하게 조합하는 텅스텐층을 식각함으로써 텅스텐층의 언더컷 현상의 발생을 방지하는 기술이다. 즉, SF6가스는 텅스텐의 식각 소오스 가스이며, WF6가스는 O2가스와 함께 SF6가스에 의한 식각과 동시에 식각된 텅스텐 측벽에 텅스텐 산화물(WOX,WSxOy)이 증가되도록 한다. O2가스는 또한 WF6가스를 활성화 시키는 촉매 역할을 하기도 한다.The present invention is a technique for preventing the occurrence of the undercut phenomenon of the tungsten layer by etching the tungsten layer to properly combine the SF 6 + O 2 + WF 6 gas during the metallization patterning of the laminated structure including the tungsten layer. That is, SF 6 gas is an etch source gas of tungsten, and WF 6 gas causes an increase in tungsten oxides (WO X, WS x O y ) on the etched tungsten sidewall simultaneously with the etching by SF 6 gas together with O 2 gas. . O 2 gas also acts as a catalyst to activate the WF 6 gas.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 본 발명의 바람직한 실시예를 소개한다.Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.
첨부된 도면 제2A도 내지 제2D도는 본 발명의 일 실시예에 따른 다층 금속배선 형성 공정도로서, 이하 이를 참조하여 그 공정을 상세히 설명한다.2A to 2D are attached to the process of forming a multi-layered metal wiring according to an embodiment of the present invention, the process will be described in detail below.
먼저, 제2A도에 도시된 바와 같이 전도층(11) 상부에 절연층(2)을 형성하고, 사진식각법으로 예정된 부위에 콘택홀을 형성한 다음, Ti/TiN층과 같은 장벽금속층층(13), 텅스텐층(14) 및 알루미늄 합금층(15)을 차례로 형성한다. 이어서 알루미늄 합금층(15)상에 금속배선 형성용 감광막 패턴(16)을 형성하고 이를 식각 마스크로 사용하여 알루미늄 합금층(15)을 선택 식각한다. 이때 알루미늄 합금층(15)을 선택 식각하기 위해 BCl3가스 또는 Cl2가스를 사용하는데 도시된 바와 같이 알루미늄 합금층(15)의 측벽에 폴리머(17)가 형성된다.First, as shown in FIG. 2A, an insulating layer 2 is formed on the conductive layer 11, a contact hole is formed in a predetermined portion by a photolithography method, and then a barrier metal layer layer such as a Ti / TiN layer ( 13), the tungsten layer 14 and the aluminum alloy layer 15 are sequentially formed. Subsequently, the photoresist film pattern 16 for forming metal wirings is formed on the aluminum alloy layer 15, and the aluminum alloy layer 15 is selectively etched using the photoresist pattern 16 as an etching mask. At this time, the polymer 17 is formed on the sidewall of the aluminum alloy layer 15 as shown in using BCl 3 gas or Cl 2 gas to selectively etch the aluminum alloy layer 15.
이어서, 제2B도에 도시된 바와 같이 동일한 (알루미늄 합금층(15)의 식각을 위해 사용한)식각 챔버 내에서 50내지 100SCCM의 유량으로 100내지 500mTorr의 압력을 유지하며, 플라즈마를 발생시키기 위해 100내지 500W의 전력을 인가하여 O2플라즈마 처리를 수행함으로써 알루미늄 합금층(15)의 측벽에 형성된 폴리머(17)를 제거한다.Then, in the same etching chamber (used for etching the aluminum alloy layer 15) as shown in FIG. 2B, a pressure of 100 to 500 mTorr is maintained at a flow rate of 50 to 100 SCCM, and 100 to The polymer 17 formed on the sidewall of the aluminum alloy layer 15 is removed by applying a 500 W electric power to perform an O 2 plasma treatment.
계속해서, 제2C도에 도시된 바와 같이 50내지 100SCCM의 SF6가스, 10 내지 30SCCM의 O2가스, 10내지 40SCCM의 WF6가스를 포함하여 100내지 300mTorr의 압력을 유지하도록 혼합한 혼합가스에 100 내지 1000W의 전력, 50내지 500Gauss의 자장을 인가하여 플라즈마를 형성하고, 이를 이용하여 노출된 텅스텐층(14)을 선택 식각한다. 이때 식각과 함께 알루미늄 합금층(15) 및 텅스텐층(14)의 측벽에 텅스텐 산화물(18)이 증착되며, 텅스텐 산화물(18)이 알루미늄 합금층(15) 및 식각된 텅스텐층(14)의 측벽에 형성되기 때문에 텅스텐층(14)의 언더컷 현상을 억제할 수 있게 된다.Subsequently, as shown in FIG. 2C, the mixed gas is mixed to maintain a pressure of 100 to 300 mTorr including SF 6 gas of 50 to 100 SCCM, O 2 gas of 10 to 30 SCCM, and WF 6 gas of 10 to 40 SCCM. A plasma is formed by applying a power of 100 to 1000 W and a magnetic field of 50 to 500 Gauss, and the exposed tungsten layer 14 is selectively etched using the plasma. At this time, the tungsten oxide 18 is deposited on the sidewalls of the aluminum alloy layer 15 and the tungsten layer 14 together with etching, and the tungsten oxide 18 is formed on the sidewalls of the aluminum alloy layer 15 and the etched tungsten layer 14. Since it is formed in the film, the undercut phenomenon of the tungsten layer 14 can be suppressed.
다음으로, 제2D도에 도시된 바와 같이 감광막 패턴(16)을 제거한다.Next, the photoresist pattern 16 is removed as shown in FIG. 2D.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러가지 치환, 변환 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어서 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, conversions, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
예를들어, 전술한 실시예에서는 텅스텐층(14)상부에 알루미늄 합금층(15)을 형성하는 것을 일례로 들어 설명하였으나, 본 발명은 알루미늄 합금층(15)을 대신하여 알루미늄층이나 그 이외의 전도층(특히 금속층)을 사용하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, the aluminum alloy layer 15 is formed on the tungsten layer 14 by way of example. However, the present invention replaces the aluminum alloy layer 15 with an aluminum layer or the like. It is also applicable to the case of using a conductive layer (especially a metal layer).
상기와 같이 이루어지는 본 발명은 텅스텐층을 포함하는 적층 구조의 금속배선 패터닝시 텅스텐층의 언더컷 현상을 방지하는 효과가 있으며 이에따라 반도체 소자의 제조 수율 및 전기적 특성을 향상시키는 효과가 있다.The present invention as described above has the effect of preventing the undercut phenomenon of the tungsten layer during the metallization patterning of the laminated structure including the tungsten layer, thereby improving the manufacturing yield and electrical properties of the semiconductor device.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006555A KR100190376B1 (en) | 1995-03-27 | 1995-03-27 | Forming method for metal wiring in semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950006555A KR100190376B1 (en) | 1995-03-27 | 1995-03-27 | Forming method for metal wiring in semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR960035820A KR960035820A (en) | 1996-10-28 |
| KR100190376B1 true KR100190376B1 (en) | 1999-06-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019950006555A KR100190376B1 (en) | 1995-03-27 | 1995-03-27 | Forming method for metal wiring in semiconductor device |
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| KR (1) | KR100190376B1 (en) |
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1995
- 1995-03-27 KR KR1019950006555A patent/KR100190376B1/en not_active IP Right Cessation
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| KR960035820A (en) | 1996-10-28 |
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