KR100549333B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
- Publication number
- KR100549333B1 KR100549333B1 KR1019980041671A KR19980041671A KR100549333B1 KR 100549333 B1 KR100549333 B1 KR 100549333B1 KR 1019980041671 A KR1019980041671 A KR 1019980041671A KR 19980041671 A KR19980041671 A KR 19980041671A KR 100549333 B1 KR100549333 B1 KR 100549333B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- forming
- metal wiring
- metal
- table top
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 금속배선 형성 방법에 관한 것이다.The present invention relates to a method for forming metal wiring of a semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
본 발명은 금속배선 상부에 형성된 테이블 탑(table top)을 제거하여 보이드(void) 형성을 억제하므로서, 소자의 신뢰성을 향상시키고자 한다.The present invention is to improve the reliability of the device by suppressing the formation of void (void) by removing the table top (top) formed on the metal wiring.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
본 발명은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판에 층간 절연막을 형성한 후, 장벽 금속층, 금속층 및 반사 방지층을 순차적으로 형성하는 단계; 제 1 마스크층을 이용한 주식각 공정을 통해 상기 반사 방지층 및 상기 금속층을 순차적으로 식각하고, 이로 인하여 상기 금속층 양측벽에 폴리머가 형성되고, 동시에 상기 폴리머상에 테이블 탑이 발생되는 단계; 상기 테이블 탑을 노출시키기 위해, 상기 제 1 마스크층의 일부분을 침식시켜 제 2 마스크층을 이루는 단계; 및 상기 제 2 마스크층을 이용한 과도 식각 공정을 통해 상기 테이블 탑 및 상기 장벽 금속층을 식각하여 금속배선을 형성하는 단계로 이루어진다.The present invention comprises the steps of sequentially forming a barrier metal layer, a metal layer and an antireflection layer after forming an interlayer insulating film on a substrate on which various elements for forming a semiconductor device are formed; Sequentially etching the anti-reflection layer and the metal layer through a stock angle process using a first mask layer, thereby forming a polymer on both side walls of the metal layer and simultaneously generating a table top on the polymer; Eroding a portion of the first mask layer to form a second mask layer to expose the table top; And forming a metal wiring by etching the table top and the barrier metal layer through a transient etching process using the second mask layer.
4. 발명의 중요한 용도4. Important uses of the invention
모든 반도체 소자의 금속배선 형성 방법.Method of forming metal wiring of all semiconductor devices.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로서, 특히 금속배선 상부에 형성된 테이블 탑(table top)을 제거하여 보이드(void) 형성을 억제하므로서, 소자의 신뢰성을 향상시킬 수 있는 금속배선 형성 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a process for forming a metal wiring that can improve the reliability of a device by removing voids by removing a table top formed on an upper portion of the metal wiring. will be.
일반적으로 금속배선 형성후 외부 입자 또는 수분 등의 침투를 방지하기 위하여, PECVD(Plasma Enhance Chemical Vapor Deposition) 공정에 의한 질화막 및 산화막의 이층 구조 보호막이 형성된다. 이러한 방법에 의한 보호막 형성 방법이 도 1에 도시되었다.In general, in order to prevent penetration of external particles or moisture after metal wiring is formed, a double layer protective film of a nitride film and an oxide film is formed by a Plasma Enhance Chemical Vapor Deposition (PECVD) process. A protective film formation method by this method is shown in FIG.
도 1은 종래의 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도로서, 금속배선 형성후 PECVD 공정에 의해 형성된 보호막이 도시된다.FIG. 1 is a cross-sectional view for explaining a metal wiring formation method of a conventional semiconductor device, and a protective film formed by a PECVD process after metal wiring formation is illustrated.
반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(11)에 층간 절연막(12)을 형성한 후, 타이타늄(Ti)/타이타늄 나이트라이드(TiN)의 이층 구조인 장벽 금속층(13), 금속배선용 알루미늄(Al)층(14) 및 타이타늄 나이트라이드를 사용한 반사 방지층(15)을 순차적으로 형성한다. 각각의 식각비가 다른 식각제를 사용한 식각 공정으로 반사 방지층(15), 알루미늄층(14) 및 장벽 금속층(13)을 순차적으로 식각하고, 이로 인하여 금속배선이 형성된다. 상기 금속배선 형성후, PECVD 공정을 통해 상기 전체 구조상에 산화막(16) 및 질화막(17)을 형성하여 보호막으로 사용한다.After the interlayer insulating film 12 is formed on the substrate 11 having various elements for forming a semiconductor device, the barrier metal layer 13, which is a two-layer structure of titanium (Ti) / titanium nitride (TiN), and aluminum for metal wiring ( Al) layer 14 and antireflection layer 15 using titanium nitride are sequentially formed. The antireflection layer 15, the aluminum layer 14, and the barrier metal layer 13 are sequentially etched by an etching process using an etchant having different etching ratios, thereby forming metal wirings. After the metal wiring is formed, an oxide film 16 and a nitride film 17 are formed on the entire structure through a PECVD process to be used as a protective film.
상기에서, PECVD 공정을 통해 형성된 보호막은 갭 필링(Gap Filling) 능력이 저하되어 도 1의 A와 같은 보이드가 발생된다.In the above, the protective film formed through the PECVD process is the gap filling (Gap Filling) capacity is reduced to generate voids as shown in A of FIG.
이에 따라, 최근에는 고밀도 플라즈마 화학 기상 증착법(High Density Plasma Chemical Vapor Deposition)을 통해 산화막을 형성하는 방법이 제시되었다. 이러한 방법에 의한 보호막 형성 방법이 도 2에 도시되었다.Accordingly, recently, a method of forming an oxide film through high density plasma chemical vapor deposition has been proposed. A protective film formation method by this method is shown in FIG.
도 2는 종래의 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도로서, 금속배선 형성후 고밀도 플라즈마 화학 기상 증착법에 의해 형성된 보호막이 도시된다.FIG. 2 is a cross-sectional view illustrating a conventional method for forming metal wirings of a semiconductor device, and shows a protective film formed by a high density plasma chemical vapor deposition method after forming metal wirings.
반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(21)에 층간 절연막(22)을 형성한 후, 타이타늄/타이타늄 나이트라이드의 이층 구조인 장벽 금속층(23), 금속배선용 알루미늄층(24) 및 타이타늄 나이트라이드를 사용한 반사 방지층(25)을 순차적으로 형성한다. 각각의 식각비가 다른 식각제를 사용한 식각 공정으로 반사 방지층(25), 알루미늄층(24) 및 장벽 금속층(23)을 순차적으로 식각하고, 이로 인하여 금속배선이 형성된다. 상기 금속배선 형성후, 고밀도 플라즈마 화학 기상 증착법을 통해 상기 전체 구조상에 산화막(26)을 형성하여 보호막으로 사용한다.After the interlayer insulating film 22 is formed on the substrate 21 on which various elements for forming a semiconductor device are formed, the barrier metal layer 23, which is a two-layer structure of titanium / titanium nitride, the aluminum layer 24 for metal wiring 24, and titanium nitride The antireflection layer 25 using the ride is formed sequentially. The anti-reflection layer 25, the aluminum layer 24, and the barrier metal layer 23 are sequentially etched by an etching process using an etchant having different etching ratios, thereby forming metal wirings. After the metal wiring is formed, an oxide film 26 is formed on the entire structure through high density plasma chemical vapor deposition and used as a protective film.
상기에서, 식각 공정은 염소계 가스(Chlorine Gas)에서 화학적인 반응으로 제거되는 알루미늄층(24)과 물리적으로 제거되는 타이타늄 나이트라이드의 반사 방지층(25)들의 식각 메카니즘(Etch Mechanism)으로 인하여, 도 2의 C와 같은 테이블 탑(Table top)이 발생하게 되며, 스페이싱 마진(Spacing Margin) 역시 소자가 수축(shrink)될수록 더욱 좁아진다. 또한 보호막을 형성하기 위한 고밀도 플라즈마 화학 기상 증착시, 테이블 탑 하부의 금속배선(24) 좌우측에 산화막(26)이 완전히 매립되지 않아 도 2의 B와 같은 보이드가 발생하게 된다.In the above, the etching process is due to the etching mechanism of the aluminum layer 24 removed by a chemical reaction in the chlorine-based gas and the antireflection layers 25 of titanium nitride physically removed, FIG. 2. A table top such as C occurs, and the spacing margin becomes narrower as the device shrinks. In addition, during the high-density plasma chemical vapor deposition for forming the protective film, the oxide film 26 is not completely embedded in the left and right sides of the metal wiring 24 under the tabletop, thereby generating voids as shown in FIG. 2.
상술한 바와 같이, 종래의 금속배선 형성 방법은 금속배선 상부에 형성된 테이블 탑과 금속배선의 스페이서 마진 감소로 인하여 보호막 형성시 금속배선의 측벽을 따라 보이드가 발생하게 되었고, 이에 따라 수분 등의 침투로 소자의 특성에 악영향을 미치게 되었다.As described above, in the conventional method of forming metal wirings, voids are generated along sidewalls of the metal wirings when the protective film is formed due to a decrease in the spacer margin between the table top and the metal wirings formed on the metal wirings. The characteristics of the device are adversely affected.
따라서, 본 발명은 마스크층의 침식(erosion) 공정을 통해 노출된 테이블 탑을 과도 식각과 동시에 또는 주식각후 과도 식각 전에 제거하여 후속 공정인 보호막 형성 공정시에 발생되는 보이드를 방지하므로서, 소자의 신뢰성을 향상시킬 수 있는 반도체 소자의 금속배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention removes the table top exposed through the erosion process of the mask layer at the same time as the over etching or before the post etching after the stock etching to prevent voids generated during the subsequent protective film forming process, thereby improving reliability of the device. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wirings in a semiconductor device capable of improving the amount of metal.
상기한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 금속배선 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판에 층간 절연막을 형성한 후, 장벽 금속층, 금속층 및 반사 방지층을 순차적으로 형성하는 단계; 제 1 마스크층을 이용한 주식각 공정을 통해 상기 반사 방지층 및 상기 금속층을 순차적으로 식각하고, 이로 인하여 상기 금속층 양측벽에 폴리머가 형성되고, 동시에 상기 폴리머상에 테이블 탑이 발생되는 단계; 상기 테이블 탑을 노출시키기 위해, 상기 제 1 마스크층의 일부분을 침식시켜 제 2 마스크층을 이루는 단계; 및 상기 제 2 마스크층을 이용한 과도 식각 공정을 통해 상기 테이블 탑 및 상기 장벽 금속층을 식각하여 금속배선을 형성하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to the present invention, a method for forming a metal wiring of a semiconductor device according to the present invention is to form an interlayer insulating film on a substrate on which various elements for forming a semiconductor device are formed, and then sequentially forming a barrier metal layer, a metal layer, and an antireflection layer. step; Sequentially etching the anti-reflection layer and the metal layer through a stock angle process using a first mask layer, thereby forming a polymer on both side walls of the metal layer and simultaneously generating a table top on the polymer; Eroding a portion of the first mask layer to form a second mask layer to expose the table top; And forming a metal wiring by etching the table top and the barrier metal layer through a transient etching process using the second mask layer.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 3(a) 내지 도 3(c)는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도로서, 마스크층의 침식 공정이 이용되어 테이블 탑이 제거되는 과정이 도시된다.3 (a) to 3 (c) are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention, and a process of removing a table top by using an erosion process of a mask layer is illustrated.
도 3(a)를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 기판(31)에 층간 절연막(32)을 형성한 후, 타이타늄/타이타늄 나이트라이드의 이층 구조인 장벽 금속층(33), 금속배선용 알루미늄층(34) 및 타이타늄 나이트라이드를 사용한 반사 방지층(35)을 순차적으로 형성한다. 포토레지스터 패턴을 제 1 마스크층(36A)으로 이용한 주식각 공정을 통해 반사 방지층(35) 및 금속배선용 알루미늄층(34)을 순차적으로 식각하고, 이로 인하여 금속배선용 알루미늄층(34) 양측벽에 폴리머(polymer; 37)가 형성되며, 또한 상기 폴리머(37)상에 테이블 탑(C; 타이타늄 나이트라이드의 돌출)이 발생된다.Referring to FIG. 3A, an interlayer insulating film 32 is formed on a substrate 31 on which various elements for forming a semiconductor device are formed, and then a barrier metal layer 33 and a metal, which are two-layer structures of titanium / titanium nitride, are formed. The wiring aluminum layer 34 and the antireflection layer 35 using titanium nitride are sequentially formed. The anti-reflective layer 35 and the metallization aluminum layer 34 are sequentially etched through a stock angle process using the photoresist pattern as the first mask layer 36A, thereby polymerizing both sides of the metallization aluminum layer 34. A polymer 37 is formed, and a table top C (protrusion of titanium nitride) is generated on the polymer 37.
도 3(b)를 참조하면, 상기 테이블 탑(C) 부분을 노출시키기 위해 제 1 마스크층(36A)을 침식시켜 제 2 마스크층(36B)을 이룬 후, 상기 제 2 마스크층(36B)을 이용한 과도 식각 공정을 통해 반사 방지층(35), 폴리머(37) 및 장벽 금속층(33)을 순차적으로 식각하고, 이로 인하여 테이블 탑(C)이 제거되어 금속배선이 형성된다.Referring to FIG. 3B, the second mask layer 36B is formed by eroding the first mask layer 36A to expose a portion of the table top C, and then forming the second mask layer 36B. The anti-reflective layer 35, the polymer 37, and the barrier metal layer 33 are sequentially etched through the transient etching process, thereby removing the table top C, thereby forming metal wiring.
상기에서, 반도체 소자의 금속배선을 형성하기 위해서는 Cl2/BCl3/N2 가스를 이용하여 금속배선용 알루미늄층(34)을 식각하는 주식각 공정과, 금속 잔류물 및 브릿지를 제거하기 위한 과도 식각 공정을 실시한다. 이때, 반사 방지층(35)은 물리적인 식각이, 금속배선용 알루미늄층(34)은 화학적인 식각이 진행되며, 이로 인하여 테이블 탑(C)이 발생되고, 제 1 마스크층(36A)이 소정의 두께가 침식되어 금속배선을 수직하게 형성시키는 폴리머(37)가 형성된다. 폴리머(37)상에 형성된 테이블 탑(C)은 제 1 마스크층(36A)의 침식시에 노출되기 때문에 과도 식각 공정시 물리적으로 제거한다.In the above, in order to form the metal wiring of the semiconductor device, the stock angle process of etching the aluminum layer 34 for metal wiring using Cl 2 / BCl 3 / N 2 gas, and the transient etching for removing metal residues and bridges Carry out the process. At this time, the anti-reflection layer 35 is physically etched, the metallization aluminum layer 34 is chemically etched, thereby causing a table top C, and the first mask layer 36A having a predetermined thickness. Is eroded to form a polymer 37 which vertically forms the metallization. Since the table top C formed on the polymer 37 is exposed during the erosion of the first mask layer 36A, the table top C is physically removed during the excessive etching process.
또한, 주식각 및 과도 식각 공정은 TCP 또는 RIE 타입의 챔버(chamber)를 이용하여 실시되는데, TCP 타입의 챔버를 이용하는 경우, 주식각 공정은 BCl3가 20 내지 80 SCCM, Cl2가 40 내지 120 SCCM인 BCl3/Cl2 가스 분위기하에서 200 내지 400W의 소오스 전력(Source Power), 100 내지 250W의 바이어스 전력(Bias Power)으로 실시된다. 과도 식각 공정은 주식각 공정과 동일한 가스 분위기하에서 100 내지 250W의 소오스 전력, 80 내지 150W의 바이어스 전력으로 실시된다. 한편, 제 1 마스크층(36A)의 침식 공정은 10 내지 50 SCCM의 O2 가스 분위기하에서 50 내지 100W의 소오스 전력, 10 내지 80W의 바이어스 전력에서 실시된다. 상기 침식 공정은 과도 식각 공정시에 동시에 실시될 수 있다.In addition, the stock angle and the transient etching process is carried out using a chamber of the TCP or RIE type, when using the chamber of the TCP type, the stock angle process is 20 to 80 SCCM of BCl 3 , 40 to 120 of Cl 2 In a BCl 3 / Cl 2 gas atmosphere, which is SCCM, a source power of 200 to 400 W and a bias power of 100 to 250 W are performed. The transient etching process is performed with a source power of 100 to 250 W and a bias power of 80 to 150 W in the same gas atmosphere as the stock etching process. On the other hand, the erosion process of the first mask layer 36A is performed at a source power of 50 to 100 W and a bias power of 10 to 80 W in an O 2 gas atmosphere of 10 to 50 SCCM. The erosion process may be performed simultaneously during the transient etching process.
도 3(c)를 참조하면, 상기 금속배선 형성후, 고밀도 플라즈마 화학 기상 증착법을 통해 상기 전체 구조상에 산화막(38)을 형성하여 보호막으로 사용한다.Referring to FIG. 3 (c), after the metal wiring is formed, an oxide film 38 is formed on the entire structure through high density plasma chemical vapor deposition and used as a protective film.
상술한 바와 같이, 본 발명은 마스크층의 침식 공정을 통해 금속배선 상부에 형성된 테이블 탑을 노출시키고, 노출된 테이블 탑을 과도 식각 공정에서 제거하므로서, 후속 공정인 고밀도 플라즈마 화학 기상 증착법에 의한 보호막 형성시에 발생되는 보이드를 제거하여 대기중의 수분 등의 침투를 방지할 수 있어 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention exposes the table top formed on the upper portion of the metal wiring through the erosion process of the mask layer, and removes the exposed table top in the transient etching process, thereby forming a protective film by a high density plasma chemical vapor deposition method which is a subsequent process. By removing voids generated at the time, it is possible to prevent penetration of moisture and the like in the air, thereby improving the reliability of the device.
도 1 및 도 2는 종래의 제 1 및 제 2 실시예에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도.1 and 2 are cross-sectional views for explaining a method for forming metal wirings of a semiconductor device according to the first and second embodiments of the prior art.
도 3(a) 내지 도 3(c)는 본 발명에 따른 반도체 소자의 금속배선 형성 방법을 설명하기 위한 단면도.3 (a) to 3 (c) are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
11, 21 및 31 : 반도체 기판 12, 22 및 32 : 층간 절연막11, 21, and 31: semiconductor substrates 12, 22, and 32: interlayer insulating film
13, 23 및 33 : 장벽 금속층 14, 24 및 34 : 알루미늄층13, 23 and 33: barrier metal layers 14, 24 and 34: aluminum layers
15, 25 및 35 : 반사 방지층 16, 26 및 38: 산화막15, 25, and 35: antireflection layers 16, 26, and 38: oxide film
17 : 질화막 36A 및 36B : 마스크층17 nitride films 36A and 36B mask layer
37 : 폴리머 A 및 B : 보이드(void)37 polymer A and B void
C : 테이블 탑(Table Top)C: Table Top
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980041671A KR100549333B1 (en) | 1998-10-02 | 1998-10-02 | Metal wiring formation method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980041671A KR100549333B1 (en) | 1998-10-02 | 1998-10-02 | Metal wiring formation method of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000024881A KR20000024881A (en) | 2000-05-06 |
| KR100549333B1 true KR100549333B1 (en) | 2006-04-06 |
Family
ID=19553118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980041671A KR100549333B1 (en) | 1998-10-02 | 1998-10-02 | Metal wiring formation method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100549333B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030011478A (en) * | 2001-08-03 | 2003-02-11 | (주)온달 | Method for lifecare membership service on internet website |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122567A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Fabrication of semiconductor device |
| KR960005847A (en) * | 1994-07-08 | 1996-02-23 | 김주용 | Method of forming insulating film between metal wires |
| KR970003630A (en) * | 1995-06-28 | 1997-01-28 | 김주용 | Method of manufacturing insulating film between metal wirings of semiconductor device |
| KR970003488A (en) * | 1995-06-26 | 1997-01-28 | 김주용 | Metal wiring formation method of semiconductor device |
| KR970052400A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Metal film formation method of semiconductor device |
-
1998
- 1998-10-02 KR KR1019980041671A patent/KR100549333B1/en not_active IP Right Cessation
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07122567A (en) * | 1993-10-21 | 1995-05-12 | Nec Corp | Fabrication of semiconductor device |
| KR960005847A (en) * | 1994-07-08 | 1996-02-23 | 김주용 | Method of forming insulating film between metal wires |
| KR970003488A (en) * | 1995-06-26 | 1997-01-28 | 김주용 | Metal wiring formation method of semiconductor device |
| KR970003630A (en) * | 1995-06-28 | 1997-01-28 | 김주용 | Method of manufacturing insulating film between metal wirings of semiconductor device |
| KR970052400A (en) * | 1995-12-27 | 1997-07-29 | 김광호 | Metal film formation method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000024881A (en) | 2000-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7482279B2 (en) | Method for fabricating semiconductor device using ArF photolithography capable of protecting tapered profile of hard mask | |
| US6500767B2 (en) | Method of etching semiconductor metallic layer | |
| KR100239442B1 (en) | Conduction plug forming method in contact hole | |
| KR100493486B1 (en) | Method for etching a conductive layer | |
| KR100581244B1 (en) | Fabricating method of semiconductor device | |
| KR100549333B1 (en) | Metal wiring formation method of semiconductor device | |
| JP3238363B2 (en) | Method for forming metal wiring of semiconductor device | |
| US7148150B2 (en) | Method of forming metal line layer in semiconductor device | |
| KR100382312B1 (en) | Method for forming a conductor pattern of semiconductor device | |
| KR100326262B1 (en) | Method for forming semiconductor device | |
| KR0166508B1 (en) | Metal wiring forming method of semiconductor device | |
| KR100395775B1 (en) | Method for forming a metal line of semiconductor device | |
| KR100562312B1 (en) | Fabrication method of semiconductor device | |
| KR100289656B1 (en) | Method of manufacturing semiconductor device | |
| KR101181271B1 (en) | Method for Forming Metal Line of Semiconductor Device | |
| KR100412145B1 (en) | A method for forming via hole of semiconductor device | |
| KR20000003119A (en) | Method for forming metal wiring of semiconductor device | |
| KR100291189B1 (en) | Semiconductor device manufacturing method | |
| KR100831572B1 (en) | Method of forming metal line for semiconductor device | |
| KR100777365B1 (en) | Method for forming a metal line | |
| KR100548564B1 (en) | method for forming bit line | |
| KR20050035359A (en) | Method of manufacturing semiconductor device | |
| KR20030052270A (en) | Method for manufacturing metal line of semiconductor device | |
| KR20040004909A (en) | Method for forming electric wiring in semiconductor device | |
| KR20060074498A (en) | Method for removing hardening residue of the semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20101224 Year of fee payment: 6 |
|
| LAPS | Lapse due to unpaid annual fee |