KR100548564B1 - method for forming bit line - Google Patents

method for forming bit line Download PDF

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KR100548564B1
KR100548564B1 KR1020030046343A KR20030046343A KR100548564B1 KR 100548564 B1 KR100548564 B1 KR 100548564B1 KR 1020030046343 A KR1020030046343 A KR 1020030046343A KR 20030046343 A KR20030046343 A KR 20030046343A KR 100548564 B1 KR100548564 B1 KR 100548564B1
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film
etching
bit line
silicon nitride
forming
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KR1020030046343A
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KR20050006504A (en
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남기원
이주희
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines

Abstract

본 발명은 비트 라인용 금속막의 식각 공정에서 식각 공정에 따른 손실을 최소화하여 이 후의 스토리지노드 콘택 식각 공정에서 공정 마진을 확보할 수 있는 비트 라인 형성 방법에 관해 개시한 것으로서, 반도체 기판 상에 텅스텐 막, 실리콘 질화막 및 SiON 막을 차례로 형성하는 단계와, SiON 막 위에 금속배선 영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 기판 전면에 플라즈마 상태의 SF6 및 N2 가스를 공급하여 SiON 막을 1차 식각하는 단계와, 감광막 패턴을 제거하는 단계와, 1차 식각 후 잔류된 SiON 막 및 실리콘 질화막을 마스크로 하고 결과물 전면에 플라즈마 상태의 Cl2 및 NF3 가스를 공급하여 텅스텐 막을 2차 식각하여 금속배선을 형성하는 단계를 포함한다.The present invention discloses a method for forming a bit line which minimizes the loss caused by the etching process in the etching process of the metal film for the bit line and secures the process margin in the subsequent storage node contact etching process. Forming a silicon nitride film and a SiON film sequentially; forming a photoresist pattern covering a metal wiring region on the SiON film; and supplying SF 6 and N 2 gases in a plasma state to the entire surface of the substrate using the photoresist pattern as a mask; First etching the film, removing the photoresist pattern, and using the SiON film and silicon nitride film remaining after the first etching as a mask, and supplying Cl 2 and NF 3 gas in a plasma state to the entire surface of the resultant to make the tungsten film secondary. Etching to form a metal wiring.

Description

비트 라인 형성 방법{method for forming bit line}Method for forming bit line

도 1a 내지 도 1c는 종래 기술에 따른 비트 라인 형성 방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming a bit line according to the related art.

도 2a 내지 도 2c는 본 발명에 따른 비트 라인 형성 방법을 설명하기 위한 공정단면도.2A to 2C are cross-sectional views illustrating a method of forming a bit line according to the present invention.

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 보다 구체적으로는 비트 라인용 금속막의 식각 공정에서 식각 공정에 따른 손실을 최소화하여 이 후의 스토리지노드 콘택 식각 공정에서 공정 마진을 확보할 수 있는 비트 라인 형성 방법에 관한 것이다.
반도체 소자가 고집적화됨에 따라, 콘택 크기 또한 작아지게 된다. 따라서, 콘택 오픈을 위하여 산화막 대 질화막 간의 고선택비를 이용하였으나, 현재 이러한 고선택비를 이용한 방법은 그 한계에 이르게 되어 낫 오픈(not open)을 유발하게 되었다.
따라서, 이러한 고선택비를 이용하는 방법 대신 비트 라인의 하드마스크 두께를 증가시키는 방안이 채택되었다. 그러나, 상기 하드마스크 두께 증가는 비트 라인 식각 시 감광막 마진을 감소시켜 비트 라인의 탑부분이 손실(loss)됨으로써, 이 후의 스토리지노드 콘택 형성 시 콘택 마진을 감소시키게 된다.
도 1a 내지 도 1c는 종래 기술에 따른 비트 라인 형성 방법을 설명하기 위한 공정단면도이다.
종래 기술에 따른 비트 라인 형성 방법은, 도 1a에 도시된 바와 같이, 반도체기판(1) 상에 Ti/TiN 막(2), 텅스텐 막(3) 및 하드마스크용 실리콘 질화막(4) 및 반사방지막용 SiON 막(5)을 차례로 형성한다. 이어, 상기 SiON 막(5) 위에 감광막을 도포하고 노광 및 현상하여 비트 라인영역(미도시)을 덮는 감광막 패턴(9)을 형성한다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to form a bit line that can secure a process margin in a subsequent storage node contact etching process by minimizing a loss due to an etching process in an etching process of a metal film for bit lines. It is about a method.
As semiconductor devices become more integrated, contact sizes also become smaller. Therefore, the high selectivity ratio between the oxide film and the nitride film was used for the contact open. However, the method using the high selectivity ratio has reached its limit and caused not open.
Therefore, a method of increasing the hard mask thickness of the bit line has been adopted instead of the method using such a high selectivity ratio. However, the increase of the hard mask thickness reduces the photoresist margin when the bit line is etched, so that the top portion of the bit line is lost, thereby reducing the contact margin when forming a subsequent storage node contact.
1A to 1C are cross-sectional views illustrating a method of forming a bit line according to the related art.
The bit line forming method according to the related art is, as shown in Fig. 1A, a Ti / TiN film 2, a tungsten film 3, a silicon nitride film 4 for hard mask and an antireflection film on the semiconductor substrate 1; The SiON film 5 for is formed in order. Subsequently, a photoresist film is coated on the SiON film 5 and exposed and developed to form a photoresist pattern 9 covering a bit line region (not shown).

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그런 다음, 도 1b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 하여 상기 SiON 막 및 실리콘 질화막을 1차 건식 식각하고 나서, 상기 감광막 패턴을 제거 및 상기 결과물에 세정 공정을 진행한다. 이때, 상기 1차 건식 식각 공정에서, 식각 가스로는 플라즈마 상태의 SF6 및 N2 가스를 이용한다. 또한, 식각 챔버 내부의 압력을 9 mTorr로, 탑 파워(top po Wer)를 636 Watt로, 바텀 파워(bottom power)를 45 Watt로 각각 셋팅한다.Next, as shown in FIG. 1B, the SiON film and the silicon nitride film are first dry-etched using the photoresist pattern as a mask, and then the photoresist pattern is removed and the resultant is cleaned. At this time, in the first dry etching process, SF 6 and N 2 gas in a plasma state is used as an etching gas. In addition, the pressure inside the etching chamber is set to 9 mTorr, top po (Wer po Wer) to 636 Watt, bottom power (bottom power) to 45 Watt.

한편, 도 1b에서, 미설명된 도면부호 4a는 1차 건식 식각 공정 완료 후 잔류된 실리콘 질화막을, 도면부호 5a는 1차 식각 공정 완료 후 잔류된 SiON 막을 각각 나타낸 것이다.Meanwhile, in FIG. 1B, reference numeral 4a, which is not described, denotes a silicon nitride film remaining after completion of the first dry etching process, and reference numeral 5a denotes a SiON film remaining after completion of the first etching process.

이 후, 도 1c에 도시된 바와 같이, 상기 잔류된 SiON 막(5a) 및 실리콘 질화막(4a)를 식각베리어로 하여 상기 텅스텐 막 및 Ti/TiN 막을 2차 건식 식각하여 비트 라인(B1)을 형성한다. 이때, 상기 2차 건식 식각 공정에서, 식각 가스로는 1차 건식 식각 가스와 동일한 플라즈마 상태의 SF6 및 N2를 이용하며, 챔버 공정 조건은 1차 건식 식각 공정과 동일하게 셋팅한다. 또한, 상기 2차 건식 식각 공정에서, 반사방지막은 완전히 제거되고, 반사방지막 하부의 실리콘 질화막의 일정 두께가 제거된다.Thereafter, as illustrated in FIG. 1C, the tungsten film and the Ti / TiN film are secondarily dry-etched using the remaining SiON film 5a and the silicon nitride film 4a as etch barriers to form a bit line B1. do. In this case, in the secondary dry etching process, SF 6 and N 2 in the same plasma state as the primary dry etching gas are used as the etching gas, and the chamber process conditions are set in the same manner as the primary dry etching process. In addition, in the second dry etching process, the antireflection film is completely removed, and a predetermined thickness of the silicon nitride film under the antireflection film is removed.

도 1c에서, 미설명된 도면부호 2a는 2차 식각 공정 완료 후 잔류된 Ti/TiN 막을, 도면부호 3a는 2차 식각 공정 후 잔류된 텅스텐 막을 각각 나타낸 것이다. 그리고, 미설명된 도면부호 4a1은 2차 식각 공정 후 잔류된 실리콘 질화막을 나타낸 것이다. In FIG. 1C, reference numeral 2a, which is not described, denotes a Ti / TiN film remaining after completion of the secondary etching process, and reference numeral 3a denotes a tungsten film, which remains after the secondary etching process. Unexplained reference numeral 4a1 represents a silicon nitride film remaining after the secondary etching process.

그러나, 종래의 기술에서는, 비트 라인 식각 공정에서, SF6 가스의 경우, 텅스텐 막뿐만 아니라 SiON 막 및 실리콘 질화막의 식각률이 매우 높은 특성이 있다.
따라서, SiON 막 및 실리콘 질화막의 1차 식각 공정 → 감광막 패턴 제거 및 세정 공정 → 텅스텐 막 및 Ti/TiN 막의 2차 식각 공정을 차례로 진행함으로써, 상기 SF6 가스에 의해 SiON 막과 실리콘 질화막이 계속적으로 손실되며, 최종의 2차 식각 공정이 완료되면 SiON 막은 완전히 제거되고 상기 실리콘 질화막도 상당 두께가 손실된다. 이로써, 후속의 스토리지노드 콘택 형성 시, 콘택 마진을 감소시키는 문제점이 있었다.
따라서, 상기 문제점을 해결하고자, 본 발명의 목적은 비트 라인 식각 공정에서 SiON 막과 실리콘 질화막의 손실을 최소화함으로써, 후속의 스토리지노드 콘택 형성 시, 콘택 마진을 확보할 수 있는 비트 라인 형성 방법을 제공하려는 것이다.However, in the conventional art, in the bit line etching process, in the case of SF 6 gas, not only the tungsten film but also the etching rate of the SiON film and the silicon nitride film is very high.
Accordingly, the SiON film and the silicon nitride film are continuously formed by the SF 6 gas by sequentially performing the first etching process of the SiON film and the silicon nitride film, followed by the photoresist pattern removing and cleaning process, and the second etching process of the tungsten film and the Ti / TiN film. When the final secondary etching process is completed, the SiON film is completely removed and the silicon nitride film also loses a considerable thickness. As a result, there is a problem of reducing contact margin when forming subsequent storage node contacts.
Accordingly, an object of the present invention is to minimize the loss of the SiON film and the silicon nitride film in the bit line etching process, thereby providing a bit line forming method that can secure a contact margin when forming subsequent storage node contacts I will.

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상기 목적을 달성하고자, 본 발명에 따른 비트 라인 형성 방법은 반도체 기판 상에 텅스텐 막, 실리콘 질화막 및 SiON 막을 차례로 형성하는 단계와, SiON 막 위에 금속배선 영역을 덮는 감광막 패턴을 형성하는 단계와, 감광막 패턴을 마스크로 하고 기판 전면에 플라즈마 상태의 SF6 및 N2 가스를 공급하여 SiON 막을 1차 식각하는 단계와, 감광막 패턴을 제거하는 단계와, 1차 식각 후 잔류된 SiON 막 및 실리콘 질화막을 마스크로 하고 결과물 전면에 플라즈마 상태의 Cl2 및 NF3 가스를 공급하여 텅스텐 막을 2차 식각하여 금속배선을 형성하는 단계를 포함한 것을 특징으로 한다.
이때, 상기 1차 식각 공정은 식각 챔버 내부의 압력을 9 mTorr로, 탑 파워를 636와트로, 바텀 파워를 45와트로 각각 셋팅하는 것이 바람직하다.
또한, 상기 2차 식각 공정은 식각 챔버 내부의 압력을 4 mTorr로, 탑 파워를 500와트로, 바텀 파워를 60와트로 각각 셋팅하는 것이 바람직하다.In order to achieve the above object, the bit line forming method according to the present invention comprises the steps of sequentially forming a tungsten film, a silicon nitride film and a SiON film on a semiconductor substrate, forming a photosensitive film pattern covering a metal wiring region on the SiON film, and First etching the SiON film by supplying SF 6 and N 2 gas in a plasma state to the entire surface of the substrate as a mask, removing the photoresist pattern, masking the remaining SiON film and silicon nitride film after the first etching And supplying Cl 2 and NF 3 gas in a plasma state to the entire surface of the resultant to form a metal wiring by secondary etching the tungsten film.
In this case, in the first etching process, the pressure inside the etching chamber is set to 9 mTorr, the top power to 636 watts, and the bottom power to 45 watts, respectively.
In the second etching process, the pressure inside the etching chamber is set to 4 mTorr, the top power is set to 500 watts, and the bottom power is set to 60 watts, respectively.

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(실시예)(Example)

도 2a 내지 도 2c는 본 발명에 따른 비트 라인 형성 방법을 설명하기 위한 공정단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a bit line according to the present invention.

본 발명에 따른 비트 라인 형성 방법은, 도 2a에 도시된 바와 같이, 반도체기판(10) 상에 Ti/TiN 막(11), 텅스텐 막(12), 실리콘 질화막(13) 및 SiON 막(14)을 차례로 형성한다. 이때, 상기 Ti/TiN 막(11)에서, 상기 Ti막은 기판(10)과 텅스텐 막(12) 간의 접착력을 향상시키기 위한 접착층으로서의 역할을 하며, 상기 TiN 막은 확산방지막으로서의 역할을 수행한다. 또한, 텅스텐 막(12)은 전기 신호를 전달하는 도전층의 역할을 한다. 한편, 상기 실리콘 질화막(13)은 하드마스크로서, 2000∼3000Å두께로 형성하고, 상기 SiON 막(14)은 반사방지막으로서, 600Å두께로 형성한다. 바람직하게는, 상기 실리콘 질화막(13)과 SiON 막(14)의 합한 두께는 2600Å 이하로 형성한다.In the bit line forming method according to the present invention, as shown in FIG. 2A, a Ti / TiN film 11, a tungsten film 12, a silicon nitride film 13, and a SiON film 14 are formed on a semiconductor substrate 10. Form in turn. In this case, in the Ti / TiN film 11, the Ti film serves as an adhesive layer for improving adhesion between the substrate 10 and the tungsten film 12, and the TiN film serves as a diffusion barrier film. In addition, the tungsten film 12 serves as a conductive layer for transmitting an electrical signal. On the other hand, the silicon nitride film 13 is formed as a hard mask with a thickness of 2000 to 3000 mm 3, and the SiON film 14 is formed with a thickness of 600 mm as an antireflection film. Preferably, the combined thickness of the silicon nitride film 13 and SiON film 14 is 2600 kPa or less.

이어, 상기 SiON 막(14) 위에 감광막을 도포하고 노광 및 현상하여 비트 라인영역(미도시)을 덮는 감광막 패턴(19)을 형성한다.
그런 다음, 도 2b에 도시된 바와 같이, 상기 감광막 패턴을 마스크로 이용하여 SiON 막 및 실리콘 질화막을 1차 식각하고 나서, 상기 감광막 패턴을 제거하고 상기 결과물에 세정 공정을 실시한다. 이때, 상기 1차 식각 공정(15)은 식각 가스로서 플라즈마 상태의 SF6 및 N2 가스를 이용하며, 상기 1차 식각 공정이 진행되는 식각 챔버 내부의 압력을 9 mTorr로, 탑 파워를 636와트로, 바텀 파워를 45와트로 각각 셋팅한다.
한편, 도 2b에서, 미설명된 도면부호 13a는 1차 식각 공정 완료 후 잔류된 실리콘 질화막을, 도면부호 14a는 1차 식각 공정 완료 후 잔류된 SiON 막을 각각 나타낸 것이다.
이 후, 도 2c에 도시된 바와 같이, 상기 잔류된 SiON 막(14a) 및 실리콘 질화막(13a)을 마스크로 하여 텅스텐 막 및 Ti/TiN 막을 2차 건식 식각(16)하여 비트 라인(B2)을 형성한다. 이때, 상기 2차 건식 식각 공정(16)은 식각 가스로서 플라즈마 상태의 Cl2 및 NF3 가스를 이용하며, 식각 챔버 내부의 압력을 4 mTorr로, 탑 파워를 300∼600와트로, 바텀 파워를 60와트로 각각 셋팅한다. 여기서, 상기 탑 파워는 바람직하게는 500와트로 셋팅한다.
한편, 상기 SF6 대 Cl2 가스 비율은 10:1∼5:1 로 유지하고, 이들 가스의 총유량은 130 sccm 이하로 유지한다.
상기 2차 건식 식각(16) 공정에서, 기존의 SF6 가스 대신 Cl2 가스를 사용함으로써, SiON 막과 실리콘 질화막의 식각율이 낮아진다. 구체적으로, 기존과 대비하여 실리콘 질화막 두께가 200∼300Å 상향된다. 또한, 탑 파워를 기존의 636와트에서 500와트로 낮춤으로써, 물리적 식각을 방지한다.
도 2에서, 미설명된 도면부호 14a1,12a 및 11a는 2차 식각 공정이 완료된 후 기판에 잔류된 실리콘 질화막, 텅스텐 막, Ti/TiN 막을 각각 나타낸 것이다.
한편, 본 발명의 비트 라인 형성 공정은 일반적인 RIE(Reactive Ion Etching) 타입의 식각 장비 또는 MERIE(Magnetically Enhanced Reactive Ion Etching) 등 모든 플라즈마를 이용하는 식각 장비 내에서 진행된다.
본 발명에 따르면, Ti/TiN 막, 텅스텐 막, 실리콘 질화막(하드마스크) 및 SiON 막(반사방지막)의 적층 구조를 가진 비트 라인을 식각할 경우, 먼저 플라즈마 상태의 SF6 및 N2 가스를 이용하여 SiON 막과 실리콘 질화막을 식각하고 나서, SiON 막 및 실리콘 질화막의 식각률이 낮은 플라즈마 상태의 NF3 및 Cl2 가스를 이용하여 텅스텐 막 및 Ti/TiN 막을 식각함으로써, 상기 텅스텐 막 식각 공정 시 식각되는 실리콘 질화막의 손실을 최소화한다. 따라서, 이 후의 스토리지노드 콘택 공정 시, 콘택 마진을 확보 가능하다.Subsequently, a photoresist film is coated on the SiON film 14, and the photoresist film is exposed and developed to form a photoresist pattern 19 covering a bit line region (not shown).
Next, as shown in FIG. 2B, the SiON film and the silicon nitride film are first etched using the photoresist pattern as a mask, and then the photoresist pattern is removed and the resultant is subjected to a cleaning process. In this case, the primary etching process 15 uses SF 6 and N 2 gas in a plasma state as an etching gas, the pressure inside the etching chamber in which the primary etching process is performed is 9 mTorr, and the top power is 636 watts. Set the bottom power to 45 watts each.
In FIG. 2B, reference numeral 13a, which is not described, indicates a silicon nitride film remaining after the completion of the primary etching process, and reference numeral 14a indicates a SiON film that remains after the completion of the primary etching process.
After that, as shown in FIG. 2C, the tungsten film and the Ti / TiN film are subjected to secondary dry etching 16 using the remaining SiON film 14a and the silicon nitride film 13a as a mask to form the bit line B2. Form. In this case, the secondary dry etching process 16 uses Cl 2 and NF 3 gas in a plasma state as an etching gas, the pressure inside the etching chamber is 4 mTorr, the top power is 300 to 600 watts, and the bottom power is Set to 60 watts each. Here, the top power is preferably set to 500 watts.
Meanwhile, the SF 6 to Cl 2 gas ratio is maintained at 10: 1 to 5: 1, and the total flow rate of these gases is maintained at 130 sccm or less.
In the secondary dry etching 16 process, by using Cl 2 gas instead of the conventional SF 6 gas, the etching rate of the SiON film and the silicon nitride film is lowered. Specifically, compared with the conventional silicon nitride film thickness is raised 200 ~ 300Å. In addition, by lowering the top power from the existing 636 watts to 500 watts, physical etching is prevented.
In FIG. 2, reference numerals 14a1, 12a, and 11a, which are not described, represent silicon nitride films, tungsten films, and Ti / TiN films remaining on the substrate after the secondary etching process is completed, respectively.
Meanwhile, the bit line forming process of the present invention is performed in an etching apparatus using all plasmas such as a general reactive ion etching (RIE) type etching equipment or a magnetically enhanced reactive ion etching (MERIE).
According to the present invention, when etching a bit line having a stacked structure of a Ti / TiN film, a tungsten film, a silicon nitride film (hard mask) and a SiON film (anti-reflective film), SF 6 and N 2 gas in a plasma state are first used. Etching the SiON film and the silicon nitride film, and then etching the tungsten film and the Ti / TiN film using NF 3 and Cl 2 gas in the plasma state with low etching rates of the SiON film and the silicon nitride film, thereby etching during the tungsten film etching process. Minimize the loss of silicon nitride film. Therefore, in the subsequent storage node contact process, a contact margin can be secured.

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이상에서 설명한 바와 같이, 본 발명은 반사방지막 및 하드마스크를 베리어로 하고 텅스텐 막을 식각하여 비트 라인을 형성할 경우, 식각 가스로서 반사방지막 및 하드마스크의 식각율이 낮은 플라즈마 상태의 Cl2 및 NF3를 이용하고 탑 파워를 기존과 대비하여 감소시킴으로써, 식각 후 잔존하는 하드마스크가 200∼300Å 두께 상향된다.
따라서, 본 발명은 추가적인 하드마스크의 두께 증가없이 비트 라인 식각 후 하드마스크가 일정 두께로 잔존함으로써, 이 후의 스토리지노드 콘택 식각 공정에서 공정 마진이 증가되는 이점이 있다.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다. As described above, in the present invention, when the anti-reflection film and the hard mask are used as a barrier and the tungsten film is etched to form a bit line, the present invention provides Cl 2 and NF 3 in a plasma state where the etch rate of the anti-reflection film and the hard mask is low as an etching gas. By using and reducing the top power as compared to the existing, the remaining hard mask after etching up 200 ~ 300Å thickness.
Therefore, the present invention has the advantage that the hard mask remains after the bit line etching to a certain thickness without increasing the thickness of the additional hard mask, thereby increasing the process margin in the subsequent storage node contact etching process.
In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

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Claims (4)

하기 단계를 포함한 것을 특징으로 하는 비트 라인 형성 방법:A bit line forming method comprising the following steps: 반도체 기판 상에 텅스텐 막, 실리콘 질화막 및 SiON 막을 차례로 형성하는 단계와,Sequentially forming a tungsten film, a silicon nitride film and a SiON film on a semiconductor substrate, 상기 SiON 막 위에 금속배선 영역을 덮는 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern on the SiON film to cover the metallization region; 상기 감광막 패턴을 마스크로 하고 상기 기판 전면에 플라즈마 상태의 SF6 및 N2 가스를 공급하여 상기 SiON 막을 1차 식각하는 단계와,First etching the SiON film by supplying SF 6 and N 2 gas in a plasma state to the entire surface of the substrate using the photoresist pattern as a mask; 상기 감광막 패턴을 제거하는 단계와,Removing the photoresist pattern; 상기 1차 식각 후 잔류된 SiON 막 및 실리콘 질화막을 마스크로 하고 상기 결과물 전면에 플라즈마 상태의 Cl2 및 NF3 가스를 공급하여 텅스텐 막을 2차 식각하여 금속배선을 형성하는 단계; Forming a metal wire by second etching the tungsten film by supplying Cl 2 and NF 3 gas in a plasma state to the entire surface of the resultant with the SiON film and silicon nitride film remaining after the first etching; 상기 2차 식각 공정은 식각 챔버 내부의 압력을 4 mTorr로, 탑 파워를 500와트로, 바텀 파워를 60와트로 각각 셋팅함.In the secondary etching process, the pressure inside the etching chamber is set to 4 mTorr, the top power is set to 500 watts, and the bottom power is set to 60 watts, respectively. 상기 제 1항에 있어서, 상기 1차 식각 공정은 식각 챔버 내부의 압력을 9 mTorr로, 탑 파워를 636와트로, 바텀 파워를 45와트로 각각 셋팅하는 것을 특징으로 하는 비트 라인 형성 방법.The method of claim 1, wherein the first etching process sets the pressure in the etching chamber to 9 mTorr, the top power to 636 watts, and the bottom power to 45 watts, respectively. 삭제delete 제 1항에 있어서, 상기 SF6 대 Cl2 가스 비율은 10:1∼5:1 로 유지하고, 상기 SF6 및 Cl2 가스의 총유량은 130 sccm 이하로 유지하는 것을 특징으로 하는 비트 라인 형성 방법.The bit line formation of claim 1, wherein the SF 6 to Cl 2 gas ratio is maintained at 10: 1 to 5: 1, and the total flow rate of the SF 6 and Cl 2 gases is maintained at 130 sccm or less. Way.
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