JPS6119132A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6119132A
JPS6119132A JP13998784A JP13998784A JPS6119132A JP S6119132 A JPS6119132 A JP S6119132A JP 13998784 A JP13998784 A JP 13998784A JP 13998784 A JP13998784 A JP 13998784A JP S6119132 A JPS6119132 A JP S6119132A
Authority
JP
Japan
Prior art keywords
film
conductive film
etching
semiconductor device
resist pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13998784A
Other languages
Japanese (ja)
Inventor
Yasuhiro Ito
康浩 伊藤
Yukimasa Yoshida
幸正 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13998784A priority Critical patent/JPS6119132A/en
Publication of JPS6119132A publication Critical patent/JPS6119132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To restrain resist from deterioration and undercut by a method wherein an insulating film containing no oxygen is formed on another insulating film mainly comprising SiO2 and a conductive film deposited on the former insulating film is plasma-etched. CONSTITUTION:An SiO2 film 17 is formed on a semiconductor substrate 11 to deposit an Si3N4 film 18 on the film 17. Next a contact hole 19 passing through a source region 15 and a drain region 16 is opened by etching the films 18 and 17. Firstly after depositing an Al film 20 on overall surface, a resist pattern 21 is formed on the film 20. Secondly the film 20 is plasma-etched utilizing the pattern 21 as a mask. Thus the film 20 is patterned to be removed at the opening of pattern 21. Resultantly a wiring 21' connecting to the regions 15, 16 through the intermediary of the hole 19 is patterned. Through these procedures, the film 17 may be prevented from producing oxygen atoms while restraining the resist 21 from deterioration and undercut in case of plasma etching process by means of forming the film 18.

Description

【発明の詳細な説明】 [発明の技術分野] 本発明は半導体基板上の絶縁膜上に形成された金属膜を
プラズマエツチングにより加工する際に、下地絶縁膜の
酸素原子分離を防止できるようにした半導体装置の製造
方法に関するものである。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention provides a method for preventing the separation of oxygen atoms in a base insulating film when processing a metal film formed on an insulating film on a semiconductor substrate by plasma etching. The present invention relates to a method for manufacturing a semiconductor device.

[発明の技術的背景とその問題点〕 近年、半導体素子の高集積化に伴い、高度の微線加工技
術が要求されるようになり、エツチング方法としては従
来の等方的な湿式エツチングに代り、異方的なエツチン
グが可能であるプラズマエツチング法が広く用いられる
ようになった。また、多層配線も多く用いられ、その層
間絶縁膜としてCVD−8i 02 ヤPSG (!、
D/硅化カラス)など、主として、5i02が用いられ
、また、金属配線にはAβ(アルミニウム)が主に用い
られている。
[Technical background of the invention and its problems] In recent years, with the increasing integration of semiconductor devices, advanced micro-line processing technology has become required, and as an etching method, the conventional isotropic wet etching has been replaced. , plasma etching methods that enable anisotropic etching have come to be widely used. In addition, multilayer wiring is often used, and CVD-8i 02 YaPSG (!,
5i02 is mainly used, such as D/glass silicide), and Aβ (aluminum) is mainly used for metal wiring.

そこで、半導体装置の高集積化を図り、且つ、素子の高
信頼性を得るためには、SiO2膜上のAρ配線を制御
性良く加工形成できる技術が必要となる。
Therefore, in order to achieve high integration of a semiconductor device and to obtain high reliability of the device, a technique is required that can process and form the Aρ wiring on the SiO2 film with good controllability.

ところで、SiO2を主成分とする絶縁膜上の金属(こ
こではAQ>を制御性良く加工するためにプラズマエツ
チングを用いるが、下地絶縁膜に段差が生じる場合やエ
ツチングの均一性を考えると、通常、30〜50%程度
のオーバエツチングが必要である。しかし、オーバエツ
チング中には下地の5iO211がエツチングされるこ
とから、5102中の酸素原子が分離され、この分離さ
れた酸素原子により、レジストが著しく劣化(膜減り)
したり、あるいはAβにアンダーカットが生じて、寸法
の制御性が著しく低下してしまうと云う問題があった。
By the way, plasma etching is used to process the metal (here AQ) on an insulating film whose main component is SiO2 with good control, but it is usually , overetching of about 30 to 50% is required. However, since the underlying 5iO211 is etched during overetching, the oxygen atoms in 5102 are separated, and the separated oxygen atoms cause the resist to Significant deterioration (film reduction)
Otherwise, undercuts may occur in Aβ, resulting in a significant decrease in dimensional controllability.

[発明の目的] 本発明は上記の事情に鑑みて成されたもので、絶縁膜上
の金属膜を制御性良くプラズマエツチング加工できるよ
うにした半導体装置の製造方法を提供することを目的と
する。
[Object of the Invention] The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which a metal film on an insulating film can be plasma etched with good controllability. .

[発明の概要] 本発明は上記目的を達成するため、半導体基板に形成さ
れた絶縁膜の表面に導電性膜を堆積して後、該導電性膜
上にレジストパターンを形成し、これをマスクに前記導
電性膜をプラズマエツチングして該導電性膜をパターニ
ングする半導体装置の製造工程において、前記絶縁膜上
に酸素原子を含まない絶縁物質の膜を形成し、その表面
に導電性膜を堆積して後、該導電性膜上にレジストパタ
ーンを形成し、これをマスクに前記導電性膜をプラズマ
エツチングして該導電性膜をパターニングすることを特
徴ととする。かかる本発明によれば、オーバエツチング
時に発生するレジストの劣化及びアンダーカットが、エ
ツチングされたSiO2膜より発生する酸素原子の影響
によるものであると云う事実に基づき、SiO2を主成
分とする絶縁膜上に酸素を含まない絶縁膜、例えば、3
i3N4を形成した上で、その表面に、加工するべき導
電性膜を形成して、この導電性膜をレジストをマスクに
プラズマエツチングするようにしたので、これにより酸
素原子の発生を防止して、レジストの劣化とアンダーカ
ットの発生を抑制することができる。
[Summary of the Invention] In order to achieve the above object, the present invention deposits a conductive film on the surface of an insulating film formed on a semiconductor substrate, forms a resist pattern on the conductive film, and masks the resist pattern. In the manufacturing process of a semiconductor device in which the conductive film is patterned by plasma etching, a film of an insulating material that does not contain oxygen atoms is formed on the insulating film, and a conductive film is deposited on the surface of the film. After that, a resist pattern is formed on the conductive film, and the conductive film is patterned by plasma etching using the resist pattern as a mask. According to the present invention, based on the fact that resist deterioration and undercuts that occur during overetching are due to the influence of oxygen atoms generated from the etched SiO2 film, an insulating film mainly composed of SiO2 is used. An insulating film that does not contain oxygen on top, e.g.
After forming i3N4, a conductive film to be processed was formed on its surface, and this conductive film was plasma-etched using a resist as a mask.This prevented the generation of oxygen atoms. Deterioration of the resist and occurrence of undercuts can be suppressed.

[発明の実施例] 以下、本発明の実施例を図面を参照しながら説明する。[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

初めに本発明の製造工程で用いる配線用Aβ膜のエツチ
ングのためのプラズマエツチング装置の概要を第3図に
示す。すなわち、図に示す如くプラズマエツチング装置
は、容器40内に、対向する平板状の一対の電極41.
42を配設し、これらの電極のうち、下方の電極41を
アースし、上方の電極42は高周波電源43に接続する
とともに、電極41上にはウェハーを載置する。そして
、容器40内にエツチングガスを流通させ、電極41.
42間に、高周波電流を与えてプラズマを発生させ、エ
ツチングを行うようしたものである。
First, FIG. 3 shows an outline of a plasma etching apparatus for etching the Aβ film for wiring used in the manufacturing process of the present invention. That is, as shown in the figure, the plasma etching apparatus includes a pair of flat electrodes 41 .
Of these electrodes, the lower electrode 41 is grounded, the upper electrode 42 is connected to a high frequency power source 43, and a wafer is placed on the electrode 41. Then, etching gas is passed through the container 40, and the electrodes 41.
42, a high frequency current is applied to generate plasma to perform etching.

実施例 先ず、半導体基板11に、その素子領域を島状分離する
厚いフィールド酸化1112、素子領域の表面のゲート
絶縁膜13、ゲート絶縁膜13上のゲート電極14、そ
の他ソース、ドレイン領域15゜16などを形成し、次
にこの半導体基板11上に熱酸化により3000人のシ
リコン酸化m <s +02膜)17を層間絶縁膜とし
て形成し、次に、この81021117上にCVD法に
よりシリコン窒化膜(S i:+ N4 Ilり 18
を500人堆積した(第1図(a)図示)。つづいて、
全面にレジストを塗布し写真蝕剣法によりパターニング
して形成したレジストパターンを用いて5iaN+I1
18およびl1間絶縁![117をエツチングし、ソー
ス。
Embodiment First, a thick field oxide layer 1112 is formed on a semiconductor substrate 11 to isolate the device region into islands, a gate insulating film 13 on the surface of the device region, a gate electrode 14 on the gate insulating film 13, and other source and drain regions 15° and 16. Then, on this semiconductor substrate 11, a 3000 silicon oxide m < s +02 film) 17 is formed as an interlayer insulating film by thermal oxidation, and then a silicon nitride film ( S i: + N4 Ilri 18
500 people were deposited (as shown in Figure 1(a)). Continuing,
5iaN+I1 using a resist pattern formed by applying resist to the entire surface and patterning it by photo-etching method.
Insulation between 18 and l1! [Etches 117 and sources.

ドレイン領域に通ずるコンタクトホール19を開口した
。次に、全面にスパッタ法によりAn膜20を800O
A堆積した後、このAβ膜20上にポジ形フォトレジス
トを塗布して、これを写真蝕刻法によりパターニングし
、レジストパターン21を形成したく第1図(b)図示
)。
A contact hole 19 communicating with the drain region was opened. Next, an An film 20 of 800O was deposited on the entire surface by sputtering.
After the Aβ film 20 is deposited, a positive photoresist is coated on the Aβ film 20 and patterned by photolithography to form a resist pattern 21 (as shown in FIG. 1B).

次いで、レジストパターン21をマスクにAβ膜20を
プラズマエツチングした。ARR2O3エツチングには
第3図に示す如く、容器40内の対向する平板状の一対
の電極41.42のうち、アースされた下方の電極41
上に半導体基板11を載置し、そして、容器40内にエ
ツチングガスを流通させ、電極41.42間に、高周波
電流を与えてプラズマを発生させて、エツチングを行う
ようにした。エツチング条件は次の通りである。
Next, the Aβ film 20 was plasma etched using the resist pattern 21 as a mask. For ARR2O3 etching, as shown in FIG.
The semiconductor substrate 11 was placed thereon, etching gas was passed through the container 40, and a high frequency current was applied between the electrodes 41 and 42 to generate plasma to perform etching. The etching conditions are as follows.

プラズマエツチング装置に供給するエツチングガスはC
Cβ4を用い、このCCβ4の流量を2008CCmと
し、また、電極間に印加する高周波電力は500w、エ
ツチング圧力は350mt。
The etching gas supplied to the plasma etching equipment is C.
Cβ4 was used, the flow rate of CCβ4 was 2008 CCm, the high frequency power applied between the electrodes was 500 W, and the etching pressure was 350 mt.

rrとした。It was set as rr.

これにより、Aρ膜20はパターニングされ、レジスト
パターン21の開口部のへ2膜20は除去された。この
とき、A℃膜20WA厚のバラツキにより除去すべき部
分のへβ膜20が残るのを防ぐため、約30%のオーバ
エツチングを行った。
As a result, the Aρ film 20 was patterned, and the H2 film 20 at the opening of the resist pattern 21 was removed. At this time, in order to prevent the β film 20 from remaining in the portion to be removed due to variations in the thickness of the A° C. film 20WA, overetching was performed by about 30%.

その際、5iaN+l118の露出面も僅かにエツチン
グされた。これにより、コンタクトホール19を介して
ソース・ドレイン領域15.16に接続される配線22
がパターニング形成された(第1図(C)図示)。
At that time, the exposed surface of 5iaN+l118 was also slightly etched. As a result, the wiring 22 connected to the source/drain region 15.16 via the contact hole 19
was patterned (as shown in FIG. 1(C)).

尚、この時の八2のエツチングレートは700人/mi
nであり、オーバエツチング中の5i3N4WA17の
エツチング量はわずか200人であった。従って、50
0人の3i3N+膜17はオーバエツチング後において
も300人も残り、下地の8+02躾17はこの5ia
N41[118の保護されてエツチングされなかった。
Furthermore, the etching rate of 82 at this time was 700 people/mi.
n, and the etching amount of 5i3N4WA17 during overetching was only 200. Therefore, 50
The 3i3N+ film 17 of 0 remains as much as 300 after overetching, and the underlying 8+02 film 17 is this 5ia
N41[118 was protected and not etched.

比較例 先ず、半導体基板11に、その素子領域を島状分離する
厚いフィールド酸化膜12、素子領域の表面のゲート絶
縁膜13、ゲート絶縁膜13上のゲート電極14、その
他ソース、ドレイン領域15.16などを形成し、次に
この半導体基板11上に熱酸化により3500人のシリ
コン酸化膜(Si0211)17を層間絶縁膜として形
成した(第2図(a)図示)。つづいて、全面にレジス
トを塗布し写真蝕刻法によりパターニングして形成した
レジストパターンを用いて層間絶縁膜17をエツチング
し、ソース、ドレイン領域に通ずるコンタクトホール1
9を開口した。次に、全面にスパッタ法によりAfil
l#20を8000人堆積した後、このへβN1120
上にポジ形フォトレジストを塗布して、これを写真蝕刻
法によりパターニングし、レジストパターン21を形成
したく第2図(1))図示)。
Comparative Example First, on a semiconductor substrate 11, a thick field oxide film 12 for isolating device regions into islands, a gate insulating film 13 on the surface of the device region, a gate electrode 14 on the gate insulating film 13, and other source and drain regions 15, . A silicon oxide film (Si0211) 17 of 3,500 layers was then formed as an interlayer insulating film on this semiconductor substrate 11 by thermal oxidation (as shown in FIG. 2(a)). Subsequently, the interlayer insulating film 17 is etched using a resist pattern formed by applying a resist to the entire surface and patterning it by photolithography, and forming contact holes 1 leading to the source and drain regions.
9 was opened. Next, Afil is applied to the entire surface by sputtering.
After depositing 8000 l#20, βN1120 to this
A positive photoresist is applied thereon and patterned by photolithography to form a resist pattern 21 (as shown in FIG. 2(1)).

次いで、レジストパターン21をマスクにAλ膜20を
実施例と同様のプラズマエツチング装置を用いて同様な
条件でプラズマエツチングした。
Next, using the resist pattern 21 as a mask, the Aλ film 20 was plasma etched using the same plasma etching apparatus as in the example under the same conditions.

これにより、A2膜20はパターニングされ、レジスト
パターン21の開口部のAj211120は除去された
。これにより、コンタクトホール19を介してソース・
ドレイン領域15.16に接続される配線22をパター
ニング形成した。このとき、へβ膜20のバラツキによ
り除去すべき部分のA℃膜20が残るのを防ぐため、オ
ーバエツチングするが、その際、@間絶縁II(Si0
211)17の露出面も僅かにエツチングされた(第2
図(C)図示)。
As a result, the A2 film 20 was patterned, and the Aj211120 in the opening of the resist pattern 21 was removed. As a result, the source can be connected via the contact hole 19.
Wiring 22 connected to drain regions 15 and 16 was formed by patterning. At this time, in order to prevent the A°C film 20 from remaining in the portion to be removed due to variations in the β film 20, overetching is performed.
211) The exposed surface of 17 was also slightly etched (second
Figure (C) (Illustrated).

尚、この比較例に用いたプラズマエツチング条件は実施
例と同じである。
Incidentally, the plasma etching conditions used in this comparative example were the same as in the example.

すなわち、比較例は従来構造の半導体装置の製造方法で
、第1図構造に対し、S+3N418を除いた構造を持
っており、8i02膜17上にAa膜20を形成しであ
る。
That is, the comparative example is a method of manufacturing a semiconductor device having a conventional structure, and has a structure in which S+3N418 is removed from the structure shown in FIG. 1, and an Aa film 20 is formed on an 8i02 film 17.

しかして、本実施例及び比較例について、それらの製造
工程におけるプラズマエッチング工程際し、A℃膜20
のエツチング中とオーバエツチング中でのレジストパタ
ーン21のエツチング量を調べるため、ジャストエッチ
前後でエツチングが終了するようエツチング時間を変え
てみた。なお、レジストパターン21のエツチング量は
タリステップ(段差針)で測定し、断面の形状は走査型
電子顕微鏡(SEM)で観察した。
Therefore, in the present example and the comparative example, during the plasma etching process in their manufacturing process, the A°C film 20
In order to investigate the amount of etching of the resist pattern 21 during etching and overetching, the etching time was varied so that etching was completed before and after just etching. The etching amount of the resist pattern 21 was measured using a Talystep (stepped needle), and the cross-sectional shape was observed using a scanning electron microscope (SEM).

第4図はその結果を示す特性図であり、実施例をA1比
較例をBで示した。すなわち、図はプラズマエツチング
装置でエツチングした時のレジストパターン21の膜減
り量とエツチング時間の関係を示す図であり、矢印Jで
示した位置がAn膜20のジャストエツチング時間であ
る。図かられかるように、従来構造を持つ比較例日では
ジャストエツチング時間前後で傾きが増大し、レジスト
のエツチングレートが増大していることを示しており、
これにより、明らかに酸素原子が影響していることがわ
かる。一方、Aで示す本発明方法ではA2膜20のジャ
ストエツチング後でも、レジストの劣化及び断面形状の
異状は見られなかった。
FIG. 4 is a characteristic diagram showing the results, in which examples are shown as A and comparative examples as B. That is, the figure shows the relationship between the amount of film loss of the resist pattern 21 and the etching time when etched with a plasma etching apparatus, and the position indicated by arrow J is the just etching time of the An film 20. As can be seen from the figure, in the comparative example with the conventional structure, the slope increases before and after the just etching time, indicating that the etching rate of the resist increases.
This clearly shows that oxygen atoms have an effect. On the other hand, in the method of the present invention indicated by A, no deterioration of the resist or abnormality in the cross-sectional shape was observed even after just etching the A2 film 20.

従って、SiO2膜上にA2膜を形成して、このA℃膜
をプラズマエツチングによりパターニングし、A℃配線
等を形成する場合において、3io2躾上に保護膜とし
てSi3N4膜を形成し、この3i3N41上にA℃膜
を形成して、これをレジストパターンをマスクにプラズ
マエツチングすれば、5102膜のエツチングを防止で
きて、該S+02膜の酸素原子分離を防止でき、これに
よって、レジストパターンの膜減りとアンダーカットの
発生を防止できるのでへβ膜のパターニングを制御性良
く、目的の寸法となるように行うことができる。従って
、高品質の半導体装置が得られる。
Therefore, when forming an A2 film on a SiO2 film and patterning this A°C film by plasma etching to form A°C wiring, etc., an Si3N4 film is formed as a protective film on the 3i3N41 film, and the Si3N4 film is formed on the 3i3N41 film. By forming an A°C film on the substrate and plasma etching it using the resist pattern as a mask, it is possible to prevent the etching of the 5102 film and the separation of oxygen atoms in the S+02 film, thereby reducing the thickness of the resist pattern. Since the occurrence of undercuts can be prevented, the patterning of the β film can be performed with good controllability so as to obtain the desired dimensions. Therefore, a high quality semiconductor device can be obtained.

尚、5iQ2膜の保護膜である513N4膜の膜厚はプ
ラズマエツチング加工時のオーバエツチングによる躾減
り置部上とする必要がある他、保i!膜は酸素原子を含
まない耐熱性のある絶縁材であればSI3N4膜以外の
ものを用いることもできる。上記実施例では配線等の導
電膜にへ2膜を用いていたが、これはアルミニウム合金
もしくは多結晶シリコンまたは高融点金属または高融点
金属のシリサイドなどでも良い。
Note that the thickness of the 513N4 film, which is a protective film for the 5iQ2 film, must be set to a level that reduces the thickness of the 513N4 film due to overetching during plasma etching. The film may be made of a heat-resistant insulating material other than the SI3N4 film that does not contain oxygen atoms. In the above embodiment, a He2 film is used as a conductive film for wiring, etc., but it may be an aluminum alloy, polycrystalline silicon, a high melting point metal, a silicide of a high melting point metal, or the like.

半導体基板上のSiO2膜は熱シリコン酸化膜の他、C
VDシリコン酸化躾またはリン添加硅化ガラスまたはボ
ロン添加硅化ガラスを利用することができる。
The SiO2 film on the semiconductor substrate is not only a thermal silicon oxide film but also a C
VD silicon oxide, phosphorus-doped silicide glass, or boron-doped silica glass can be used.

[発明の効果] 以上、詳述したように本発明によれば、導電膜パターニ
ング用のレジストパターンの膜減りとアンダーカットの
抑制を図ることができ、従って、導電膜を制御性良くパ
ターニングすることができるので、高品質の半導体装置
が得られるなどの特徴を有する半導体装置の製造方法を
提供することができる。
[Effects of the Invention] As described in detail above, according to the present invention, it is possible to suppress film thinning and undercut of a resist pattern for patterning a conductive film, and therefore pattern a conductive film with good controllability. Therefore, it is possible to provide a method for manufacturing a semiconductor device which has features such as being able to obtain a high quality semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(C)は本発明の実施例を示す製造工程
図、第2図(a)〜(C)は比較例の製造工程図、第3
図はプラズマエツチングに用いたプラズマエツチング装
置の概略的な構造を示す図、IN4図はこれら第1図、
第2図の各サンプルのプラズマエツチングによるエツチ
ング時間とレジストパターンの膜減り量との関係を示す
図である。 11・・・半導体基板、12・・・フィールド酸化膜、
13・・・グ〜ト絶縁膜、14・・・ゲート電極、17
・・・シリコン酸化II(SiO2膜上)、18・・・
シリコン窟化膜(Si3N4膜)、20・・・A℃膜、
21・・・レジストパターン、22・・・へβ配線。 出願人代理人 弁理士 鈴江武彦 第1vi!J 第2図
Figures 1 (a) to (C) are manufacturing process diagrams showing examples of the present invention, Figures 2 (a) to (C) are manufacturing process diagrams of comparative examples, and Figure 3.
The figure shows the schematic structure of the plasma etching apparatus used for plasma etching, and the IN4 figure shows the structure shown in Figure 1.
3 is a diagram showing the relationship between the etching time of each sample in FIG. 2 by plasma etching and the amount of film loss of the resist pattern. FIG. 11... Semiconductor substrate, 12... Field oxide film,
13... Gate insulating film, 14... Gate electrode, 17
...Silicon oxide II (on SiO2 film), 18...
Silicon cave film (Si3N4 film), 20...A℃ film,
21...Resist pattern, β wiring to 22... Applicant's agent Patent attorney Takehiko Suzue 1st vi! J Figure 2

Claims (5)

【特許請求の範囲】[Claims] (1)半導体基板に形成された酸化シリコンを主成分と
する絶縁膜の表面に導電性膜を堆積して後、該導電性膜
上にレジストパターンを形成し、これをマスクに前記導
電性膜をプラズマエッチングして該導電性膜をパターニ
ングする半導体装置の製造工程において、前記絶縁膜上
に酸素原子を含まない絶縁物質の膜を形成し、その表面
に導電性膜を堆積して後、該導電性膜上にレジストパタ
ーンを形成し、これをマスクに前記導電性膜をプラズマ
エッチングして該導電性膜をパターニングすることを特
徴とする半導体装置の製造方法。
(1) After depositing a conductive film on the surface of an insulating film mainly composed of silicon oxide formed on a semiconductor substrate, a resist pattern is formed on the conductive film, and this is used as a mask to form the conductive film. In the manufacturing process of a semiconductor device in which the conductive film is patterned by plasma etching, a film of an insulating material that does not contain oxygen atoms is formed on the insulating film, a conductive film is deposited on the surface of the insulating film, and then the conductive film is patterned by plasma etching. 1. A method of manufacturing a semiconductor device, comprising forming a resist pattern on a conductive film, and patterning the conductive film by plasma etching the conductive film using the resist pattern as a mask.
(2)酸素原子を含まない絶縁物質の膜厚はプラズマエ
ッチング加工時のオーバエッチングによる膜減り量以上
とすることを特徴とする特許請求の範囲第1項記載の半
導体装置の製造方法。
(2) The method of manufacturing a semiconductor device according to claim 1, wherein the thickness of the insulating material that does not contain oxygen atoms is greater than the amount of film reduction due to over-etching during plasma etching.
(3)酸素原子を含まない絶縁物質の膜はシリコン窒化
膜であることを特徴とする特許請求の範囲第1項記載の
半導体装置の製造方法。
(3) The method of manufacturing a semiconductor device according to claim 1, wherein the film of an insulating material that does not contain oxygen atoms is a silicon nitride film.
(4)導電性膜はアルミニウムまたはアルミニウム合金
もしくは多結晶シリコンまたは高融点金属または高融点
金属のシリサイドのいずれか一つであることを特徴とす
る特許請求の範囲第1項記載の半導体装置の製造方法。
(4) Manufacturing a semiconductor device according to claim 1, wherein the conductive film is any one of aluminum, an aluminum alloy, polycrystalline silicon, a high melting point metal, or a silicide of a high melting point metal. Method.
(5)絶縁膜は熱シリコン酸化膜またはCVDシリコン
酸化膜またはリン添加硅化ガラスまたはボロン添加硅化
ガラスのいずれか一つであることを特徴とする特許請求
の範囲第1項記載の半導体装置の製造方法。
(5) Manufacturing a semiconductor device according to claim 1, wherein the insulating film is any one of a thermal silicon oxide film, a CVD silicon oxide film, a phosphorous-doped silicide glass, and a boron-doped silica glass. Method.
JP13998784A 1984-07-06 1984-07-06 Manufacture of semiconductor device Pending JPS6119132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13998784A JPS6119132A (en) 1984-07-06 1984-07-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13998784A JPS6119132A (en) 1984-07-06 1984-07-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6119132A true JPS6119132A (en) 1986-01-28

Family

ID=15258298

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13998784A Pending JPS6119132A (en) 1984-07-06 1984-07-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6119132A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0265713U (en) * 1988-11-07 1990-05-17
JPH0461327A (en) * 1990-06-29 1992-02-27 Sharp Corp Manufacturing of semiconductor device
KR100256137B1 (en) * 1996-03-26 2000-05-15 아사무라 타카싯 Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0265713U (en) * 1988-11-07 1990-05-17
JPH0461327A (en) * 1990-06-29 1992-02-27 Sharp Corp Manufacturing of semiconductor device
KR100256137B1 (en) * 1996-03-26 2000-05-15 아사무라 타카싯 Semiconductor device and manufacturing method thereof

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