KR930010670B1 - Metal contact forming method of semiconductor device - Google Patents

Metal contact forming method of semiconductor device Download PDF

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KR930010670B1
KR930010670B1 KR1019910000571A KR910000571A KR930010670B1 KR 930010670 B1 KR930010670 B1 KR 930010670B1 KR 1019910000571 A KR1019910000571 A KR 1019910000571A KR 910000571 A KR910000571 A KR 910000571A KR 930010670 B1 KR930010670 B1 KR 930010670B1
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metal contact
oxide film
forming
film
polysilicon
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KR1019910000571A
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Korean (ko)
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KR920015471A (en
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이영곤
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금성일렉트론 주식회사
문정환
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The metal contact of a semiconductor device is prepared by coating and patterning a photoresist (14) to display the metal contact part on a substrate (11) having a gate (13), forming a polysilicon film (15) and an oxide film (16) in order, removing the photoresist, the polysilicon film and the oxide film at no metal contact area by a lift-off process, forming 1st CVD oxide film (17), etch-backing to form a buried contact area, forming 2nd CVD oxide film (21) and BPSG film (22) in order on all area, removing oxide film (16), 2nd CVD oxide film (21) and BPSG film (22) on the polysilicon film (15) of metal contact area.

Description

반도체장치의 메탈 콘택 형성방법Metal contact formation method of semiconductor device

제1a∼c도 종래의 제조공정도.1a to c are conventional manufacturing process diagrams.

제2a∼d도는 본 발명에 따른 제조공정도이다.2a to d are manufacturing process drawings according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 반도체기판 12 : 필드 산화막11 semiconductor substrate 12 field oxide film

13 : 게이트 14 : 포토레지스트13 gate 14 photoresist

15 : 폴리실리콘 16, 21 : 산화막15 polysilicon 16, 21 oxide film

17 : CVD 산화막 18 : 스토리지 노드17: CVD oxide film 18: storage node

19 : 유전체막 20 : 플레이트19: dielectric film 20: plate

21 : BPSG막21: BPSG film

본 발명은 반도체장치의 제조공정에 관한 것으로, 특히 메탈콘택의 단차를 완화하여 고집적소자에 적합하게 한 반도체장치의 메틸 콘택 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly, to a method of forming a methyl contact in a semiconductor device in which a step of metal contact is alleviated to be suitable for a highly integrated device.

종래에는, 제1a∼c도에 도시한 바와 같이 우선 필드 산화막(2)으로 소자격리된 반도체기판(1)상에 게이트(3)를 형성한 후 고온산화막(4)을 도포하고 소정의 부분에 배리드콘택(Buried Contact)을 형성한 다음(제1a도), 그위에 스토리지 노드(5), 유전체막(6), 플레이트 풀리(7)로 된 커패시터를 형성하고(제1b도), CVD(Chemical Vapour Deposition) 산화막(8), BPSG막(9)을 도포한 후 소정의 부분에 메탈 콘택을 형성하여 제조하였다.Conventionally, as shown in Figs. 1A to 1C, a gate 3 is first formed on a semiconductor substrate 1 isolated from a field oxide film 2, and then a high temperature oxide film 4 is applied to a predetermined portion. After forming a buried contact (FIG. 1A), a capacitor of storage node 5, dielectric film 6, and plate pulley 7 is formed thereon (FIG. 1B), and CVD ( Chemical Vapor Deposition) After the oxide film 8 and the BPSG film 9 were coated, a metal contact was formed on a predetermined portion.

그러나, 이러한 종래 기술은 디바이스의 집적도가 높아짐에 따라 게이트와 게이트사이의 간격이 축소되어 메탈 콘택의 단차가 더욱 심하게 된다. 이에 따라 메탈 콘택에치시 오버 에치 데미지(Over Etch Damage)가 반도체기판에 미치게 되는 단점이 있었다. 더욱이, 5㎛ 정도의 패터닝 기술이 요구되는 16메가 디램급 이상의 디바이스에는 적용이 불가능한 문제점이 있었다.However, in the prior art, as the degree of integration of the device increases, the gap between the gate and the gate is reduced, so that the step of the metal contact becomes more severe. Accordingly, there is a disadvantage in that over etch damage occurs to the semiconductor substrate when the metal contact is etched. Moreover, there is a problem that cannot be applied to devices of 16 mega DRAM or more that require patterning technology of about 5 μm.

본 발명은 이와 같은 문제점을 해결하기 위한 것으로, 본 발명의 목적은 메탈 콘택의 단차를 소정의 높이만큼 완화시키고 배리드 콘택을 샐프 얼라인(Self-allgh)시키며 스토리지 노드의 마진을 확대시킬 수 있는 반도체장치의 메탈 콘택 형성방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object of the present invention is to reduce the step of the metal contact by a predetermined height, to self-allgh the buried contact, and to increase the margin of the storage node. A metal contact forming method of a semiconductor device is provided.

이와 같은 목적을 달성하기 위한 본 발명의 특징은 게이트 형상이 완료된 반도체장치에 있어서, 전면에 포토레지스트를 도포하고 메탈 콘택 형성영역을 노출시킨 후 저면에 폴리실리콘, 산화막을 차례로 스퍼터링하는 공정과, 메탈 콘택 형성영역이외의 폴리실리콘, 산화막을 리포트 오프공정으로 제거하고 전면에 제1CVD 산화막을 도포하는 공정과, 제1 CVD산화막을 에치백하여 배리드 콘택을 내고 상기 배리드 콘택상에 커패시터를 형성하는 공정과, 전면에 제2 CVD 산화막, BPSG막을 차례로 도포하고 폴리실리콘상의 BPSG막, 제2 CVD 산화막을 제거하여 메탈 콘택을 형성하는 공정으로 이루어진 반도체장치의 메탈 콘택 형성방법에 있다.In order to achieve the above object, the present invention provides a semiconductor device in which a gate shape is completed, a process of sputtering polysilicon and an oxide film on a bottom surface after applying a photoresist on a front surface and exposing a metal contact formation region, Removing the polysilicon and oxide films other than the contact forming region by a report off process, applying a first CVD oxide film on the entire surface, etching back the first CVD oxide film to form a buried contact, and forming a capacitor on the buried contact. A metal contact forming method of a semiconductor device comprising a step of applying a second CVD oxide film and a BPSG film on the entire surface, and then removing the polysilicon BPSG film and the second CVD oxide film to form a metal contact.

이하, 본 발명을 첨부도면에 의하여 상세히 설명한다.Hereinafter, the present invention will be described in detail by the accompanying drawings.

제2a∼d도는 본 발명에 따른 제조공정도로서, 우선 제2a도에 도시한 바와 같이 필드 산화막(12)으로 소자격리된 반도체기판(11)상에 게이트(13)을 형성한 후 전면에 포토레지스터(14)를 도포하고 메탈 콘택 형성영역을 노출시킨 다음 전면에 폴리실리콘 15), 산화막(16)을 차례로 스퍼터링한다. 그후, 제2b도와 같이 리프트 오프(Lift-off)공정으로 메탈 콘택영역이외의 폴리실리콘(15), 산화막(16)을 제거하고 전면에 CVD 산화막(17)을 도포한다.2A to 2D are manufacturing process diagrams according to the present invention. First, as shown in FIG. 2A, a gate 13 is formed on a semiconductor substrate 11 isolated from a field oxide film 12, and then a photoresist (on the front surface) is formed. 14) is applied, the metal contact formation region is exposed, and then sputtered polysilicon 15) and oxide film 16 on the entire surface. Thereafter, as shown in FIG. 2B, the polysilicon 15 and the oxide film 16 other than the metal contact region are removed by a lift-off process, and the CVD oxide film 17 is applied to the entire surface.

제2c도에 도시한 바와 같이 CVD 산화막(17)을 에치백하여 배리드 콘택영역에 셀프 얼라인된 배리드 콘택을 형성하고 배리드 콘택상에 스토리지 노드(18), 유전체막 (19) 플레이트(20)로 된 커패시터를 형성한다.As shown in FIG. 2C, the CVD oxide film 17 is etched back to form a self-aligned buried contact in the buried contact region, and the storage node 18 and the dielectric film 19 plate (on the buried contact). Form a capacitor of 20).

그후, 제2d도와 같이 전면에 CVD 산화막(21), BPSG막(22)을 차례로 도포하고 폴리실리콘(15)상의 BPSG막(22), CVD 산화막(21), 산화막(16)을 제거하여 메탈 콘택을 형성하면 본 발명에 따른 반도체 장치의 메탈 콘택이 얻어지게 된다.Thereafter, as shown in FIG. 2D, the CVD oxide film 21 and the BPSG film 22 are sequentially applied to the entire surface, and the BPSG film 22, the CVD oxide film 21, and the oxide film 16 on the polysilicon 15 are removed to remove the metal contact. By forming the metal contact of the semiconductor device according to the present invention is obtained.

이상 설명한 바와 같이, 본 발명에 따르면 메탈 콘택영역상의 폴리실리콘의 높이만큼 메탈 콘택의 단차를 줄일 수 있으며, 상술한 폴리실리콘이 메탈 콘택영역 형성시 블록킹(Blocking)층으로 사용되어 반도체기판에 에치데미지가 미치지 않도록 한다. 또한 콘택홀의 넓이를 크게 할 수 있으므로 차후 메탈공정을 용이하게 할 수 있는 이점이 있다. 더욱이, 메탈 콘택영역상의 폴리실리콘과 스토리지 노드를 동시에 형성하지 않으므로 0.5㎛ 정도의 패터닝이 가능하여 16메가 디램급 이상의 디바이스에 적용할 수 있으며, 콘택 에치시 얼라인 실수로 인한 게이트 측벽의 침식을 방지할 수 있는 효과도 있다.As described above, according to the present invention, the step of the metal contact can be reduced by the height of the polysilicon on the metal contact region, and the polysilicon described above is used as a blocking layer when forming the metal contact region, thereby causing damage to the semiconductor substrate. Do not reach. In addition, since the area of the contact hole can be increased, there is an advantage of facilitating subsequent metal processing. Furthermore, since polysilicon and storage nodes on the metal contact area are not formed at the same time, patterning of about 0.5 μm is possible, which can be applied to devices of 16 mega DRAM or more, and prevents erosion of the gate sidewall due to misalignment during contact etching. There is also an effect that can be done.

Claims (1)

소정영역에 게이트(13)가 형성된 반도체기판(11)상에 포토레지스트(14)를 도포하고 패터닝하여 메탈콘택영역의 반도체기판 부위를 노출시키는 공정과, 결과물 전면에 폴리실리콘층(15)과 산화막(16)을 차례로 형성하는 공정, 상기 메탈콘택영역 이외의 영역에 형성된 포토레지스트(14)와 다결정실리콘층(15) 및 산화막(16)을 리프트 오프 공정에 의해 제거하는 공정, 결과물 전면에 제1 CVD 산화막(17)을 형성한 후 에치백하여 반도체기판 소정부위를 노출시켜 배리드콘택 영역을 형성하는 공정의 상기 배리드콘택영역상에 커패시터를 형성하는 공정, 결과물 전면에 제2 CVD 산화막(21)과 BPSG막(22)을 차례로 형성하는 공정, 및 상기 메탈콘택영역의 다결정실리콘(15)상의 산화막(16), 제2 CVD 산화막(21), BPSG막(22)을 제거하는 공정으로 이루어진 것을 특징으로 하는 반도체 장치의 메탈콘택 형성방법.Exposing and patterning the photoresist 14 on the semiconductor substrate 11 having the gate 13 formed in a predetermined region to expose the semiconductor substrate portion of the metal contact region, and the polysilicon layer 15 and the oxide film on the entire surface of the resultant. A step of sequentially forming (16), a step of removing the photoresist 14, the polysilicon layer 15, and the oxide film 16 formed in a region other than the metal contact region by a lift-off process; Forming a capacitor on the buried contact region in the process of forming a buried contact region by forming a CVD oxide layer 17 and then etching back to expose a predetermined portion of the semiconductor substrate, and a second CVD oxide layer 21 on the entire surface of the resultant. ) And a step of forming the BPSG film 22 in order, and a step of removing the oxide film 16, the second CVD oxide film 21, and the BPSG film 22 on the polysilicon 15 in the metal contact region. Featuring peninsula Metal contact method for forming a device.
KR1019910000571A 1991-01-15 1991-01-15 Metal contact forming method of semiconductor device KR930010670B1 (en)

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KR930010670B1 true KR930010670B1 (en) 1993-11-05

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