KR100353530B1 - method of manufacturing semiconductor device - Google Patents
method of manufacturing semiconductor device Download PDFInfo
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- KR100353530B1 KR100353530B1 KR1019990047562A KR19990047562A KR100353530B1 KR 100353530 B1 KR100353530 B1 KR 100353530B1 KR 1019990047562 A KR1019990047562 A KR 1019990047562A KR 19990047562 A KR19990047562 A KR 19990047562A KR 100353530 B1 KR100353530 B1 KR 100353530B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
Abstract
본 발명은 비트라인 공정 중 플러그 패드의 형성시 주변영역에서의 잔류물 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor device capable of preventing the occurrence of residues in the peripheral area during the formation of the plug pad during the bit line process.
본 발명에 따라, 먼저 셀영역 및 주변영역이 정의되고, 셀영역 및 주변영역에 그의 하부에 게이트 산화막이 구비되고 그의 상부에 마스크 절연막이 구비된 게이트 전극이 각각 형성된 반도체 기판을 제공한다. 그런 다음, 게이트 전극 및 마스크 절연막의 측벽에 절연막 스페이서를 형성하고, 기판 전면에 폴리실리콘막을 형성한 후, 폴리실리콘막 상부에 난반사막을 형성한다. 그리고 나서, 주변영역의 난반사막을 제 1 식각으로 제거하고, 난반사막 및 폴리실리콘막을 제 2 식각으로 식각하여, 셀영역에 플러그 패드를 형성함과 동시에 주변영역의 기판을 노출시킨다. 여기서, 제 1 및 제 2 식각은 다운 스트림 방식의 플라즈마 식각으로 진행한다.According to the present invention, there is provided a semiconductor substrate in which a cell region and a peripheral region are defined first, and a gate electrode is provided below the cell region and the peripheral region, and a gate electrode is provided with a mask insulating film thereon. Then, an insulating film spacer is formed on the sidewalls of the gate electrode and the mask insulating film, a polysilicon film is formed on the entire surface of the substrate, and then a diffuse reflection film is formed on the polysilicon film. Then, the diffuse reflection film of the peripheral area is removed by the first etching, and the diffuse reflection film and the polysilicon film are etched by the second etching, thereby forming a plug pad in the cell area and exposing the substrate of the peripheral area. Here, the first and second etching proceeds with downstream plasma etching.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 비트라인 공정 중 플러그 패드 형성방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a plug pad during a bit line process of a semiconductor device.
일반적으로, 디램(DRAM; Dynamic Random Access Memory)과 같은 반도체 메모리 소자에서 비트라인의 형성시 콘택에서의 전기적 특성을 향상시키기 위하여 폴리실리콘막으로 플러그 패드를 형성한다.In general, in a semiconductor memory device such as a DRAM (DRAM), a plug pad is formed of a polysilicon film to improve electrical characteristics at a contact when forming a bit line.
도 1a 및 도 1b는 종래의 반도체 소자의 비트라인 공정 중 플러그 패드 형성방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of forming a plug pad during a bit line process of a conventional semiconductor device.
도 1a를 참조하면, 셀영역(C) 및 주변영역(P)이 정의된 반도체 기판(10) 상에 하부에 게이트 산화막(11)이 개재되고 상부에 마스크 절연막(13)이 형성된 게이트 전극(12)을 형성한다. 그런 다음, 게이트 전극(12) 및 마스크 절연막(13)의 측벽에 절연막 스페이서(14)를 형성하고, 기판 전면에 폴리실리콘막(15)을 형성한다.Referring to FIG. 1A, a gate electrode 12 having a gate oxide film 11 interposed therebetween and a mask insulating layer 13 formed thereon is formed on a semiconductor substrate 10 on which a cell region C and a peripheral region P are defined. ). Then, the insulating film spacer 14 is formed on the sidewalls of the gate electrode 12 and the mask insulating film 13, and the polysilicon film 15 is formed on the entire substrate.
도 1b를 참조하면, 이후 주변영역(P)에서의 폴리실리콘막(15)을 효과적으로 제거하기 위하여, 폴리실리콘막(15)을 에치백(etch back)으로 소정 두께만큼 식각한다. 그런 다음, 식각된 폴리실리콘막(15A) 상부에 난반사(anti-reflective coating; ACR)막(16)을 형성하고, 셀영역(C)의 ARC막(16) 상에 포토리소그라피로 플러그 패드 영역을 한정하는 포토레지스트 패턴(17)을 형성한다.Referring to FIG. 1B, in order to effectively remove the polysilicon layer 15 in the peripheral region P, the polysilicon layer 15 is etched by a predetermined thickness with an etch back. Then, an anti-reflective coating (ACR) film 16 is formed on the etched polysilicon film 15A, and the plug pad region is formed by photolithography on the ARC film 16 of the cell region C. A photoresist pattern 17 to be defined is formed.
도 1c를 참조하면, 포토레지스트 패턴(17)을 식각 마스크로하여 ARC막(16) 및 폴리실리콘막(15A)을 식각하여, 셀영역(C)의 게이트 전극(12) 사이의 기판과 콘택하는 플러그 패드(100)를 형성함과 동시에 주변영역(P)의 기판(10)을 노출시킨다. 그리고 나서, 공지된 방법으로 포토레지스트 패턴(17)을 제거한다.Referring to FIG. 1C, the ARC film 16 and the polysilicon film 15A are etched using the photoresist pattern 17 as an etch mask to contact the substrate between the gate electrodes 12 of the cell region C. The plug pad 100 is formed and the substrate 10 of the peripheral area P is exposed. Then, the photoresist pattern 17 is removed by a known method.
상기한 종래의 플러그 패드 형성을 위한 ARC막(16) 및 폴리실리콘막(15A)의 식각은 일반적으로 스퍼터링 식각(sputter etching)으로 진행한다. 그러나, 상기한 식각의 진행시, 직진성을 갖는 이온 효과에 의해 주변영역(P)의 ARC막(16)이 완전히 제거되지 않고 잔재하여 하부의 폴리실리콘막(15A)의 식각을 방해함으로써, 도 1c에 도시된 바와 같이, 식각 후 주변영역(P)에 잔류물(R)이 발생하게 된다. 이러한 잔류물(R)은 챔버 오염 및 웨이퍼 오염을 유발하여, 후속 공정시 악영향을 미치게 되어 결국 소자의 신뢰성 및 수율이 저하된다.The etching of the ARC film 16 and the polysilicon film 15A for forming the conventional plug pad is generally performed by sputter etching. However, when the etching proceeds, the ARC film 16 in the peripheral region P is not completely removed by the ion effect having the straightness, and thus remains to prevent the lower polysilicon film 15A from being etched. As shown in FIG. 3, residues R are generated in the peripheral region P after etching. These residues R cause chamber contamination and wafer contamination, adversely affecting subsequent processing, resulting in lower reliability and yield of the device.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 비트라인 공정 중 플러그 패드의 형성시 주변영역에서의 잔류물 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing the occurrence of residues in the peripheral area when the plug pad is formed during the bit line process.
도 1a 및 도 1c는 종래의 반도체 소자의 플러그 패드 형성방법을 설명하기 위한 단면도.1A and 1C are cross-sectional views illustrating a method of forming a plug pad of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 플러그 패드 형성방법을 설명하기 위한 단면도.2A to 2D are cross-sectional views illustrating a method for forming a plug pad of a semiconductor device in accordance with an embodiment of the present invention.
(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
20 : 반도체 기판 21 : 게이트 산화막20 semiconductor substrate 21 gate oxide film
22 : 게이트 전극 23 : 마스크 절연막22 gate electrode 23 mask insulating film
24 : 절연막 스페이서 25 : 폴리실리콘막24 insulating film spacer 25 polysilicon film
26 : 난반사막26: diffuse reflection
27, 28 : 제 1 및 제 2 포토레지스트 패턴27, 28: first and second photoresist pattern
200 : 플러그 패드 C : 셀영역200: plug pad C: cell area
P : 주변영역P: peripheral area
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따라, 먼저 셀영역 및 주변영역이 정의되고, 셀영역 및 주변영역에 그의 하부에 게이트 산화막이 구비되고 그의 상부에 마스크 절연막이 구비된 게이트 전극이 각각 형성된 반도체 기판을 제공한다. 그런 다음, 게이트 전극 및 마스크 절연막의 측벽에 절연막 스페이서를 형성하고, 기판 전면에 폴리실리콘막을 형성한 후, 폴리실리콘막 상부에 난반사막을 형성한다. 그리고 나서, 주변영역의 난반사막을 제 1 식각으로 제거하고, 난반사막 및 폴리실리콘막을 제 2 식각으로 식각하여, 셀영역에 플러그 패드를 형성함과 동시에 주변영역의 기판을 노출시킨다.In order to achieve the above object of the present invention, according to the present invention, the cell region and the peripheral region are first defined, the gate electrode is provided with a gate oxide film on the lower portion of the cell region and the peripheral region and provided with a mask insulating film on the upper portion thereof. Provided are each formed semiconductor substrate. Then, an insulating film spacer is formed on the sidewalls of the gate electrode and the mask insulating film, a polysilicon film is formed on the entire surface of the substrate, and then a diffuse reflection film is formed on the polysilicon film. Then, the diffuse reflection film of the peripheral area is removed by the first etching, and the diffuse reflection film and the polysilicon film are etched by the second etching, thereby forming a plug pad in the cell area and exposing the substrate of the peripheral area.
본 실시예에서, 제 1 및 제 2 식각은 다운 스트림 방식의 플라즈마 식각으로진행한다.In this embodiment, the first and second etching proceed with downstream plasma etching.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 플러그 패드 형성방법을 설명하기 위한 단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a plug pad of a semiconductor device according to an embodiment of the present invention.
도 2a를 참조하면, 셀영역(C) 및 주변영역(P)이 정의된 반도체 기판(20) 상에 하부에 게이트 산화막(21)이 개재되고 상부에 마스크 절연막(23)이 형성된 게이트 전극(22)을 형성한다. 그런 다음, 게이트 전극(22) 및 마스크 절연막(23)의 측벽에 절연막 스페이서(24)를 형성하고, 기판 전면에 폴리실리콘막(25)을 형성한다. 그리고 나서, 이후 주변영역(P)에서의 폴리실리콘막(25)을 효과적으로 제거하기 위하여, 폴리실리콘막(25)을 에치백(etch back)으로 소정 두께만큼 식각하고, 식각된 폴리실리콘막(25) 상부에 ACR막(26)을 형성한다.Referring to FIG. 2A, a gate electrode 22 having a gate oxide film 21 interposed therebetween and a mask insulating film 23 formed thereon is formed on a semiconductor substrate 20 on which a cell region C and a peripheral region P are defined. ). Then, an insulating film spacer 24 is formed on the sidewalls of the gate electrode 22 and the mask insulating film 23, and a polysilicon film 25 is formed on the entire surface of the substrate. Then, in order to effectively remove the polysilicon film 25 in the peripheral region P, the polysilicon film 25 is etched by a etch back to a predetermined thickness, and the etched polysilicon film 25 ACR film 26 is formed on the upper side.
도 2b를 참조하면, ARC막(26) 상에 포토리소그라피로 셀영역(C)을 마스킹함과 동시에 주변영역(P)을 노출시키는 제 1 포토레지스트 패턴(27)을 형성한다. 그런 다음, 제 1 포토레지스트 패턴(27)을 식각 마스크로하여 플라즈마 식각으로 주변영역 (P)의 ARC막(26)을 완전히 제거한다. 바람직하게, 플라즈마 식각은 다운 스트림 (down stream) 방식으로 진행한다.Referring to FIG. 2B, a first photoresist pattern 27 is formed on the ARC film 26 to expose the cell region C and expose the peripheral region P with photolithography. Thereafter, the ARC film 26 in the peripheral region P is completely removed by plasma etching using the first photoresist pattern 27 as an etching mask. Preferably, the plasma etching proceeds in a downstream manner.
도 2c를 참조하면, 공지된 방법으로 제 1 포토레지스트 패턴(27)을 제거하고, 셀영역(C)의 ARC막(26) 상에 포토리소그라피로 플러그 패드 영역을 한정하는 제 2 포토레지스트 패턴(28)을 형성한다.Referring to FIG. 2C, the second photoresist pattern 27 may be removed by a known method, and the plug pad region may be defined by photolithography on the ARC layer 26 of the cell region C. 28).
도 2d를 참조하면, 제 2 포토레지스트 패턴(28)을 식각 마스크로하여 셀영역(C)의 ARC막(26)과, 폴리실리콘막(25)을 플라즈마 식각으로 식각하여 셀영역 (C)에 게이트 전극(22) 사이의 기판과 콘택하는 플러그 패드(200)를 형성함과 동시에 주변영역(P)의 기판(20)을 노출시킨다. 바람직하게, 플라즈마 식각은 다운 스트림 방식으로 진행한다. 그리고 나서, 공지된 방법으로 제 2 포토레지스트 패턴(28)을 제거한다.Referring to FIG. 2D, the ARC film 26 of the cell region C and the polysilicon layer 25 are etched by plasma etching using the second photoresist pattern 28 as an etching mask to the cell region C. Referring to FIG. The plug pad 200 contacting the substrate between the gate electrodes 22 is formed, and the substrate 20 in the peripheral region P is exposed. Preferably, the plasma etching proceeds in a downstream manner. Then, the second photoresist pattern 28 is removed by a known method.
상기한 본 발명에 의하면, 종래의 스퍼터링 식각 대신 다운 스트림 방식의 플라즈마 식각공정을 적용하여, 주변영역의 ARC막을 완전히 제거한 후, 셀영역에 플러그 패드를 형성함으로써, 주변영역의 잔류물 발생이 방지된다. 이에 따라, 종래와 같은 잔류물에 기인하는 챔버 오염 및 웨이퍼 오염이 방지되어, 후속 공정이 용이해짐에 따라, 소자의 수율 및 신뢰성이 향상된다.According to the present invention described above, by applying a downstream plasma etching process instead of the conventional sputtering etching, after completely removing the ARC film in the peripheral region, by forming a plug pad in the cell region, the occurrence of residue in the peripheral region is prevented. . This prevents chamber contamination and wafer contamination due to conventional residues, thereby facilitating subsequent processing, thereby improving device yield and reliability.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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