KR20000004399A - Method for manufacturing semiconductor devices - Google Patents
Method for manufacturing semiconductor devices Download PDFInfo
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- KR20000004399A KR20000004399A KR1019980025831A KR19980025831A KR20000004399A KR 20000004399 A KR20000004399 A KR 20000004399A KR 1019980025831 A KR1019980025831 A KR 1019980025831A KR 19980025831 A KR19980025831 A KR 19980025831A KR 20000004399 A KR20000004399 A KR 20000004399A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
- H01L21/32132—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only of silicon-containing layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 주변영역의 심한 경사로 인한 식각 잔류물의 발생을 효과적으로 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of effectively preventing the occurrence of etching residues due to severe inclination of a peripheral area.
반도체 메모리 소자의 집적도가 증가됨에 따라, 배선의 폭 및 배선 사이의 간격이 감소된다. 이에 따라, 0.25 ㎛ 이하의 디자인룰이 적용되는 메모리 소자에서는 하부 배선의 양 측에 절연막 스페이서를 형성한 후 상부배선을 형성하는 기술이 적용된다.As the integration degree of the semiconductor memory device is increased, the width of the wiring and the spacing between the wirings are reduced. Accordingly, in a memory device to which a design rule of 0.25 μm or less is applied, a technique of forming an insulating film spacer on both sides of the lower wiring and then forming an upper wiring is applied.
도 1a 및 도 1b는 상기한 바와 같은 스페이서가 적용된 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device to which a spacer as described above is applied.
도 1a를 참조하면, 셀영역(미도시) 및 주변영역(A)이 정의되고, 상부에 필드 산화막(11) 및 도전막 패턴(12a, 12b)이 형성된 반도체 기판(10) 상에 절연막을 증착한다. 그런 다음, 상기 절연막을 블랭킷 식각으로 식각하여, 도전막 패턴(12a, 12b)의 양 측벽에 스페이서(13)를 각각 형성한다. 그런 다음, 기판 전면에 절연막(30)을 증착하고, 셀영역의 절연막(30)을 식각하여 스토리지 전극용 콘택홀(미도시)을 형성한다. 그 후, 상기 콘택홀에 매립되도록 절연막(30) 상에 플러그용 폴리실리콘막(14)을 증착한다.Referring to FIG. 1A, an insulating film is deposited on a semiconductor substrate 10 on which a cell region (not shown) and a peripheral region A are defined, and the field oxide layer 11 and the conductive layer patterns 12a and 12b are formed thereon. do. Then, the insulating layer is etched by blanket etching to form spacers 13 on both sidewalls of the conductive layer patterns 12a and 12b, respectively. Then, an insulating film 30 is deposited on the entire surface of the substrate, and the insulating film 30 in the cell region is etched to form a contact hole (not shown) for a storage electrode. Thereafter, a plug-in polysilicon film 14 is deposited on the insulating film 30 so as to be filled in the contact hole.
도 1b를 참조하면, 폴리실리콘막(14)을 블랭킷 건식식각으로 소정 두께 식각하여, 주변영역(A)의 단차를 최소화한다. 그런 다음, 폴리실리콘막(14) 상에 ARC(Anti-Reflective Coating)막(15)을 증착하고, ARC막(15) 및 폴리실리콘막(14a)을 식각하여 셀영역에 스토리지 전극용 콘택을 위한 폴리실리콘막 플러그(미도시)를 형성함과 동시에, 도 1c에 도시된 바와 같이, 주변영역(A)의 ARC막(15) 및 폴리실리콘막(14a)을 제거한다.Referring to FIG. 1B, the polysilicon film 14 is etched by a blanket dry etching to a predetermined thickness to minimize the step difference of the peripheral area A. FIG. Then, an ARC (Anti-Reflective Coating) film 15 is deposited on the polysilicon film 14, the ARC film 15 and the polysilicon film 14a are etched to etch the contacts for storage electrodes in the cell region. While forming a polysilicon film plug (not shown), as shown in FIG. 1C, the ARC film 15 and the polysilicon film 14a in the peripheral region A are removed.
그러나, 상기한 바와 같이 셀 영역에 폴리실리콘막 플러그를 형성할 때, 도 1b에 도시된 바와 같은 주변영역(A)의 경사각이 심한 부분의 ARC막(15)이 단차로 인하여, 식각 공정에서 ARC막(15)이 완전히 제거되지 않고 잔재하여 하부의 폴리실리콘막(14a)의 식각을 방해한다. 이에 따라, 도 1c에 도시된 바와 같이, 폴리실리콘막(14a)이 완전히 제거되지 않고, 절연막(30) 상부에 잔류물(R)로 존재한다.즉, 도 2a는 ARC막(15)의 증착전의 주변영역(A)을 나타낸 단면 사진으로서, 도 2a에 나타낸 바와 같이, 폴리실리콘막(14a)의 경사각이 심한 부분(S)이 존재함을 알 수 있다. 또한, 도 2b는 폴리실리콘막(14a)의 제거후 주변영역(A)을 나타낸 단면 사진으로서, 도 2b에 나타낸 바와 같이, 폴리실리콘막(14a)이 완전히 제거되지 않고, 잔류물(R)로 존재함을 알 수 있다. 따라서, 이러한 잔류물(R)에 의해 브릿지가 유발되어, 결국 소자의 신뢰성이 저하된다. 또한, 이러한 잔류물(R)을 완전히 제거하기 위하여, 식각을 과도하게 진행하게 되면, 도시되지는 않았지만, 셀 영역에 형성되는 폴리실리콘막 플러그가 손상되는 문제가 발생한다.However, when the polysilicon film plug is formed in the cell region as described above, the ARC film 15 at the inclined angle of the peripheral region A, as shown in FIG. The film 15 is not completely removed but remains to prevent etching of the lower polysilicon film 14a. Accordingly, as shown in FIG. 1C, the polysilicon film 14a is not completely removed but exists as a residue R on the insulating film 30. That is, FIG. 2A shows deposition of the ARC film 15. As a cross-sectional photograph showing the former peripheral area A, as shown in FIG. 2A, it can be seen that a portion S having a high inclination angle of the polysilicon film 14a exists. FIG. 2B is a cross-sectional photograph showing the peripheral area A after removal of the polysilicon film 14a. As shown in FIG. 2B, the polysilicon film 14a is not completely removed and remains as a residue R. As shown in FIG. It can be seen that it exists. Therefore, such a residue R causes a bridge, which in turn lowers the reliability of the device. In addition, when the etching is excessively performed to completely remove the residue R, a polysilicon film plug formed in the cell region may be damaged, although not illustrated.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리실리콘막 플러그의 형성시 셀 영역의 패턴을 손상시키는 것 없이, 주변 영역의 경사각을 완화시켜 식각 잔류물 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned conventional problems, a semiconductor that can reduce the inclination angle of the peripheral region to prevent the occurrence of etching residues without damaging the pattern of the cell region when forming the polysilicon film plug Its purpose is to provide a method for manufacturing a device.
도 1a 내지 도 1c는 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
도 2a 및 도 2b는 종래의 반도체 소자의 주변영역의 단면사진을 나타낸 도면.2A and 2B illustrate cross-sectional photographs of peripheral regions of a conventional semiconductor device.
도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 4a 및 도 4b는 본 발명의 실시예에 따른 반도체 소자의 주변영역의 단면사진을 나타낸 도면.4A and 4B are cross-sectional views of peripheral regions of semiconductor devices in accordance with an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
20 : 반도체 기판 21 : 필드 산화막20: semiconductor substrate 21: field oxide film
22a, 22b : 도전막 패턴 23 : 스페이서22a, 22b: conductive film pattern 23: spacer
24 : 폴리실리콘막 25 : ARC막24 polysilicon film 25 ARC film
A : 주변영역 R : 잔류물A: peripheral area R: residue
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자는 셀 영역 및 주변영역이 정의되고 셀 영역 및 주변영역 상에 양 측벽에 절연막의 스페이서를 구비한 도전막 패턴이 형성된 반도체 기판과, 기판 전면에 형성되고 상기 도전막 패턴에 의해 그의 표면이 제 1 경사각을 가지는 폴리실리콘막을 포함한다. 여기서, 폴리실리콘막을 제 1 식각함으로써, 그의 표면이 상기 제 1 경사각 보다 감소된 제 2 경사각을 갖도록 한 후, 폴리실리콘막을 제 2 식각하여 셀 영역에 폴리실리콘막 플러그를 형성함과 동시에 주변영역의 폴리실리콘막을 제거한다.The semiconductor device according to the present invention for achieving the above object is a semiconductor substrate in which a cell region and a peripheral region are defined, and a conductive film pattern having spacers of insulating films formed on both sidewalls of the cell region and the peripheral region, and formed on the front surface of the substrate. And a polysilicon film whose surface has a first inclination angle by the conductive film pattern. Here, the polysilicon film is etched first so that its surface has a second inclination angle that is reduced from the first inclination angle, and then the polysilicon film is etched second to form a polysilicon film plug in the cell region and at the same time Remove the polysilicon film.
본 실시예에서, 제 1 식각은 스퍼터링 방식으로 진행하고, 스퍼터링은 He, Ne, 및 Ar 으로 이루어진 그룹으로부터 선택되는 하나의 개스를 이용하여 플라즈마를 형성하여 진행한다. 또한, 스퍼터링은 HBr, C2F6개스와 같은 분자량이 무거운 개스를 이용하여 진행하거나, 상기 분자량이 무거운 개스와 비활성 개스의 혼합개스를 이용하여 진행할 수 있다.In the present embodiment, the first etching proceeds in a sputtering manner, and the sputtering proceeds by forming a plasma using one gas selected from the group consisting of He, Ne, and Ar. In addition, sputtering may be carried out using a mixed gas of HBr, C 2 F 6 gas and the molecular weight is conducted by using a heavy gas, or gas and inert gas such that the heavy molecular weight.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 3a 내지 도 3c는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다. 도 4a 및 도 4b는 본 발명의 실시예에 따른 반도체 소자의 주변영역의 단면사진을 나타낸 도면으로서, 도 4a는 폴리실리콘막의 스퍼터링후의 주변영역을 나타내고, 도 4b는 폴리실리콘막의 제거후의 주변영역을 나타낸다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. 4A and 4B are cross-sectional views of peripheral regions of semiconductor devices according to an exemplary embodiment of the present invention, and FIG. 4A illustrates a peripheral region after sputtering of a polysilicon film, and FIG. 4B illustrates a peripheral region after removal of a polysilicon film. Indicates.
도 3a를 참조하면, 셀영역(미도시) 및 주변영역(A)이 정의되고, 상부에 필드 산화막(21) 및 도전막 패턴(22a, 22b)이 형성된 반도체 기판(20) 상에 절연막을 증착한다. 그런 다음, 상기 절연막을 블랭킷 식각으로 식각하여, 도전막 패턴(22a, 22b)의 양 측벽에 스페이서(23)를 각각 형성한다. 기판 전면에 절연막(40)을 증착하고, 셀영역의 절연막(40)을 식각하여 스토리지 전극용 콘택홀(미도시)을 형성한다. 그 후, 상기 콘택홀에 매립되도록 절연막(40) 상에 플러그용 폴리실리콘막(24)을 증착하고, 스퍼터링 식각으로 식각한다.Referring to FIG. 3A, an insulating film is deposited on a semiconductor substrate 20 on which a cell region (not shown) and a peripheral region A are defined, and field oxide films 21 and conductive layer patterns 22a and 22b are formed thereon. do. Then, the insulating film is etched by blanket etching to form spacers 23 on both sidewalls of the conductive film patterns 22a and 22b, respectively. The insulating film 40 is deposited on the entire surface of the substrate, and the insulating film 40 in the cell region is etched to form a contact hole (not shown) for the storage electrode. Thereafter, a plug-in polysilicon film 24 is deposited on the insulating film 40 so as to be filled in the contact hole, and etched by sputtering etching.
여기서, 스퍼터링 식각은 분자량이 무거울수록, 화학반응이 일어나지 않을수록 효과적으로 진행되므로, He, Ne, Ar과 같은 8족 비활성 개스, 바람직하게 Ar을 이용하여 플라즈마를 형성하여 진행한다. 또한, 스퍼터링 식각은 HBr, C2F6개스와 같은 분자량이 무거운 개스를 단독으로 이용하여 진행하거나, 상기 분자량이 무거운 개스와 비활성 개스의 혼합개스를 이용하여 진행할 수 있다. 이때, RIE(Reactive Ion Etching), MERIE(Magnetically Enhanced RIE), ECR(Electron Cyclotron Resonace), ICP(Inductive Coupled Plasma), TCP(Transformer Coupled Plasma), HRe 등의 장비를 이용하여 100 내지 3,000 W의 소오스 파워와, 0 내지 3,000W의 바이어스 파워에서 진행한다.Here, since the sputtering etching proceeds more effectively as the molecular weight is higher and the chemical reaction does not occur, the plasma is formed using a Group 8 inert gas such as He, Ne, and Ar, preferably Ar. In addition, the sputtering etching may be performed by using a gas having a high molecular weight such as HBr, C 2 F 6 gas alone, or by using a mixed gas of the gas having a high molecular weight and an inert gas. In this case, a source of 100 to 3,000 W using equipment such as Reactive Ion Etching (RIE), Magnetically Enhanced RIE (MERIE), Electron Cyclotron Resonace (ECR), Inductive Coupled Plasma (ICP), Transformer Coupled Plasma (TCP), HRe, etc. It proceeds at power and a bias power of 0-3,000W.
여기서, ICP의 일종인 HDP 장비에서, 상기한 분자량이 무거운 C2F6개스를 이용하면, 스퍼터링 효과를 볼 수 있다. 즉, HDP 장비에서 C2F6개스는 다음과 같이 F＋을 생성한다.Here, in the HDP equipment which is a kind of ICP, if the above-mentioned heavy molecular weight C 2 F 6 gas is used, sputtering effect can be seen. That is, C 2 F 6 gas in the HDP equipment generates F + as follows.
C2F6→ C2F5＋ FC 2 F 6 → C 2 F 5 + F
C2F5→ C2F5 ＋＋ e- C 2 F 5 → C 2 F 5 + + e -
F→ F＋＋ e- F → F + + e -
이때, 생성된 F＋는 실리콘과 반응하여 화학반응을 일으키는 F＋을 소모한다. 그 결과, C2F5 ＋가 기판에 입사되어 화학반응을 억제하면서 스퍼터링만 일어날 수 있도록 할 수 있다.At this time, the resulting F + F + consumes causing a chemical reaction by reacting with the silicon. As a result, C 2 F 5 + can be incident on the substrate so that only sputtering can occur while suppressing the chemical reaction.
또한, 폴리실리콘막(24)의 경사가 심한 부분과 경사가 완만한 부분의 식각 선택비를 3 : 1 이상으로 진행하여, 도 3b에 도시된 바와 같이, 경사각을 완화시킨다. 즉, 도 4a에 도시된 바와 같이, 상기한 스퍼터링의 진행 후, 폴리실리콘막(24a)이 완만한 경사를 갖는 것을 알 수 있다. 그런 다음, 식각된 폴리실리콘막(24a)상에 ARC(Anti-Reflective Coating)막(25)을 증착한다.In addition, the etching selectivity of the highly inclined portion and the inclined portion of the polysilicon film 24 is advanced to 3: 1 or more, and as shown in FIG. 3B, the inclination angle is relaxed. That is, as shown in FIG. 4A, it can be seen that the polysilicon film 24a has a gentle slope after the above sputtering. Then, an ARC (Anti-Reflective Coating) film 25 is deposited on the etched polysilicon film 24a.
도 3c를 참조하면, ARC막(25) 및 폴리실리콘막(24)을 건식식각하여, 셀영역에 스토리지 전극용 콘택을 위한 폴리실리콘막 플러그(미도시)를 형성함과 더불어 주변영역(A)의 폴리실리콘막(24a) 및 ARC막(25)을 완전히 제거한다. 즉, 도 4b에 도시된 바와 같이, 폴리실리콘막(24a) 및 ARC막(25)의 제거공정 후 종래(도 2b 참조)와 같이, 주변영역에 폴리실리콘막(24a)의 잔류물이 존재하지 않는 것을 볼 수 있다.Referring to FIG. 3C, the ARC film 25 and the polysilicon film 24 are dry-etched to form a polysilicon film plug (not shown) for the storage electrode contact in the cell region, and the peripheral region A. Of the polysilicon film 24a and the ARC film 25 are completely removed. That is, as shown in FIG. 4B, after the process of removing the polysilicon film 24a and the ARC film 25, there is no residue of the polysilicon film 24a in the peripheral region as in the prior art (see FIG. 2B). You can see that it doesn't.
상기한 본 발명에 의하면, 플러그용 폴리실리콘막의 증착 후 단차로 인해 발생된 폴리실리콘막의 경사각을 완화시킴으로써, 폴리실리콘막 상부의 ARC막이 완전히 제거된다. 이에 따라, 주변영역의 폴리실리콘막이 잔류물을 발생시키는 것 없이 완전히 제거된다. 따라서, 식각 잔류물로 인한 브릿지 발생이 방지된다. 또한, 식각이 과도하게 진행될 필요가 없으므로, 폴리실리콘막 플러그가 손상되지 않으므로, 결국 소자의 신뢰성이 향상된다.According to the present invention described above, by reducing the inclination angle of the polysilicon film generated due to the step after the deposition of the plug polysilicon film, the ARC film on the polysilicon film is completely removed. Thus, the polysilicon film in the peripheral area is completely removed without generating residue. Thus, bridge generation due to etching residues is prevented. In addition, since the etching does not need to proceed excessively, the polysilicon film plug is not damaged, and thus the reliability of the device is improved.
또한, 본 발명은 상기 실시예에 한정되지 되지 않고 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
Claims (7)
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