KR100299514B1 - method of manufacturing semiconductor device - Google Patents
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- KR100299514B1 KR100299514B1 KR1019990023754A KR19990023754A KR100299514B1 KR 100299514 B1 KR100299514 B1 KR 100299514B1 KR 1019990023754 A KR1019990023754 A KR 1019990023754A KR 19990023754 A KR19990023754 A KR 19990023754A KR 100299514 B1 KR100299514 B1 KR 100299514B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 230000008021 deposition Effects 0.000 claims abstract description 21
- 239000007789 gas Substances 0.000 claims abstract description 21
- 230000002093 peripheral effect Effects 0.000 claims abstract description 19
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims abstract description 14
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims abstract description 7
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 229910052786 argon Inorganic materials 0.000 claims abstract description 6
- CTQNGGLPUBDAKN-UHFFFAOYSA-N O-Xylene Chemical compound CC1=CC=CC=C1C CTQNGGLPUBDAKN-UHFFFAOYSA-N 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 239000012495 reaction gas Substances 0.000 claims description 3
- 239000008096 xylene Substances 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000006117 anti-reflective coating Substances 0.000 description 9
- 238000004544 sputter deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 241000219289 Silene Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052918 calcium silicate Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 폴리실리콘막의 증착시 토폴로지 완화가 동시에 이루어지도록 하여 공정을 단순화시키고, 폴리실리콘막 플러그의 형성시 잔류물 및 파티클 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method of manufacturing a semiconductor device capable of simplifying a process by simultaneously performing topology relaxation upon deposition of a polysilicon film and preventing generation of residues and particles during formation of the polysilicon film plug.
본 발명에 따른 반도체 소자는 셀 영역 및 주변영역이 정의되고 셀 영역 및 주변영역 상에, 그의 측벽에 절연막 스페이서를 구비한 도전막 패턴이 형성된 반도체 기판과, 기판 전면에 형성되고 상기 셀 영역의 일부를 노출시키는 콘택홀을 구비한 절연막을 포함한다. 콘택홀에 매립되도록 절연막 상에 플러그용 폴리실리콘막을 형성하고, 폴리실리콘막 상에 ARC막을 형성한 후, ARC막 및 폴리실리콘막을 식각하여 셀영역에 폴리실리콘막 플러그를 형성하고 주변영역의 ARC막을 제거한다. 또한, 폴리실리콘막은 고밀도 플라즈마 화학기상증착으로 형성하여 증착과 동시에 토폴로지를 완화시킨다. 본 실시예에서, 고밀도 플라즈마 화학기상증착은 0 내지 1,000W의 저주파 바이어스 파워만을 인가하여 증착만이 이루어지도록 한 후, 0 내지 4,000W의 고주파 바이어스 파워를 인가하여 식각과 증착이 동시에 이루어지도록 하고, 0 내지 1,000sccm의 사일렌 개스와 0 내지 100sccm의 포스핀 개스와, 0 내지 1,000sccm의 아르곤 개스를 이용하여 진행한다. 또한, 고밀도 플라즈마 화학기상증착은 반응챔버 온도를 300 내지 600℃로 유지시켜 진행한다.The semiconductor device according to the present invention is a semiconductor substrate having a cell region and a peripheral region defined thereon, and a conductive film pattern having an insulating film spacer formed on sidewalls thereof on a cell region and a peripheral region, and formed on a front surface of the substrate and a part of the cell region. It includes an insulating film having a contact hole for exposing the. A polysilicon film for a plug is formed on the insulating film so as to be filled in the contact hole, an ARC film is formed on the polysilicon film, and then the ARC film and the polysilicon film are etched to form a polysilicon plug in the cell region and the ARC film in the peripheral region. Remove In addition, the polysilicon film is formed by high density plasma chemical vapor deposition to relax the topology at the same time as the deposition. In this embodiment, the high-density plasma chemical vapor deposition is applied to only the low-frequency bias power of 0 to 1,000W to make the deposition only, and then to apply the high-frequency bias power of 0 to 4,000W, so that etching and deposition are performed at the same time, It proceeds using 0-1,000 sccm of a silylene gas, 0-100 sccm of phosphine gas, and 0-1,000 sccm of argon gas. In addition, the high-density plasma chemical vapor deposition is performed by maintaining the reaction chamber temperature at 300 to 600 ℃.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 폴리실리콘막 플러그의 형성시 공정을 단순화시키면서 주변영역의 잔류물 발생을 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing the generation of residues in a peripheral region while simplifying the process of forming a polysilicon film plug.
반도체 메모리 소자의 집적도가 증가됨에 따라, 배선의 폭 및 배선 사이의 간격이 감소된다. 이에 따라, 0.25㎛ 이하의 디자인룰이 적용되는 메모리 소자에서는 하부배선의 측벽에 절연막 스페이서를 형성한 후, 하부배선과 상부배선을 폴리실리콘막 플러그를 이용하여 연결한다.As the integration degree of the semiconductor memory device is increased, the width of the wiring and the spacing between the wirings are reduced. Accordingly, in the memory device to which the design rule of 0.25 mu m or less is applied, after forming the insulating film spacer on the sidewall of the lower wiring, the lower wiring and the upper wiring are connected by using the polysilicon film plug.
도 1a 및 도 1b는 상기한 바와 같은 폴리실리콘 플러그가 적용된 반도체 소자의 제조방법을 설명하기 위한 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing a semiconductor device to which a polysilicon plug as described above is applied.
도 1a를 참조하면, 셀영역(미도시) 및 주변영역(A)이 정의되고, 상부에 필드 산화막(11) 및 워드라인(12A, 12b)이 형성된 반도체 기판(10) 상에 절연막을 증착한다. 그런 다음, 상기 절연막을 블랭킷 식각으로 식각하여, 워드라인(12A, 12B)의 측벽에 스페이서(13)를 각각 형성하고, 기판 전면에 절연막(14)을 증착한다. 그 후, 셀영역의 절연막(14)을 식각하여 콘택홀(미도시)을 형성하고, 콘택홀에 매립되도록 절연막(14) 상에 플러그용 폴리실리콘막(15)을 증착한 후, 그 상부에 반사방지(Anti-Reflective Coating; ARC)막(16)을 증착한다.Referring to FIG. 1A, an insulating film is deposited on a semiconductor substrate 10 on which a cell region (not shown) and a peripheral region A are defined, and field oxide films 11 and word lines 12A and 12b are formed thereon. . Then, the insulating film is etched by blanket etching to form spacers 13 on sidewalls of the word lines 12A and 12B, and the insulating film 14 is deposited on the entire surface of the substrate. Thereafter, the insulating film 14 in the cell region is etched to form a contact hole (not shown), and a plug polysilicon film 15 is deposited on the insulating film 14 so as to be filled in the contact hole, and then, An anti-reflective coating (ARC) film 16 is deposited.
도 1b를 참조하면, ARC막(16) 및 폴리실리콘막(15)을 식각하여 셀영역에 폴리실리콘막 플러그(미도시)를 형성하고, 주변영역(A)의 ARC막(16) 및 폴리실리콘막 (15)을 제거한다.Referring to FIG. 1B, the ARC film 16 and the polysilicon film 15 are etched to form a polysilicon plug (not shown) in the cell region, and the ARC film 16 and the polysilicon in the peripheral region A are formed. The membrane 15 is removed.
한편, 폴리실리콘막 플러그의 형성시, 주변영역(A)의 단차가 큰 영역의 토폴로지로 인하여 ARC막(16)이 완전히 제거되지 않고 잔재하여 하부의 폴리실리콘막 (15)의 식각을 방해하여, 도 1b에 도시된 바와 같이, 주변영역역(A)에 폴리실리콘막의 잔류물(R)이 발생한다. 따라서, 잔류물(R)의 발생을 방지하기 위하여, 폴리실리콘막(15)의 증착 후, 아르곤 스퍼터링을 이용한 전면식각으로 토폴로지 완화공정이 진행되어야 한다. 즉, 도 2는 폴리실리콘막(15)의 토폴로지 완화공정 후 관찰된 주변영역의 단면사진을 나타낸 도면으로서, 도 2에 나타낸 바와 같이 폴리실리콘막 (15)의 표면 토폴로지가 완화됨을 알 수 있다.On the other hand, when the polysilicon film plug is formed, the ARC film 16 is not completely removed due to the topology of the region having a large step height of the peripheral region A, thereby preventing the lower polysilicon film 15 from being etched. As shown in Fig. 1B, residues R of the polysilicon film occur in the peripheral region A. Therefore, in order to prevent the occurrence of residues R, after the deposition of the polysilicon film 15, the topology relaxation process must be performed by the front surface etching using argon sputtering. That is, FIG. 2 is a cross-sectional view of the peripheral region observed after the topology relaxation process of the polysilicon film 15. As shown in FIG. 2, it can be seen that the surface topology of the polysilicon film 15 is relaxed.
그러나, 아르곤 스퍼터링은 많은 파티클을 발생하기 때문에, 이러한 파티클을 제거하기 위한 별도의 제거공정이 요구된다. 이에 따라, 폴리실리콘막의 형성공정이 증착공정-토폴로지 완화공정-파티클 제거공정으로 진행되므로 공정이 복잡할 뿐만 아니라, 공정자체에서 발생되는 잔류물 및 파티클로 인하여 소자의 수율 및 신뢰성이 저하된다.However, since argon sputtering generates a lot of particles, a separate removal process for removing such particles is required. Accordingly, since the process of forming the polysilicon film proceeds to a deposition process, a topology relaxation process, and a particle removing process, the process is not only complicated, but also the yield and reliability of the device are reduced due to residues and particles generated in the process itself.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로서, 폴리실리콘막의 증착시 도 2에 나타낸 바와 같은 토폴로지 완화가 동시에 이루어지도록 하여 공정을 단순화시키고, 폴리실리콘막 플러그의 형성시 잔류물 및 파티클 발생을 방지할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention is to solve the above-mentioned conventional problems, to simplify the process by simultaneously performing the topology relaxation as shown in Figure 2 during the deposition of the polysilicon film, residues and particles in the formation of the polysilicon film plug It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing the occurrence of the same.
도 1a 및 도 1b는 종래의 반도체 소자의 제조방법을 설명하기 위한 단면도.1A and 1B are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
도 2는 폴리실리콘막의 토폴로지 완화공정 후 관찰된 주변영역의 단면사진을 나타낸 도면.2 is a cross-sectional view of the peripheral region observed after the topology relaxation process of the polysilicon film.
도 3a 및 3b는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도.3A and 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
〔도면의 주요 부분에 대한 부호의 설명〕[Description of Code for Major Parts of Drawing]
30 : 반도체 기판 31 : 필드 산화막30 semiconductor substrate 31 field oxide film
32A, 32B : 워드라인 33 : 스페이서32A, 32B: Wordline 33: Spacer
34 : 절연막 35 : 폴리실리콘막34 insulating film 35 polysilicon film
36 : ARC막 A : 주변영역36: ARC film A: surrounding area
상기한 본 발명의 목적을 달성하기 위하여, 본 발명에 따른 반도체 소자는 셀 영역 및 주변영역이 정의되고 셀 영역 및 주변영역 상에, 그의 측벽에 절연막 스페이서를 구비한 도전막 패턴이 형성된 반도체 기판과, 기판 전면에 형성되고 상기 셀 영역의 일부를 노출시키는 콘택홀을 구비한 절연막을 포함한다. 콘택홀에 매립되도록 절연막 상에 플러그용 폴리실리콘막을 형성하고, 폴리실리콘막 상에 반사방지막을 형성한 후, 반사방지막 및 폴리실리콘막을 식각하여 셀영역에 폴리실리콘막 플러그를 형성하고 주변영역의 반사방지막을 제거한다. 또한, 폴리실리콘막은 고밀도 플라즈마 화학기상증착으로 형성하여 증착과 동시에 토폴로지를 완화시킨다.In order to achieve the above object of the present invention, the semiconductor device according to the present invention includes a semiconductor substrate in which a cell region and a peripheral region are defined, and on the cell region and the peripheral region, a conductive film pattern having an insulating film spacer on the sidewall thereof is formed; And an insulating film formed on the entire surface of the substrate and having a contact hole exposing a portion of the cell region. A polysilicon film for a plug is formed on the insulating film so as to be filled in the contact hole, an antireflection film is formed on the polysilicon film, and then the antireflection film and the polysilicon film are etched to form a polysilicon plug in the cell region and to reflect the peripheral region. Remove the barrier. In addition, the polysilicon film is formed by high density plasma chemical vapor deposition to relax the topology at the same time as the deposition.
본 실시예에서, 고밀도 플라즈마 화학기상증착은 0 내지 1,000W의 저주파 바이어스 파워만을 인가하여 증착만이 이루어지도록 한 후, 0 내지 4,000W의 고주파 바이어스 파워를 인가하여 식각과 증착이 동시에 이루어지도록 하고, 0 내지 1,000sccm의 사일렌 개스와 0 내지 100sccm의 포스핀 개스와, 0 내지 1,000sccm의 아르곤 개스를 이용하여 진행한다. 또한, 고밀도 플라즈마 화학기상증착은 반응챔버 온도를 300 내지 600℃로 유지시켜 진행한다.In this embodiment, the high-density plasma chemical vapor deposition is applied to only the low-frequency bias power of 0 to 1,000W to make the deposition only, and then to apply the high-frequency bias power of 0 to 4,000W, so that etching and deposition are performed at the same time, It proceeds using 0-1,000 sccm of a silylene gas, 0-100 sccm of phosphine gas, and 0-1,000 sccm of argon gas. In addition, the high-density plasma chemical vapor deposition is performed by maintaining the reaction chamber temperature at 300 to 600 ℃.
또한, 폴리실리콘막은 반응개스로서 사일렌 개스를 사용하고 도핑개스로서 포스핀 개스를 이용한 인시튜 도핑으로 도핑한다.In addition, the polysilicon film is doped by in-situ doping using xylene gas as the reaction gas and phosphine gas as the doping gas.
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.
도 3a 내지 도 3b는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 단면도이다.3A to 3B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
도 3a를 참조하면, 셀영역(미도시) 및 주변영역(A)이 정의되고, 상부에 필드 산화막(31) 및 워드라인(32A, 32B)과 같은 도전막 패턴이 형성된 반도체 기판(30) 상에 절연막을 증착한다. 그런 다음, 상기 절연막을 블랭킷 식각으로 식각하여, 워드라인(32A, 32B)의 측벽에 스페이서(33)를 형성하고, 기판 전면에 절연막(34)을 증착한다. 그 후, 셀영역의 절연막(34)을 식각하여 콘택홀(미도시)을 형성하고, 콘택홀에 매립되도록 절연막(34) 상에 고밀도 플라즈마 화학기상증착(High Density Plasma Chemical Vapor Deposition; HDP-CVD)으로 플러그용 폴리실리콘막(35)을 형성한다.Referring to FIG. 3A, a cell region (not shown) and a peripheral region A are defined, and an upper portion of the semiconductor substrate 30 on which conductive layer patterns such as the field oxide layer 31 and the word lines 32A and 32B are formed is formed. An insulating film is deposited on the. Then, the insulating film is etched by blanket etching to form spacers 33 on sidewalls of the word lines 32A and 32B, and the insulating film 34 is deposited on the entire surface of the substrate. Thereafter, the insulating film 34 in the cell region is etched to form a contact hole (not shown), and high density plasma chemical vapor deposition (HDP-CVD) is formed on the insulating film 34 so as to be filled in the contact hole. The polysilicon film 35 for plug is formed.
상기 HDP-CVD에서는 폴리실리콘막(35)의 증착/식각/증착 공정이 동시에 연속적으로 실행되므로 증착과 동시에 토폴로지가 완화된다. 예컨대, HDP-CVD는 절연막 평탄화에 일반적으로 사용되는 방법인데, 이를 폴리실리콘막의 증착에 적용함으로써, 증착과 동시에 토폴로지를 완화시킬 수 있다. 본 발명에서는 0 내지 1,000sccm의 사일렌 개스와 0 내지 100sccm의 포스핀 개스와, 0 내지 1,000sccm의 아르곤 개스를 이용하여, HDP-CVD는 초기에는 저주파 바이어스 파워, 바람직하게 0 내지 1,000W의 바이어스 파워만을 인가하여 증착(35A)만이 이루어지도록 한 후, 고주파 바이어스 파워, 바람직하게 0 내지 4,000W의 바이어스 파워를 인가하여 식각과 증착(35B, 35C)이 동시에 이루어지도록 진행한다. 또한, 상기한 HDP-CVD는 반응챔버 온도를 300 내지 600℃로 유지시켜 진행한다.In the HDP-CVD, since the deposition / etching / deposition process of the polysilicon film 35 is performed continuously at the same time, the topology is relaxed at the same time as the deposition. For example, HDP-CVD is a method generally used for planarization of an insulating film, and by applying it to deposition of a polysilicon film, the topology can be relaxed simultaneously with deposition. In the present invention, HDP-CVD is initially performed with a low frequency bias power, preferably a bias of 0 to 1,000 W, using 0 to 1,000 sccm of silene gas, 0 to 100 sccm of phosphine gas, and 0 to 1,000 sccm of argon gas. After applying only the power to make only the deposition 35A, the high frequency bias power, preferably 0 to 4,000W of bias power, is applied so that the etching and the deposition 35B and 35C are performed simultaneously. In addition, the HDP-CVD is carried out by maintaining the reaction chamber temperature at 300 to 600 ℃.
즉, 저주파 바이어스 파워에서는 플라즈마가 형성되고 이온의 직진성이 감소되어 Ar 스퍼터링에 의한 스퍼터 효과가 감소됨으로써 워드라인(32A, 32B)이 보호되면서 증착만이 이루어지는 반면, 고주파 바이어스 파워에서는 플라즈마가 형성되고 이온의 직진성이 증가되어 스퍼터 효과가 증가됨으로써 폴리실리콘막(35)의 토폴로지가 완화된다. 또한, 폴리실리콘막(35)은 반응개스로서 사일렌 개스를 사용하고 도핑개스로서 포스핀 개스를 이용한 인시튜(in-situ) 도핑으로 도핑한다.That is, at low frequency bias power, plasma is formed, and the linearity of ions is reduced, so that sputtering effect by Ar sputtering is reduced, so that only deposition is performed while protecting word lines 32A and 32B, whereas at high frequency bias power, plasma is formed and ions are formed. The straightness of the polysilicon film 35 is relaxed by increasing the sputtering effect and increasing the sputtering effect. In addition, the polysilicon film 35 is doped by in-situ doping using xylene gas as the reaction gas and phosphine gas as the doping gas.
그리고 나서, 폴리실리콘막(35) 상부에 ARC막(36)을 증착하고, ARC막(36) 및폴리실리콘막(35)을 식각하여 셀영역에 폴리실리콘막 플러그(미도시)를 형성하고, 주변영역(A)의 ARC막(36) 및 폴리실리콘막(35)을 제거한다. 이때, 도 3b에 도시된 바와 같이, 주변영역(A)에 종래(도 1b 참조)와 같은 폴리실리콘막(35)의 잔류물이 존재하지 않는다.Then, the ARC film 36 is deposited on the polysilicon film 35, the ARC film 36 and the polysilicon film 35 are etched to form a polysilicon film plug (not shown) in the cell region. The ARC film 36 and the polysilicon film 35 in the peripheral region A are removed. At this time, as shown in FIG. 3B, no residue of the polysilicon film 35 as in the prior art (see FIG. 1B) exists in the peripheral region A. FIG.
상기한 본 발명에 의하면, 플러그용 폴리실리콘막을 HDP-CVD로 형성함으로써 증착과 동시에 식각이 이루어지도록 하여 토폴로지를 완화시킴으로써, 증착 후 별도의 토폴로지 완화공정 및 토폴로지 완화공정에 따른 불순물 제거공정이 요구되지 않으므로 공정이 단순해진다. 또한, 폴리실리콘막 플러그의 형성후 주변영역의 폴리실리콘막이 잔류물을 발생시키는 것 없이 완전히 제거됨으로써, 소자의 수율 및 신뢰성이 향상된다.According to the present invention described above, by forming a polysilicon film for a plug by HDP-CVD, so that the etching is performed at the same time as the deposition to relax the topology, a separate topology relaxation step and the impurity removal process according to the topology relaxation step is not required after deposition. Therefore, the process is simplified. In addition, after the polysilicon film plug is formed, the polysilicon film in the peripheral region is completely removed without generating residue, thereby improving the yield and reliability of the device.
또한, 본 발명은 상기 실시예에 한정되지 되지 않고 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.In addition, this invention is not limited to the said Example, It can variously deform and implement within the range which does not deviate from the technical summary of this invention.
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| KR19980050428A (en) * | 1996-12-20 | 1998-09-15 | 김영환 | Method of forming planarization insulating film of semiconductor device |
| KR19980045143A (en) * | 1996-12-09 | 1998-09-15 | 김광호 | Planarization Method of Semiconductor Device |
| KR19980057125A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Interlayer planarization method in semiconductor device manufacturing |
| JPH10294294A (en) * | 1997-04-10 | 1998-11-04 | Lg Semicon Co Ltd | Formation of metallic wiring of semiconductor device |
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| KR19980045143A (en) * | 1996-12-09 | 1998-09-15 | 김광호 | Planarization Method of Semiconductor Device |
| KR19980050428A (en) * | 1996-12-20 | 1998-09-15 | 김영환 | Method of forming planarization insulating film of semiconductor device |
| KR19980057125A (en) * | 1996-12-30 | 1998-09-25 | 김영환 | Interlayer planarization method in semiconductor device manufacturing |
| JPH10294294A (en) * | 1997-04-10 | 1998-11-04 | Lg Semicon Co Ltd | Formation of metallic wiring of semiconductor device |
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