KR100325601B1 - a manufacturing method of contact holes of semiconductor devices - Google Patents

a manufacturing method of contact holes of semiconductor devices Download PDF

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KR100325601B1
KR100325601B1 KR1019990016823A KR19990016823A KR100325601B1 KR 100325601 B1 KR100325601 B1 KR 100325601B1 KR 1019990016823 A KR1019990016823 A KR 1019990016823A KR 19990016823 A KR19990016823 A KR 19990016823A KR 100325601 B1 KR100325601 B1 KR 100325601B1
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film
oxide film
silicide
layer
active region
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KR20000073505A (en
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남창길
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황인길
아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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Abstract

본 발명은 반도체 집적회로 공정에 있어서 접촉구의 형성 방법에 관한 것으로서, 반도체 기판에 활성 영역 및 활성 영역과 인접하며 소자를 분리하기 위한 영역인 필드 산화막을 형성한 후, 기판 전면에 폴리 실리콘막을 증착하고 그 위에 실리사이드막을 형성한 다음, 산화막을 증착한다. 다음, 폴리 실리콘막, 실리사이드막, 산화막을 식각하여 게이트 패턴을 형성한 후, 게이트 패턴의 측벽에 질화막 스페이서를 형성하고 활성 영역에 에피 실리콘층을 성장시킨다. 이때 에피 실리콘층은 필드 산화막 상부의 가장자리 안쪽으로까지 형성되도록 한다. 이 에피 실리콘층을 실리사이드화한 후 TEOS막, BPSG막, TEOS막으로 이루어진 산화막을 증착한다. 다음, 산화막을 식각하여 게이트 상부의 실리사이드막, 그리고 게이트와 필드 산화막 사이의 실리사이드막을 각각 드러내는 접촉구를 형성한다. 본 발명에서는 산화막에 대해 선택비가 높은 실리사이드 막을 사용하여, 필드 산화막의 유실을 막을 수 있으므로 누설 전류를 방지할 수 있다. 또한 질화막을 사용하지 않기 때문에 질화막 식각시 발생하는 폴리머 문제를 해결하여 접촉 저항을 감소할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor integrated circuit process, wherein a field oxide film is formed on a semiconductor substrate, the active region and a region adjacent to the active region, and a region for separating devices, and then a polysilicon film is deposited on the entire surface of the substrate. A silicide film is formed thereon, and then an oxide film is deposited. Next, after forming the gate pattern by etching the polysilicon film, the silicide film, and the oxide film, a nitride film spacer is formed on the sidewall of the gate pattern, and the epi silicon layer is grown in the active region. At this time, the epi silicon layer is formed to the inner side of the upper edge of the field oxide film. After the epi silicon layer is silicided, an oxide film made of a TEOS film, a BPSG film, and a TEOS film is deposited. Next, the oxide film is etched to form contact holes for exposing the silicide film on the gate and the silicide film between the gate and the field oxide film, respectively. In the present invention, a silicide film having a high selectivity relative to the oxide film can be used to prevent the loss of the field oxide film, thereby preventing leakage current. In addition, since the nitride film is not used, the contact resistance may be reduced by solving the polymer problem generated during the nitride film etching.

Description

반도체 소자의 접촉구 형성 방법{a manufacturing method of contact holes of semiconductor devices}TECHNICAL FIELD [0001] A manufacturing method of contact holes of semiconductor devices

본 발명은 반도체 소자의 접촉구 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole in a semiconductor device.

최근, 반도체 회로는 그 크기가 더욱 감소됨에 따라, 집적 회로에서의 배선을 다층화하고, 이 배선들을 접촉구를 통해 연결하는 다층 배선 방법이 주로 사용되고 있다.Recently, as the size of a semiconductor circuit is further reduced, a multilayer wiring method for multilayering wirings in an integrated circuit and connecting these wirings through contact holes is mainly used.

그러나, 소자의 크기가 감소할수록 배선간의 교차부인 접촉구를 형성하는 과정에서 접촉구 패턴의 오정렬(misalign)이 쉽게 발생한다.However, as the size of the device decreases, misalignment of the contact pattern occurs easily in the process of forming the contact hole, which is an intersection between the wirings.

그러면 도 1a 내지 도 1c를 참고로 하여, 종래의 기술에 따른 반도체 소자의 접촉구 형성 방법에 대하여 설명한다.1A to 1C, a contact hole forming method of a semiconductor device according to the related art will be described.

도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 접촉구 형성 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a method for forming a contact hole of a semiconductor device according to the related art.

도 1a에 도시한 바와 같이, 실리콘 기판(1) 위에 소자 분리 영역으로 필드 산화막(2)이 있는 STI(shallow trench isolation)를 형성한 다음, 게이트(3)를 형성한다. 게이트(3) 측벽에 질화막 스페이서(4)를 형성하고, 실리사이드 공정을 통하여 게이트(3)의 상부 표면과 기판(1)의 활성 영역(16) 표면에 실리사이드막(5)을 형성한다.As shown in FIG. 1A, a shallow trench isolation (STI) having a field oxide film 2 is formed on the silicon substrate 1 as an isolation region, and then a gate 3 is formed. The nitride film spacer 4 is formed on the sidewall of the gate 3, and the silicide film 5 is formed on the upper surface of the gate 3 and the surface of the active region 16 of the substrate 1 through a silicide process.

다음, 도 1b에 도시한 바와 같이, 도 1a에 나타난 기판 위에 산화막과 선택비가 높은 질화막(6)을 300Å 정도 증착한다. 그 위에 평탄화를 위해 BPSG(borophosphosilicate)막(7)을 증착한 후 열처리 공정을 통하여 밀도를 높인다. 그리고 BPSG막(7)을 일정한 두께까지 CMP(chemical mechanical polishing)한다. 그 위에 1000Å의 TEOS(tetraethyl orthosilicate)막(8)을 증착한다.Next, as shown in FIG. 1B, a nitride film 6 having a high selectivity and an oxide film is deposited on the substrate shown in FIG. The BPSG (borophosphosilicate) film 7 is deposited thereon for the planarization thereof, and the density thereof is increased through a heat treatment process. The BPSG film 7 is subjected to chemical mechanical polishing (CMP) to a certain thickness. On top of that is deposited 1000 TEOS (tetraethyl orthosilicate) film (8).

이어, 감광막을 도포하고 패터닝하여 감광막 패턴(10)을 형성한 후, 감광막 패턴(10)을 마스크로 하여 도 1c에 도시한 바와 같이, TEOS막(8)과 BPSG막(7), 그리고 질화막(6)을 식각하여 게이트(3) 상부와 활성 영역(16) 상부의 실리사이드막(5)을 각각 드러내는 접촉구(C1)를 형성한다.Subsequently, after the photoresist film is applied and patterned to form the photoresist pattern 10, the photoresist pattern 10 is used as a mask, and as shown in FIG. 1C, the TEOS film 8, the BPSG film 7, and the nitride film ( 6) is etched to form contact holes C1 exposing the silicide layer 5 over the gate 3 and over the active region 16, respectively.

이때, 접촉구(C1) 형성을 위한 식각 공정은 다음의 두 단계로 나누어 실시한다. 먼저, 질화막과 선택비가 높은 산화막 식각 기체로 TEOS막(8)과 BPSG막(7) 등의 산화막을 식각한 후, 질화막(6)을 식각하기 위한 식각 기체로 남아있는 질화막(6)을 짧은 시간동안 식각한다.At this time, the etching process for forming the contact hole (C1) is carried out divided into the following two steps. First, the oxide film such as the TEOS film 8 and the BPSG film 7 is etched using the nitride film and the oxide film etching gas having a high selectivity, and then the nitride film 6 remaining as an etching gas for etching the nitride film 6 is short. Etch while.

여기서, 산화막을 식각하기 위한 기체가 TEOS막(8)과 BPSG막(7) 등의 산화막을 식각하고 질화막(6)을 만나게 되면 폴리머를 형성하게 되는데, 이러한 폴리머는 질화막(6)의 식각을 방해하며, 접촉 저항을 증가시키는 요인이 된다.Here, when the gas for etching the oxide film etches the oxide film such as the TEOS film 8 and the BPSG film 7 and meets the nitride film 6, the polymer forms a polymer, which prevents the etching of the nitride film 6. This increases the contact resistance.

또한 이러한 종래의 방법에서는, 막의 단차에 따라 국부적으로 식각비의 차이가 발생하고, 질화막의 균일성(uniformity) 및 막질(quality)이 저하됨에 따라 산화막과 질화막의 선택비도 감소하므로, 오정렬이 발생할 경우 그림 1c에서와 같이 필드 산화막(2)의 모서리 부분(A)이 유실되어 다이오드 누설 전류가 생기게 된다.In addition, in the conventional method, the difference in etching ratio occurs locally according to the step of the film, and the selectivity of the oxide film and the nitride film also decreases as the uniformity and film quality of the nitride film decrease, so that misalignment occurs. As shown in Fig. 1c, the corner portion A of the field oxide film 2 is lost, resulting in a diode leakage current.

한편, 질화막은 플라즈마 화학기상증착법으로 증착하게 되는데, 이러한 방법으로 증착된 질화막은 내부에 수소를 포함하게 된다. 이와 같은 질화막 내의 수소는 핫 캐리어 효과(hot carrier effect)와 임계 전압 변화을 유발하는 요인이 된다.On the other hand, the nitride film is deposited by a plasma chemical vapor deposition method, the nitride film deposited by this method will contain hydrogen therein. Hydrogen in such a nitride film is a factor inducing a hot carrier effect and a change in threshold voltage.

본 발명의 과제는 앞 서 언급한 문제를 해결하기 위한 것으로서, 필드 산화막이 유실되는 것을 막아 전류가 누설되는 것을 방지하는 것이다.An object of the present invention is to solve the above-mentioned problem, to prevent the field oxide film from being lost and to prevent leakage of current.

본 발명의 다른 과제는 실리콘 기판 또는 하부 배선과 상부 배선이 접촉하는 통로인 접촉구의 식각 마진을 확보하는 것이다.Another object of the present invention is to secure an etching margin of a contact hole, which is a passage between the silicon substrate or the lower wiring and the upper wiring.

본 발명의 다른 과제는 접촉구에서의 접촉 저항을 최소화하는데 있다.Another object of the present invention is to minimize the contact resistance at the contact hole.

도 1a 내지 도 1c는 종래의 기술에 따른 반도체 소자의 접촉구 형성 방법을 공정 순서에 따라 나타낸 단면도이고,1A to 1C are cross-sectional views illustrating a method for forming a contact hole in a conventional semiconductor device according to a process sequence;

도 2a 내지 도 2d는 본 발명에 따른 접촉구 형성 방법을 공정 순서에 따라 나타낸 단면도이다.2A to 2D are cross-sectional views illustrating a method for forming a contact hole according to the present invention in a process sequence.

이러한 과제를 해결하기 위한 본 발명에 따른 공정은 반도체 집적 회로 공정에서, 반도체 기판에 활성 영역 및 활성 영역과 인접하며 소자를 분리하기 위한 영역인 필드 산화막을 형성한 후, 활성 영역에 에피 실리콘층을 성장시킨 다음, 에피 실리콘층을 실리사이드화하고 절연 및 평탄화를 위한 산화막을 증착한다. 그 위에 감광막을 도포하고 패터닝한 후 패터닝된 감광막을 마스크로 산화막을 식각하여 실리사이드막을 드러내는 접촉구를 형성한다.In the process according to the present invention for solving this problem, in the semiconductor integrated circuit process, after forming the field oxide film which is adjacent to the active region and the active region on the semiconductor substrate to separate the devices, the epi silicon layer is formed in the active region After growth, the epi silicon layer is silicided and an oxide film for insulation and planarization is deposited. After the photoresist is coated and patterned, the oxide film is etched using the patterned photoresist as a mask to form a contact hole exposing the silicide layer.

여기서 게이트를 형성하기 위해 다음과 같은 공정이 포함되는 것이 바람직하다. 활성 영역 및 필드 산화막이 형성되어 있는 반도체 기판 전면에 폴리 실리콘막을 증착하고 그 위에 실리사이드막을 형성한 다음, 산화막을 보호막으로 증착한다. 다음, 폴리 실리콘막, 실리사이드막, 산화막을 식각하여 게이트 패턴을 형성한 후, 게이트 패턴의 측벽에 질화막 스페이서를 형성한다.Here, it is preferable to include the following process for forming the gate. A polysilicon film is deposited on the entire surface of the semiconductor substrate on which the active region and the field oxide film are formed, a silicide film is formed thereon, and the oxide film is deposited as a protective film. Next, after forming the gate pattern by etching the polysilicon film, the silicide film, and the oxide film, a nitride film spacer is formed on the sidewall of the gate pattern.

한편, 절연 및 평탄화를 위한 산화막은 TEOS막, BPSG막, TEOS막의 삼중막으로 이루어질 수 있다.Meanwhile, the oxide film for insulation and planarization may be formed of a triple film of a TEOS film, a BPSG film, and a TEOS film.

본 발명에서 에피 실리콘층은 활성 영역과 인접하고 있는 필드 산화막 상부의 가장자리 안쪽으로까지 형성되도록 하는데, 이 에피 실리콘층을 산화막에 대해 선택비가 높은 실리사이드막으로 실리사이드화함으로써, 접촉구 패턴의 오정렬이 발생하더라도 실리사이드막에 의해 필드 산화막이 유실되는 것이 방지된다. 따라서 누설 전류가 발생하는 것을 방지할 수 있다.In the present invention, the epi silicon layer is formed to the inner side of the upper portion of the field oxide film adjacent to the active region, and the epi silicon layer is silicided into a silicide film having a high selectivity with respect to the oxide film, whereby misalignment of the contact pattern occurs. Even if the silicide film is lost, the field oxide film is prevented from being lost. Therefore, leakage current can be prevented from occurring.

또한 접촉구 내의 활성 영역과 접하는 실리사이드막의 면적이 넓기 때문에 접촉저항이 감소되며, 질화막을 사용하지 않으므로 질화막의 식각에 의한 폴리머의 생성 문제가 해결된다.In addition, since the area of the silicide film in contact with the active region in the contact hole is large, the contact resistance is reduced, and since the nitride film is not used, the problem of formation of the polymer by etching the nitride film is solved.

그러면, 첨부한 도면을 참고로 하여 본 발명의 실시예에 따른 공정에 대하여 본 발명의 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세하게 설명한다.Then, with reference to the accompanying drawings will be described in detail to be easily carried out by those skilled in the art with respect to the process according to an embodiment of the present invention.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 접촉구 형성 방법을 공정 순서에 따라 나타낸 단면도이다.2A to 2D are cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to the present invention in a process sequence.

먼저, 도 2a에 도시한 바와 같이, 활성 영역(16)을 갖는 소자 영역과 소자 분리 영역인 필드 산화막(2) 등이 형성되어 있는 실리콘 기판(1) 위에 게이트 형성을 위한 폴리 실리콘막(3)을 증착하고 실리사이드막(11)을 형성한 후, 산화막(12)을 증착한다. 폴리 실리콘막(3), 실리사이드막(11), 산화막(12)을 식각하여 게이트 패턴을 형성한 다음, 게이트 패턴의 측벽에 질화막 스페이서(4)를 형성한다.First, as shown in FIG. 2A, a polysilicon film 3 for gate formation is formed on a silicon substrate 1 on which an element region having an active region 16 and a field oxide film 2, which is an element isolation region, are formed. Is deposited and the silicide film 11 is formed, and then the oxide film 12 is deposited. The silicon film 3, the silicide film 11, and the oxide film 12 are etched to form a gate pattern, and then a nitride film spacer 4 is formed on sidewalls of the gate pattern.

다음, 그림 2b에 도시한 바와 같이, 실리콘 기판(1)의 활성 영역(16)을 시드(seed)로 하여 에피 실리콘(epi-Si)층(13)을 성장시킨다. 이때, 성장된 에피 실리콘층(13)이 또 다른 시드가 되어 필드 산화막(2)의 가장자리 안쪽으로 일정폭만큼 성장해 간다. 한편, 게이트(3) 상부의 실리사이드막(11) 위에는 성장 방지층으로 산화막(12)이 형성되어 있어 에피 실리콘이 성장되는 것을 막는다.Next, as shown in FIG. 2B, the epi-Si layer 13 is grown using the active region 16 of the silicon substrate 1 as a seed. At this time, the grown epi silicon layer 13 becomes another seed and grows by a predetermined width inside the edge of the field oxide film 2. On the other hand, an oxide film 12 is formed on the silicide film 11 on the gate 3 as a growth prevention layer to prevent epi silicon from growing.

이어, 그림 2c에 도시한 바와 같이, 실리사이드 공정을 통하여 에피-실리콘층(13)을 실리사이드막(14)화 한다. 이때, 실리사이드 공정은 기판 전면에 금속을 증착한 후 열처리 공정으로 에피 실리콘층을 실리사이드화하고 실리사이드가 형성되지 않은 부분의 금속은 제거한다. 여기서 실리사이드막은 티타늄 실리사이드, 코발트 실리사이드, 텅스텐 실리사이드 중의 하나로 이루어질 수 있다. 다음,TEOS막(15)을 1500Å 정도 증착하고, 그 위에 BPSG막(7)을 증착한 후 CMP를 실시하여 BPSG막(7)을 평탄화 시킨다. 다시, 그 위에 TEOS막(8)을 1000Å 증착한다.Subsequently, as shown in FIG. 2C, the epi-silicon layer 13 is formed into a silicide layer 14 through a silicide process. In this case, the silicide process deposits a metal on the entire surface of the substrate, and then silicides the epi silicon layer by a heat treatment process, and removes the metal in the silicide-free portion. The silicide layer may include one of titanium silicide, cobalt silicide, and tungsten silicide. Next, the TEOS film 15 is deposited at about 1500 Å, the BPSG film 7 is deposited thereon, and then CMP is performed to planarize the BPSG film 7. Again, the TEOS film 8 is deposited thereon at 1000 mW.

그 위에 감광막을 도포하고 패터닝하여 감광막 패턴(10)을 형성한 후, 도 2d에 도시한 바와 같이 감광막 패턴(10)을 마스크로 하여 TEOS막(8), BPSG막(7), TEOS막(15)으로 이루어진 산화막을 식각하여, 게이트(3) 상부의 실리사이드막(11)과 게이트(3)와 필드 산화막(2) 사이의 실리사이드막(14)을 드러내는 접촉구(C2)를 형성한다. 이때, 게이트(3) 상부에서는 다른 부분보다 산화막(8,7,15)의 두께가 얇기 때문에 실리사이드막(11) 위에 형성되어 있는 산화막(12)까지 제거된다.After the photoresist film was applied and patterned to form the photoresist pattern 10, the photoresist pattern 10 was used as a mask as shown in FIG. 2D, and then the TEOS film 8, the BPSG film 7 and the TEOS film 15 were formed. The oxide film made of () is etched to form a contact hole C2 exposing the silicide film 11 on the gate 3 and the silicide film 14 between the gate 3 and the field oxide film 2. At this time, since the thicknesses of the oxide films 8, 7, and 15 are thinner than those of the other portions on the gate 3, the oxide films 12 formed on the silicide film 11 are removed.

이와 같은 실시예에서, 필드 산화막(2)의 가장자리를 덮고 있는 실리사이드막(14)과 산화막 간의 선택비가 상당히 높기 때문에, 오정렬된 접촉구 패턴을 마스크로 하여 접촉구를 식각하더라도, 실리사이드막(14)에 의해 필드 산화막(2)이 식각되는 것이 방지된다. 또한, 질화막을 사용하지 않으므로 질화막 식각시 발생하는 폴리머 생성을 억제할 수 있다.In such an embodiment, since the selectivity between the silicide film 14 covering the edge of the field oxide film 2 and the oxide film is considerably high, even when the contact hole is etched using the misaligned contact hole pattern as a mask, the silicide film 14 This prevents the field oxide film 2 from being etched. In addition, since the nitride film is not used, the generation of the polymer generated during the nitride film etching can be suppressed.

이와 같이 본 발명에 따른 공정은 종래의 기술에 비하여 다음과 같은 효과가 있다.Thus, the process according to the present invention has the following effects as compared to the prior art.

산화막에 대해 질화막보다 선택비가 상당히 높은 실리사이드를 필드 산화막 위의 방지층(stop layer)으로 사용하므로 필드 산화막의 유실을 막을 수 있다. 따라서 누설 전류를 방지할 수 있다. 그리고 접촉구 내의 활성 영역과 접하는 실리사이드의 면적이 넓기 때문에 접촉 저항이 감소한다. 또한 질화막을 사용하지 않으므로, 산화막의 식각만으로 접촉구를 형성할 수 있어 질화막의 식각시 생성되던 폴리머 형성 문제를 제거할 수 있으며, 종래의 질화막을 사용할 때에 나타나던 핫 캐리어 효과나 임계 전압 변화 등의 문제가 감소한다.Since silicide having a considerably higher selectivity than the nitride film for the oxide film is used as a stop layer on the field oxide film, the loss of the field oxide film can be prevented. Therefore, leakage current can be prevented. And the contact resistance decreases because the area of the silicide in contact with the active region in the contact is large. In addition, since the nitride layer is not used, the contact hole can be formed only by etching the oxide layer, thereby eliminating the polymer formation problem generated during the etching of the nitride layer, and a problem such as a hot carrier effect or a threshold voltage change when using a conventional nitride layer. Decreases.

Claims (5)

반도체 기판에 활성 영역 및 상기 활성 영역과 인접하며 소자 분리 영역인 필드 산화막을 포함하는 구조에 있어서,In a structure comprising a semiconductor substrate comprising an active region and a field oxide film adjacent to the active region and a device isolation region, 상기 활성 영역을 성장시켜 에피-실리콘층을 형성하는 단계,Growing an active region to form an epi-silicon layer, 상기 에피-실리콘층을 제1 실리사이드막으로 변화시키는 단계,Changing the epi-silicon layer to a first silicide layer, 제1 산화막을 증착하는 단계,Depositing a first oxide film, 감광막을 도포하고 패터닝하여 감광막 패턴을 형성하는 단계,Applying and patterning the photoresist to form a photoresist pattern; 상기 감광막 패턴을 마스크로 하여 상기 제1 산화막을 식각하여 상기 제1 실리사이드막을 드러내는 접촉구를 형성하는 단계를 포함하는 반도체 소자의 접촉구 형성 방법.Forming a contact hole for exposing the first silicide layer by etching the first oxide layer using the photoresist pattern as a mask. 제1항에서,In claim 1, 상기 에피-실리콘층이 상기 필드 산화막의 가장자리 안쪽으로까지 성장되도록 하는 반도체 소자의 접촉구 형성 방법.And forming the epi-silicon layer into the edge of the field oxide layer. 제1항에서,In claim 1, 필드 산화막 상부의 상기 제1 실리사이드막이 티타늄 실리사이드, 코발트 실리사이드, 텅스텐 실리사이드 중의 하나로 이루어진 반도체 소자의 접촉구 형성 방법.The method of forming a contact hole in a semiconductor device, wherein the first silicide layer on the field oxide layer is one of titanium silicide, cobalt silicide, and tungsten silicide. 제1항에서,In claim 1, 상기 제1 산화막이 TEOS막, BPSG막, 그리고 TEOS막의 삼중막으로 이루어진 반도체 소자의 접촉구 형성 방법.A method for forming a contact hole in a semiconductor device, wherein the first oxide film is composed of a TEOS film, a BPSG film, and a triple film of a TEOS film. (정정) 제1항에서,(Correction) In paragraph 1, 상기 활성 영역 및 상기 필드 산화막이 형성되어 있는 상기 반도체 기판 위에 폴리 실리콘막을 증착하는 단계,Depositing a polysilicon film on the semiconductor substrate on which the active region and the field oxide film are formed; 상기 폴리 실리콘막 위에 제2 실리사이드막을 형성하는 단계,Forming a second silicide film on the polysilicon film; 상기 제2 실리사이드막 위에 제2 산화막을 증착하는 단계,Depositing a second oxide film on the second silicide film; 상기 폴리 실리콘막, 상기 제2 실리사이드막, 상기 제2 산화막을 식각하여 상기 활성 영역 상에 게이트 패턴을 형성하는 단계, 및Etching the polysilicon layer, the second silicide layer, and the second oxide layer to form a gate pattern on the active region; and 상기 게이트 패턴의 측벽에 질화막 스페이서를 형성하는 단계를, 상기 에피-실리콘층을 형성하는 단계 이전에 수행하는 반도체 소자의 접촉구 형성 방법.Forming a nitride spacer on a sidewall of the gate pattern, before forming the epi-silicon layer.
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