JP2000031166A - Fabrication of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fabrication method for semiconductor device in which a fine resist opening having reverse tapered cross-section can be made in order to form a fine gate length pattern. SOLUTION: An electron beam resist 5 is applied to a semiconductor substrate 50 and a plurality of resist patterns, i.e., a target resist pattern 16 and resist patterns 17, 18 on the opposite sides thereof, are subjected to electron beam BM exposure. Subsequently, it is developed to form resist openings 19 corresponding to the plurality of resist patterns 16, 17, 18 and a gate electrode is formed using the resist opening 19 corresponding to the target resist pattern 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, high electron mobility transistors (HE) have been used.
In an MT (High Electron Mobility Transister), a short gate length (shortening the gate length of a gate electrode) is required in order to increase a cutoff frequency and reduce a noise figure. To meet this demand, electron beam exposure capable of forming a fine pattern is performed.

FIG. 3 is a view for explaining a conventional gate electrode forming process. Referring to FIG. 3, first, FIG.
As shown in FIG. 2, a GaAs layer serving as a channel layer, an AlGaAs layer serving as a secondary electron supply layer, and a high-concentration GaAs layer serving as an ohmic contact layer for source / drain electrodes 3
Are sequentially stacked to form a source / drain electrode 4.
On the MT substrate 50, a positive electron beam resist 5 is applied and baked.

[0006] Next, as shown in FIG. 3 (b), an electron beam exposure BM is performed on the gate forming region 6 to open the gate forming portion. Next, as shown in FIG.
After washing with water and drying, an opening pattern (resist opening) 9 is formed in the resist 5. Next, as shown in FIG. 3D, etching is performed through the resist opening 9 and G
A recess groove 10 is formed in the aGaAs layer 3 and the AlGaAs layer 2 is formed.
To expose. Next, after a metal wiring layer 11 serving as a metal for a gate electrode is laminated on the entire surface of the substrate, as shown in FIG. 3E, only the metal 11 deposited on the bottom surface 12 of the The metal wiring layer 11 thereon is removed by a lift-off method.

[0005]

However, according to the method for manufacturing a semiconductor device described above, the document "Mo
dern GaAs Processing Methods p143-p145 "
In order to form a fine opening pattern of about 0.3 μm or less, even if the exposure condition and the development condition of the electron beam exposure are adjusted, the resist opening 9 does not have a reverse taper, In the last lift-off step of the above-described manufacturing process, the metal 11 deposited on the bottom surface 12 of the recess groove 10 may be peeled off together with the unnecessary metal, and there is a problem that the manufacturing yield is very poor.

It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of forming a fine resist opening having a reverse tapered cross section in order to form a fine gate length pattern.

[0007]

According to a first aspect of the present invention, an electron beam resist is applied on a semiconductor substrate, and a desired resist pattern is formed on the electron beam resist. A plurality of resist patterns with the resist patterns on both sides are subjected to electron beam exposure and then developed to form resist openings corresponding to each of the plurality of resist patterns, and then a resist corresponding to a desired resist pattern is formed. A process for forming a gate electrode is performed using the opening.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, an electron beam for forming a resist pattern on both sides of an intended electron beam irradiation amount for forming a resist pattern. It is characterized in that the irradiation amount is increased.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first aspect, the distance between the target resist opening and the resist openings on both sides thereof is reduced.
It is characterized in that the width is not more than 10 times the width of the intended resist opening.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

The inventor of the present application has exposed an electron beam resist to an isolated fine line pattern by electron beam exposure, and an electron beam exposure to a plurality of fine line patterns in close proximity of about 1 μm. It has been found that the cross-sectional shape of the resist pattern in the portion changes. Table 1 shows the experimental results, namely, an isolated thin line pattern (isolated pattern), three thin line patterns (multiple patterns (three)),
In each of the five fine line patterns (a plurality of patterns (five patterns)), the upper opening width and the lower opening width of the resist pattern (resist opening) when electron beam exposure is performed are shown.

[0012]

[Table 1]

From Table 1, it can be seen that in the isolated pattern, the upper opening width and the lower opening width are almost the same, but in the case of a plurality of patterns, the lower opening width is wider than the upper opening width. This is considered to be due to the fact that the incident electrons collide with the substrate and are reflected and the electron beam irradiation amount under the resist increases in the case of a plurality of drawing patterns than in the case of the isolated drawing pattern.

Thus, in the method of manufacturing a semiconductor device according to the present invention, a positive electron beam resist is applied on a semiconductor substrate, the electron beam resist is exposed to an electron beam, a resist pattern is formed, and then developed. When forming a resist opening corresponding to the resist pattern, a resist pattern is formed on both sides of the target resist pattern by electron beam exposure. That is, in the present invention, an electron beam resist is applied on a semiconductor substrate, and the electron beam resist is
After forming a resist opening corresponding to each of the plurality of resist patterns by subjecting a plurality of resist patterns of the desired resist pattern and the resist patterns on both sides thereof to electron beam exposure and then performing development,
A process for forming a gate electrode is performed using a resist opening corresponding to a target resist pattern.

At this time, the amount of electron beam irradiation for forming a resist pattern on both sides is made larger than the amount of electron beam irradiation for forming a desired resist pattern.

Further, the distance between the target resist opening and the resist openings on both sides thereof is set to be within 10 times the width of the target resist opening.

FIG. 1 is a view showing a first example of a manufacturing process of a semiconductor device according to the present invention. In the example of FIG. 1, a HEMT substrate is used as the substrate. In this first example of the manufacturing process, as shown in FIG.
An As layer 1, an AlGaAs layer 2 serving as a secondary electron supply layer, and a high-concentration GaAs layer 3 serving as an ohmic contact layer of source / drain electrodes are sequentially laminated, and a positive electrode is formed on a HEMT substrate 50 on which source / drain electrodes 4 are formed. Type electron beam resist 5 (ZEP520 (manufactured by Zeon Corporation)) with a thickness of 20
Then, the film is baked in a nitrogen atmosphere at a temperature of 200 ° C. for 30 minutes.

Next, as shown in FIG. 1B, a resist pattern 16 having an opening width of 0.1 μm and resist patterns 17 and 18 having an opening width of 0.1 μm are formed on both sides thereof. An electron beam exposure BM is performed. Here, the resist pattern 16 and the resist pattern 17,
The interval between the two was 1 μm.

Next, as shown in FIG. 1C, the developer ZE
Develop with D-50N (manufactured by Zeon Corporation) for about 3 minutes to form resist openings 19 corresponding to the respective resist patterns 16, 17, and 18. Thereafter, rinsing with isopropyl alcohol is performed for 1 minute. By providing the resist patterns 17 and 18 on both sides of the target resist pattern 16, the developed pattern, that is, the resist opening 19 has an inverted tapered shape as shown in FIG.

Next, as shown in FIG. 1D, a recess groove is etched by a citric acid-based etchant through the resist opening 19 to form a recess groove 20 in the GaAs layer 3. The AlGaAs layer 2 is exposed. Next, after a metal layer 21 serving as a metal for a gate electrode is laminated on the entire surface of the substrate, as shown in FIG. 3E, only the metal 21 deposited on the bottom surface 22 of the recess groove 20 is left, and the The upper metal layer 21 is removed by a lift-off method. That is, the gate electrode metal Ti / A
After 3000 μ of u is deposited, as shown in FIG. 2E, lift-off is performed while leaving only the metal 21 deposited on the bottom surface 22 of the recess groove 20.

According to the example of the manufacturing process shown in FIG. 1 (first example of manufacturing process), by providing resist patterns 17 and 18 on both sides of a target resist pattern 16 respectively, backscattering of electron beams during electron beam exposure. Act on each other's patterns to reliably obtain the resist patterns 16, 17, and 18 having the reverse tapered shape. Therefore, when the resist patterns are developed, the resist openings 1 having the reverse tapered shape are formed.
9 can be obtained. Thereby, in the last lift-off step of the above-described manufacturing process, the metal 21 deposited on the bottom surface 22 of the recess groove 20 together with the unnecessary metal can be effectively prevented from peeling off, and the yield of the gate electrode lift-off step is greatly improved. be able to.

FIG. 2 is a diagram showing another example of the manufacturing process of the semiconductor device according to the present invention. In the second example of the manufacturing process, as shown in FIG.
AlGaAs layer 2 serving as a secondary electron supply layer, high-concentration GaAs serving as an ohmic contact layer for source / drain electrodes
A positive type electron beam resist 5 (ZEP520 (manufactured by Zeon Corporation)) is applied to a thickness of 5000 ° on the HEMT substrate 50 on which the source / drain electrodes 4 are formed by sequentially laminating the s-layers 3, Bake in a nitrogen atmosphere for 30 minutes.

Next, as shown in FIG. 2B, an electron beam is formed to form a desired pattern 26 having an opening width of 0.1 μm and resist patterns 27 and 28 having an opening width of 0.1 μm on both sides thereof. Exposure BM is performed. Here, the distance between the resist pattern 26 and the resist patterns 27 and 28 was 1 μm. At this time, the resist patterns 27 and 2
The exposure amount of No. 8 was 1.5 times the exposure amount of the resist pattern 26.

Next, as shown in FIG. 2C, the developer ZE
Develop with D-50N (manufactured by Zeon Corporation) for about 3 minutes to form a resist opening 29. Thereafter, rinsing with isopropyl alcohol is performed for 1 minute. As in the first manufacturing process example, by providing the resist patterns 27 and 28 on both sides of the target resist pattern 26, the developed pattern, that is, the resist opening 29 is formed as shown in FIG. It became reverse tapered. Further, in the second example of the manufacturing process, the exposure amount of the resist patterns 27 and 28 is set to 1.5 times the exposure amount of the resist pattern 26, so that as shown in FIG. The opening width of the lower portion of the resist is larger and wider only in the corresponding resist opening 29.

Next, as shown in FIG. 2D, etching for forming a recess is performed with a citric acid-based etchant through the resist opening 29 to form a recess groove 30 in the GaAs layer 3, and an AlGaAs is formed on the surface of the substrate. The layer 2 is exposed. Next, the gate electrode metal Ti / Au is coated with 300
After depositing 0 °, as shown in FIG.
Is lifted off, leaving only the metal 31 deposited on the bottom surface 32 of the substrate.

Thus, in this second example of the manufacturing process,
Resist patterns 27 and 28 are provided on both sides of the target resist pattern 26, and the resist patterns 26 and 28
In this case, the reverse taper angle of the target resist pattern 26 can be increased, and the corresponding reverse taper angle of the resist opening 9 can be further increased. In the last lift-off step, the metal 3 deposited on the bottom surface 32 of the recess groove 30 is removed.
1 can be effectively prevented, and the yield of the gate electrode lift-off step can be significantly improved.

In the above-described first and second examples of the manufacturing process, an example in which AlGaAs / GaAs HEMT is used as the substrate has been described.
GaAs HEMT, AlGaAs / InGaAs pH
EMT or GaAs MESFET, InP ME
The present invention can be similarly applied to the case where a substrate such as an SFET is used, and the same effects as those obtained when AlGaAs / GaAs HEMT is used can be obtained. In particular,
INDUSTRIAL APPLICATION This invention is suitable for formation of the resist pattern used for manufacture of a gate electrode for HEMT and MESFET.

[0028]

As described above, according to the first aspect of the present invention, since the resist pattern is provided on both sides of the target resist pattern, the resist opening corresponding to the target resist pattern is formed. Shape can be inverted-tapered, which effectively prevents the metal deposited on the bottom of the recess groove from peeling off in the last lift-off process of the manufacturing process, greatly improving the yield of the gate electrode lift-off process. Can be done.

According to the second aspect of the present invention, the amount of electron beam irradiation for forming a resist pattern on both sides is larger than the amount of electron beam irradiation for forming a desired resist pattern. The angle of the reverse taper of the resist opening corresponding to the resist pattern to be made can be further increased, and in the last lift-off step of the manufacturing process, the peeling of the metal deposited on the bottom of the recess groove can be more effectively performed. Thus, the yield of the gate electrode lift-off step can be significantly improved.

According to the third aspect of the present invention, the distance between the target resist opening and the resist openings on both sides of the target resist opening is set to 10 times the width of the target resist opening.
Since it is less than twice, the reflection of electrons from the substrate effectively acts on the adjacent pattern, and the resist shape can be made into an inversely tapered shape.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a view showing another example of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a diagram showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 GaAs substrate 2 high concentration AlGaAs layer 3 high concentration GaAs layer 4 source / drain electrode 5 electron beam resist 16, 26 target pattern 17, 18, 27, 28 pattern on both sides 19, 29 resist opening 20, 30 recess groove 21, 22 Gate electrode

Claims (3)

[Claims] An electron beam resist is applied on a semiconductor substrate, and a plurality of resist patterns of a target resist pattern and resist patterns on both sides thereof are exposed to the electron beam resist, and then developed. Forming resist openings corresponding to each of the plurality of resist patterns, and then performing a process for forming a gate electrode using the resist openings corresponding to the target resist pattern. A method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the amount of electron beam irradiation for forming a resist pattern on both sides is larger than the amount of electron beam irradiation for forming a target resist pattern. Manufacturing method of a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the distance between the target resist opening and the resist openings on both sides thereof is within 10 times the width of the target resist opening. A method of manufacturing a semiconductor device.