JPS63107071A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS63107071A JPS63107071A JP25300286A JP25300286A JPS63107071A JP S63107071 A JPS63107071 A JP S63107071A JP 25300286 A JP25300286 A JP 25300286A JP 25300286 A JP25300286 A JP 25300286A JP S63107071 A JPS63107071 A JP S63107071A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- contact layer
- insulative film
- layer region
- sidewall
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- -1 silicon ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
- H01L29/66863—Lateral single gate transistors
- H01L29/66878—Processes wherein the final gate is made before the formation, e.g. activation anneal, of the source and drain regions in the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電界効果トランジスタの製造方法忙関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a field effect transistor.
従来、電界効果トランジスタのコンタクト層は、第４図
に示すように基板５１に活性層領域５２、ゲート５３を
形成後、薄い絶縁膜を付着し、リアクティブイオンエツ
チングを行なってゲート５３に側壁５４を形成し、ゲー
ト５３と側壁５４をマスクにしてイオンビーム５５を照
射することによってコンタクト層領域５６を形成した後
、アニールによって活性層領域５２、コンタクト層領域
４５６を活性化して形成していた。Conventionally, the contact layer of a field effect transistor is formed by forming an active layer region 52 and a gate 53 on a substrate 51 as shown in FIG. After forming a contact layer region 56 by irradiating with an ion beam 55 using the gate 53 and sidewalls 54 as masks, the active layer region 52 and contact layer region 456 are activated and formed by annealing.
上述した従来の製造方法では、ゲートを中心としてコン
タクト層を非対称だ形成することは困難であり、ソース
抵抗を増加させずに帰還容量を低減し、ドレイン耐圧を
向上することは容易でなかった。In the conventional manufacturing method described above, it is difficult to form a contact layer asymmetrically around the gate, and it is not easy to reduce feedback capacitance and improve drain breakdown voltage without increasing source resistance.
この発明の目的は、上記の従来方法の欠点を除去し、帰
還容量を低減し、ドレイン耐圧を向上させた電界効果ト
ランジスタの製造方法を提供である。An object of the present invention is to provide a method for manufacturing a field effect transistor that eliminates the drawbacks of the above-mentioned conventional methods, reduces feedback capacitance, and improves drain breakdown voltage.
第１図は、この発明の原理説明図である。まず、第１図
（ａｌに示すように基板１に活性層領域２およびゲート
３を形成後、厚さｔｌの第１絶縁膜４を付着する。その
後フォトリングラフィ技術を用いて、第１図（ｂ）の側
壁膜５のように加工した後、厚さｔ２の第２絶縁膜６を
付着する。FIG. 1 is an explanatory diagram of the principle of this invention. First, as shown in FIG. 1 (al), after forming an active layer region 2 and a gate 3 on a substrate 1, a first insulating film 4 having a thickness tl is deposited. After processing like the sidewall film 5 in (b), a second insulating film 6 having a thickness of t2 is deposited.
次いで、選択性のエツチングにより第１図（Ｃ）のよう
釦側壁７及び側壁８を形成し、ゲート３、側壁７及び側
壁８をマスクとしてイオンビーム９によってコンタクト
層領域ｌＯを形成する。コンタクト層領域１０は、側壁
７と側壁８の厚さの違いにより自己整合的にゲートを中
心として非対称となる。Next, a button sidewall 7 and a sidewall 8 are formed by selective etching as shown in FIG. 1C, and a contact layer region 1O is formed by an ion beam 9 using the gate 3, sidewall 7, and sidewall 8 as a mask. Contact layer region 10 becomes asymmetrical with respect to the gate in a self-aligned manner due to the difference in thickness between sidewalls 7 and sidewalls 8 .
次に本発明を実施例によって詳細に説明する。 Next, the present invention will be explained in detail by way of examples.
第２図は本発明の第１の実施例の工程を示す断面図であ
る。まず、ＱａＡｓ基板１１Ｖｃ活性層領域１２及びゲ
ート１３を形成した後、厚さ２００ＯＡ程度の酸化膜１
４を付着後レジストを塗布し露光現像処理を行なって第
２図（ａ）のような形状のレジスト１５を形成する。次
いで、フッ酸の希釈液によってレジスト１５の下坂外の
酸化膜１４を除去する。その後レジス）１５を除去し、
厚さ１００ＯＡ程度の酸化膜を付着し、全面をリアクテ
ィブイオンエツチングすることＫより第２図（ｂ）のよ
うに非対称な側壁１６．１７を形成した後、ゲート１３
、側壁１６および１７をマスクとしてシリコンイオンを
注入しコンタクト層領域１９を形成する。その後は側壁
１６側壁１７の除去、アニールオーミック電極形成の各
工程を経て、第２図（Ｃ）のようにコンタクト層２１が
ゲート１３に近い方をソース電極２４、コンタクト層２
１がゲート１３に遠い方をドレイン電極２５とする電界
効果トランジスタが作成できる。FIG. 2 is a sectional view showing the steps of the first embodiment of the present invention. First, after forming the QaAs substrate 11Vc active layer region 12 and gate 13, an oxide film 1 with a thickness of about 200 OA is formed.
4, a resist is applied and exposed and developed to form a resist 15 having a shape as shown in FIG. 2(a). Next, the oxide film 14 outside the lower slope of the resist 15 is removed using a diluted hydrofluoric acid solution. After that, remove Regis) 15,
After depositing an oxide film with a thickness of about 100 OA and performing reactive ion etching on the entire surface to form asymmetric side walls 16 and 17 as shown in FIG.
, using sidewalls 16 and 17 as masks, silicon ions are implanted to form contact layer region 19. After that, the side walls 16 and 17 are removed, and the annealed ohmic electrode is formed.As shown in FIG.
A field effect transistor can be created in which the drain electrode 25 is the one farthest from the gate 13.
このような電界効果トランジスタはドレイン側のコンタ
クト層２１とゲート１３の距離が従来のものより長くな
っているため帰還容量が低減し、かつドレイン耐圧が向
上する。さらに、このような工程は１つの基板内に多数
のトランジスタを均一性よく作製できる。In such a field effect transistor, the distance between the contact layer 21 on the drain side and the gate 13 is longer than in the conventional transistor, so that the feedback capacitance is reduced and the drain breakdown voltage is improved. Furthermore, such a process allows a large number of transistors to be manufactured with good uniformity within one substrate.
第３図は本発明の＠２の実施例ｊの工程を示す断面図で
ある。ＧａＡｓ基板３１１Ｃ活性層領域３２およびゲー
ト３３を形成した後、酸化膜を付着しる。次に、ゲート
３３と酸化膜３４をマスクとしてシリコンイオンの注入
によシ、コンタクト層領域３６を形成する。その後前述
の第１の実施例と同様に薄い酸化膜を付着し同様の工程
を経て第３図（ｂ）のような電界効果トランジスタを作
製する。FIG. 3 is a sectional view showing the process of Example j of @2 of the present invention. After forming the active layer region 32 and gate 33 on the GaAs substrate 311C, an oxide film is deposited. Next, a contact layer region 36 is formed by implanting silicon ions using the gate 33 and the oxide film 34 as a mask. Thereafter, a thin oxide film is deposited in the same manner as in the first embodiment described above, and a field effect transistor as shown in FIG. 3(b) is manufactured through the same steps.
この実施例では、コンタクト層３８がノース電極４２側
のゲート３３端直下まであるため、ソース抵抗の低減が
可能でトランジスタの特性が向上するという利点がある
。In this embodiment, since the contact layer 38 extends to just below the end of the gate 33 on the north electrode 42 side, there is an advantage that the source resistance can be reduced and the characteristics of the transistor are improved.
以上説明したように本発明は、電界効果トランジスタの
コンタクト層をゲートを中心として自己整合的忙非対称
忙作成できることによりトランジスタの帰還容量を低減
しドレイン耐圧の向上を図った多数のトランジスタを均
一性良く作製するととができる。As explained above, the present invention allows the contact layer of a field effect transistor to be formed in a self-aligned asymmetric manner around the gate, thereby reducing the feedback capacitance of the transistor and improving the drain breakdown voltage. When made, it forms a tong.
このような電界効果トランジスタは、ミリ波帯等の高周
波領域において広い利用が期待されるものである。Such field effect transistors are expected to be widely used in high frequency regions such as millimeter wave bands.
第１図伸）〜（Ｃ）はこの発明の原理説明図、ｖｇ２図
（ａ）〜（Ｃ）はこの発明の第１の実施例の工程断面図
、第３図（ａ）〜（ｂ）はこの発明の第２の実施例の工
程断面図、第４図は従来技術の説明図である。
図中、１．５１−−−−・一基板、１１．３１ ・−−
−−−ＧａＡｓ基板、２．１２．３２．５２・・−・・
活性層領域、３．１３．３３゜５３−・・・・・ゲート
、４・・・・・・第１絶縁膜、５・・・・・・＃ｌ壁膜
、６・・・・・・第２絶縁膜、７．８．．１６．１７．
５４−−−−−・側壁、９．５５・・・・・・イオンビ
ーム、１０．１９．３６．５６・・・・・・コンタクト
層領域、１４．３４・・・・・・酸化膜、１５・・・・
・・レジスト、１８．３５・・・・・・シリコンイオン
ビーム、２０、３７・・・・・・活性層、２１・・・・
・・コンタクト層、２２゜４０・・・・・・オーミック
金属、２３．４１・・・・・・絶縁膜、２４゜４２・・
・・・・ソース電極、２５．４３・・・・・・ドレイン
電極、３８．３９・・・・・・コンタクト層。
イオンビーム
ｙｆ！ｉｆ図
筋２図
↓ ↓ φ ↓ ｊ φ １ ψ ↓ ↓ ↓ ↓ ↓
箔３図Figures 1) to (C) are explanatory diagrams of the principle of this invention, Figures 2 (a) to (C) are process sectional views of the first embodiment of this invention, and Figures 3 (a) to (b) 4 is a process sectional view of the second embodiment of the present invention, and FIG. 4 is an explanatory diagram of the prior art. In the figure, 1.51---- one board, 11.31---
---GaAs substrate, 2.12.32.52...
Active layer region, 3.13.33°53-...Gate, 4...First insulating film, 5...#l wall film, 6... Second insulating film, 7.8. ．． 16.17.
54---- Side wall, 9.55... Ion beam, 10.19.36.56... Contact layer region, 14.34... Oxide film, 15...
...Resist, 18.35...Silicon ion beam, 20, 37...Active layer, 21...
...Contact layer, 22°40...Ohmic metal, 23.41...Insulating film, 24°42...
...Source electrode, 25.43...Drain electrode, 38.39...Contact layer. Ion beam yf! If diagram plot 2 ↓ ↓ φ ↓ j φ 1 ψ ↓ ↓ ↓ ↓ ↓
Foil figure 3
Claims (1)
第１の絶縁膜を設ける工程と、第１の絶縁膜を設けた基
板表面全面に第２の絶縁膜を設ける工程と、ゲート側壁
の絶縁膜以外の絶縁膜を選択的にエッチングして除去す
る工程と、ゲートおよびその両側の側壁絶縁膜をマスク
としてイオンビームを注入してコンタクト層領域を形成
する工程とを含む電界効果トランジスタの製造方法。A step of providing a first insulating film on one side of the substrate surface on which the gate is formed from the center of the gate, a step of providing a second insulating film over the entire surface of the substrate on which the first insulating film is provided, and insulating the side walls of the gate. A method for manufacturing a field effect transistor, comprising the steps of selectively etching and removing an insulating film other than the film, and forming a contact layer region by implanting an ion beam using the gate and sidewall insulating films on both sides as masks. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25300286A JPS63107071A (en) | 1986-10-23 | 1986-10-23 | Manufacture of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25300286A JPS63107071A (en) | 1986-10-23 | 1986-10-23 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63107071A true JPS63107071A (en) | 1988-05-12 |
Family
ID=17245120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25300286A Pending JPS63107071A (en) | 1986-10-23 | 1986-10-23 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107071A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0220030A (en) * | 1988-07-07 | 1990-01-23 | Nec Corp | Manufacture of field effect transistor |
| US5001077A (en) * | 1989-11-08 | 1991-03-19 | Mitsubishi Denki Kabushiki Kaisha | Method of producing an asymmetrically doped LDD MESFET |
| JPH043434A (en) * | 1990-04-19 | 1992-01-08 | Mitsubishi Electric Corp | Field effect transistor and manufacture thereof |
| EP0598711A2 (en) * | 1989-04-12 | 1994-05-25 | Mitsubishi Denki Kabushiki Kaisha | MESFET source/drain structure |
| US5512499A (en) * | 1991-03-01 | 1996-04-30 | Motorola, Inc, | Method of making symmetrical and asymmetrical MESFETS |
| US11155531B2 (en) * | 2016-03-14 | 2021-10-26 | Neostrata Company, Inc. | N-lipoic-amino acid or peptide, derivatives and their uses |
-
1986
- 1986-10-23 JP JP25300286A patent/JPS63107071A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0220030A (en) * | 1988-07-07 | 1990-01-23 | Nec Corp | Manufacture of field effect transistor |
| EP0598711A2 (en) * | 1989-04-12 | 1994-05-25 | Mitsubishi Denki Kabushiki Kaisha | MESFET source/drain structure |
| EP0598711A3 (en) * | 1989-04-12 | 1994-08-24 | Mitsubishi Electric Corp | Mesfet source/drain structure. |
| US5376812A (en) * | 1989-04-12 | 1994-12-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US5001077A (en) * | 1989-11-08 | 1991-03-19 | Mitsubishi Denki Kabushiki Kaisha | Method of producing an asymmetrically doped LDD MESFET |
| JPH043434A (en) * | 1990-04-19 | 1992-01-08 | Mitsubishi Electric Corp | Field effect transistor and manufacture thereof |
| US5296398A (en) * | 1990-04-19 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US5344788A (en) * | 1990-04-19 | 1994-09-06 | Mitsubishi Denki Kabushiki Kaisha | Method of making field effect transistor |
| US5510280A (en) * | 1990-04-19 | 1996-04-23 | Mitsubishi Denki Kabushiki Kaisha | Method of making an asymmetrical MESFET having a single sidewall spacer |
| US5512499A (en) * | 1991-03-01 | 1996-04-30 | Motorola, Inc, | Method of making symmetrical and asymmetrical MESFETS |
| US11155531B2 (en) * | 2016-03-14 | 2021-10-26 | Neostrata Company, Inc. | N-lipoic-amino acid or peptide, derivatives and their uses |
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