JPH0247839A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To enable junction of a contact layer at this region to be shallow so as to suppress short channel effect by doing ion implantation with an insulating film, being left at a position adjacent to a gate, as a mask. CONSTITUTION:An insulating film 3 is formed at a insulating substrate 1 having an active layer region 2, and a dummy gate 4 in the required shape is formed on this insulating film 3, and a sidewall film 5 consisting of a third insulating film is formed only at the side face of the gate 4. Next, with the gate 4 and the sidewall films 5 as a mask, the insulating film 3 is etched. And after etching only the sidewall film 5 to remove it, ion implantation is done with the gate 4 and the insulating film 3 being left as a mask, and contact layer regions 6 for a source and a drain are formed. At this time, at the part that the insulating film 3 is existing, ion implantation is more suppressed than other region. Hereby, a region 6 is made shallow for junction at a position adjacent to the gate, and it becomes possible to suppress short channel effect even by short gate lengthening by contraction of a Schottky gate 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and particularly to a method for manufacturing a field effect transistor having a Schottky gate.

[Conventional technology]

An example of a conventional manufacturing method of this type of field effect transistor is shown in FIGS. 3(a) to 3(C).

In this manufacturing method, first, as shown in FIG. 3(a), a silicon oxide film is formed on a GaAs substrate 1 having an active layer region 2, and this is patterned into a gate shape to form a dummy gate 4. .

Next, as shown in FIG. 3(b), impurities are introduced into the substrate 1 using the dummy gate 4 as a mask to form a contact layer region 6A.

Next, as shown in FIG. 3(C), a resist 7 is applied to the entire surface and etched back to form a dummy gate 4.
The dummy gate 4 is then selectively etched away. Then, a Schottky gate metal 8 such as Ti, PL, Au, etc. is deposited on the entire surface, and the resist 7 is removed to form a Schottky gate 8 by a lift-off method.

Needless to say, a field effect transistor can be completed by forming source and drain electrodes after that.

[Problem to be solved by the invention]

In the conventional field effect transistor manufacturing method described above, the contact layer region 6A is formed in a self-aligned manner using the dummy gate 4 as a mask, and then the shore key gate 8 having the same dimensions as the dummy gate 4 is formed. Therefore, a highly doped and deep contact layer region 6A is formed up to the gate end. Therefore, there is a problem in that the short channel effect becomes more pronounced as the gate length is reduced.

An object of the present invention is to provide a method for manufacturing a field effect transistor that suppresses short channel effects.

[Means to solve the problem]

The method for manufacturing a field effect transistor of the present invention includes a step of forming an insulating film on a semi-insulating substrate having an active layer region, a step of forming a dummy gate of a desired shape on the insulating film, and a step of forming a dummy gate on both sides of the dummy gate. forming a sidewall film on the
The method includes a step of etching the insulating film using the sidewall film as a mask, and a step of removing the sidewall film and forming a contact layer region by ion implantation using at least the dummy gate and the insulating film as a mask.

[Effect]

In the above manufacturing method, the insulating film left adjacent to the gate is used as a mask for ion implantation, so the contact layer junction in this region can be made shallow, resulting in a field effect transistor that suppresses short channel effects. can be manufactured.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are vertical sectional views showing the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), a G
A thin layer 3 of about 500 to 1000 members is formed on one As board 1.

Next, as shown in Fig. 1(b), a relatively thick second layer is applied to the entire surface.
The dummy gate 4 is formed by forming an insulating film and patterning it into a gate shape.

Next, as shown in FIG. 1(C), a third insulating film is formed on the entire surface, and this is etched back using an anisotropic etching method such as a reactive ion etching method.
A sidewall film 5 made of a third insulating film is formed only on the side surface of the dummy gate 4.

Next, as shown in FIG. 1(d), the insulating film 3 is etched using the dummy gate 4 and the sidewall film 5 as a mask. After removing only the side wall film 5 by etching,
Using the remaining dummy gate 4 and insulating film 3 as masks, silicon ions are implanted to form source and drain contact layer regions 6. At this time, ion implantation is suppressed more in the portion where the insulating film 3 is present than in other regions. Thereafter, active layer region 2 and contact layer region 6 are activated by a conventional method.

Thereafter, as shown in FIG. 1(e), a resist 7 is applied to the entire surface and etched back to expose the dummy gate 4, and then the dummy gate 4 is selectively etched away. Further, in this state, the insulating film 3 is etched.

Then, a Schottky gate 8 is formed by depositing Schottky metal 8 on the entire surface and using a lift-off method to remove the resist 7.
form. Needless to say, source and drain electrodes are formed after this.

In the field effect transistor formed by this method, when forming the source and drain contact layer regions 6, the insulating film 3 exists at the position adjacent to the gate and ion implantation is suppressed. The junction is made shallower at the location adjacent to the gate. Therefore, even by shortening the gate length by reducing the size of the Schottky gate 8, it is possible to suppress the short channel effect.

FIGS. 2(a) to 2(d) are longitudinal sectional views showing the main steps of the second embodiment of the present invention in order of process. Note that the same parts as in the first embodiment are given the same reference numerals.

In this embodiment, FIG. 2(a) shows an insulating film 3 and a dummy film on a GaAs substrate 1 having an active layer region 2, similar to the steps shown in FIGS. 1(a) to (c) of the first embodiment. gate 4
The insulating film 3 is etched by the sidewall 5 formed on the side surface of the dummy gate 4, and the sidewall 5 is removed.

Thereafter, as shown in FIG. 2(b), a thin insulating film is formed over the entire surface and anisotropically etched to form a thin sidewall film 9 on the side surface of the dummy gate 4. The thickness of this side wall film 9 is formed thinner than the side wall 5,
Therefore, it is formed only in the region inside the both ends of the insulating film 3.

Then, in this state, as shown in FIG. 2C, silicon ions are implanted and an activation process is performed to form source and drain contact layer regions 6'. At this time, ion implantation is suppressed by the insulating film 3 at a position adjacent to the gate, but ion implantation is hardly performed at a position adjacent to the gate due to the presence of the thin sidewall film 9.

Thereafter, as shown in FIG. 2(d), the thin sidewall film 9 is removed, and as explained in FIG. 1(e), the dummy gate 4 and insulating film 3 are removed using the resist 7, By forming the Schottky gate 8 and forming the source and drain electrodes by the lift-off method using
A field effect transistor is completed.

In this embodiment, the short channel effect can be suppressed due to the shallow junction of the contact layer region 6' adjacent to the gate 8, and the contact layer region 6'
By being spaced apart from the edge of the gate, there is an advantage that gate capacitance can be reduced and gate breakdown voltage can be improved.

〔Effect of the invention〕

As explained above, the present invention utilizes the insulating film left adjacent to the gate as a mask during ion implantation to form the contact layer region. This has the effect of making the junction shallower and producing a field effect transistor with suppressed short channel effects even with a short gate length.

[Brief explanation of the drawing]

FIGS. 1(a) to (e) are vertical sectional views showing a first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to (d) show a second embodiment of the present invention in the order of manufacturing steps. Longitudinal sectional view, Figure 3 (a
) to (c) are vertical cross-sectional views showing the conventional manufacturing method in the order of steps. 1... GaAs substrate, 2... active layer region, 3...
Insulating film, 4... dummy gate, 5... sidewall film, 6.
6', 6A... Contact layer region, 7... Resist, 8... Gate (Schottky metal), 9... Thin sidewall film. Figure 1! −1ζq , O

Claims (1)

[Claims] 1. A step of forming an insulating film on a semi-insulating substrate having an active layer region, a step of forming a dummy gate of a desired shape on this insulating film, a step of forming sidewall films on both sides of the dummy gate, The method includes the steps of etching the insulating film using the sidewall film as a mask, and forming a contact layer region by ion implantation after removing the sidewall film and using at least the dummy gate and the insulating film as a mask. A method for manufacturing a field effect transistor.