JPH05291301A - Field-effect transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide the method for manufacturing a field effect transistor which has no increase in source resistance but has the increased gate drain withstand voltage and which has a fine gate electrode formed stably in a recess. CONSTITUTION:Before forming a recess in a semiconductor layer, an isolation layer 4 of the specified thickness is formed by ion implantation in a specified region at the side of a drain electrode 2 of an n-type GaAs layer 5 between a source electrode 1 and the drain electrode 2. After that, a one step recess 8 which is thicker than the isolation layer 4 is formed in a specified region of the n type GaAs layer 5 between the source electrode 1 and the drain electrode 2. Using a resist pattern which was used in formation of the recess 8, a gate electrode 3 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a field effect transistor having a high gate / drain withstand voltage and a low source resistance and having a fine gate electrode. The present invention relates to a transistor and its manufacturing method.

[0002]

2. Description of the Related Art FIG. 4 is a cross-sectional view showing a manufacturing process of a conventional two-step recess type field effect transistor, in which 1 is a source electrode, 2 is a drain electrode, 3 is a gate electrode, and 3a is Gate metal, 5 is an n-type GaAs layer, 7,
10 is a resist pattern, 11 is a first-stage recess, 12
Is the second recess.

A method of manufacturing the above-mentioned two-step recess type field effect transistor will be described below with reference to this drawing. First, after forming the source electrode 1 and the drain electrode 2 respectively in predetermined regions of the n-type GaAs layer 5, a resist is applied to the entire surface of the n-type GaAs layer 5, and the photolithography and etching techniques are used to form the resist. The resist is patterned to form a resist pattern 10 in which the source electrode 1 and the drain electrode 2 are covered and an opening is formed to form a recess in the first stage. After that, when the n-type GaAs layer 5 is wet-etched using the resist pattern 10 as a mask, n-type GaAs layer 5 as shown in FIG.
The first-stage recess 11 is formed in a predetermined region of the type GaAs layer 5 between the source electrode 1 and the drain electrode 2. Next, the resist pattern 10 is removed, a new resist is applied on the n-type GaAs layer 5, and the resist is patterned by using ordinary photoengraving and etching techniques.
As shown in (b), a resist pattern 7 having an opening for forming the recess of the second step is formed in the center of the recess 11 of the first step. Next, the n-type GaAs layer 5 is wet-etched using the resist pattern 7 as a mask to form a recess 12 in the second stage, and then the n-type GaAs is formed.
When the gate metal 3a is deposited on the entire surface of the layer 5, as shown in FIG.
As shown in (c), the gate electrode 3 having a predetermined gate length corresponding to the width of the opening of the resist pattern 7 is
It is formed on the upper surface of the recess 12 in the second step. Then, after removing the resist pattern 7 and the gate metal 3a deposited on the upper surface, the two-step recess of the n-type GaAs layer 5 between the source electrode 1 and the drain electrode 2 is removed as shown in FIG. 4 (d). (Recesses 11 of the first stage and recesses 12 of the second stage) are formed, and a field effect transistor in which the gate electrode 3 is formed for these two-stage recesses is obtained.

The device structure in which the gate electrode is formed in such a two-step recess improves the efficiency of the transistor and
This is performed in order to increase the reverse breakdown voltage for improving reliability, and is generally used as a device structure of a field effect transistor that constitutes a high output amplifier.

[0005]

A conventional two-stage recess type field effect transistor is obtained by the above manufacturing process.
As shown in FIG. 4B, the resist pattern 7 having an opening for forming the recess 12 in the second step and the gate electrode 3 in a predetermined width is formed into an n-type resist 11 in which the recess 11 in the first step is formed. G
It needs to be formed on the upper surface of the aAs layer 5.

However, when the resist pattern 7 is formed on the upper surface of the n-type GaAs layer 5 in which the recess 11 of the first step is formed, the resist formed on the upper surface of the n-type GaAs layer 5 is the first step. Since a uniform film thickness is not formed due to the influence of the stepped portion of the recess 11, the opening width and shape of the resist having an uneven film thickness are formed with high precision. In particular, it becomes impossible to accurately form an opening for forming a fine gate electrode having an opening width of 1 μm or less. As a result, the gate electrode obtained using the resist pattern 7 as a mask 3 is not stably formed on the n-type GaAs layer 5,
Further, since the size and the shape are not uniform, the obtained transistor has a problem that the reliability is lowered, the device characteristics are varied, and the manufacturing yield is lowered.

The two-stage recess type field effect transistor thus obtained has a two-stage recess structure.
Although the distance between the formation regions of the drain electrode 2 and the gate electrode 3 on the surface of the n-type GaAs layer 5 becomes long and the breakdown voltage between the gate and the drain can be increased, the distance between the formation regions of the source electrode 1 and the gate electrode 3 is also increased. Since it becomes longer, the n-type G
There is a problem that the surface depletion layer formed on the surface of the aAs layer 5 extends in the lateral direction and becomes long, and the source resistance increases.

The present invention has been made in order to solve the above problems, and has a high gate / drain breakdown voltage as high as that of a two-stage recess type field effect transistor without increasing the source resistance. An object of the present invention is to obtain a field effect transistor having a device structure that can be realized and a method for manufacturing the same.

Further, another object of the present invention is that the source resistance is small and the gate / drain breakdown voltage is as high as the conventional two-step recess type field effect transistor.
Moreover, a highly efficient and highly reliable field effect transistor in which a fine gate electrode with high dimensional accuracy is stably formed,
It is an object to obtain a manufacturing method capable of manufacturing the transistor with high yield.

[0010]

In the field effect transistor according to the present invention, the recess of the recess type gate electrode is formed by a one-step recess, and the recess of the recess is formed in the semiconductor layer between the recess and the drain electrode. An isolation layer having a depth smaller than the depth is formed.

In the method for manufacturing a field effect transistor according to the present invention, before forming the recess in the semiconductor layer, a recess region is formed in a predetermined region between the source electrode and the drain electrode on the drain electrode side of the semiconductor layer by an ion implantation method. Forming an isolation layer with a depth smaller than
A one-step recess is formed in a predetermined region of the semiconductor layer between the source electrode and the drain electrode, and a gate electrode is formed using the resist pattern used for forming the one-step recess. ..

Further, in the method for manufacturing a field effect transistor according to the present invention, the source electrode is formed on a predetermined region of the semiconductor layer,
After forming the drain electrode and forming the recess type gate electrode in a predetermined region of the semiconductor layer between the source electrode and the drain electrode, the surface thereof is formed on the semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode. A flattened insulating film or resist is deposited, and a resist pattern having an opening is formed on the insulating film or resist at a portion corresponding to the upper portion between the gate electrode and the drain electrode. After that, the resist pattern is used as a mask. Ion implantation is performed on the semiconductor layer through the insulating film to form an isolation layer having a depth smaller than the depth of the recess in a predetermined region on the drain electrode side in the semiconductor layer between the source electrode and the drain electrode. It is the one.

[0013]

According to the present invention, the recess for forming the gate electrode is formed in one stage, and the isolation layer having a depth smaller than the depth of the recess is provided in the semiconductor layer between the gate electrode and the drain electrode. It is possible to increase the breakdown voltage of the gate / drain to the same extent as the conventional two-step recess without forming, and since the recess is one step, the distance between the gate electrode and the source electrode on the surface of the semiconductor is It can be shortened compared to when the two-step recess of
The source resistance can be reduced.

Further, in the present invention, since the gate electrode is formed by using the (one-step) recess forming resist pattern obtained by forming a film on the surface of the semiconductor layer having no step. When the resist pattern is formed, even if the opening to be formed has a fine opening width, it can be adjusted to a desired shape and size with high precision, and a fine gate electrode can be stably formed. ..

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing the structure of a GaAs field effect transistor according to an embodiment of the present invention. In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding parts,
In this GaAs field effect transistor, a recess 8 of one step is formed in a predetermined region of the n-type GaAs layer 5 between the source electrode 1 and the drain electrode 2, a gate electrode 3 is formed there, and further, the gate electrode 3 and N between the drain electrode 2
On the drain electrode 2 side in the type GaAs layer 5, the isolation layer 4 having a depth shallower than the depth of the recess 8 is formed.

FIG. 2 is a cross-sectional view showing the steps of manufacturing the GaAs field effect transistor shown in FIG. 1, in which the same reference numerals as those in FIG. 1 designate the same or corresponding parts, and 3a is a gate metal, and 6 is a gate metal. , 7 are resist patterns.

A method of manufacturing the GaAs field effect transistor will be described below with reference to FIG. First, n-type GaA
After forming the source electrode 1 and the drain electrode 2 in a predetermined region on the s layer 5, a resist is formed on the entire surface of the n-type GaAs layer 5, and the source electrode is formed by using ordinary photoengraving and etching techniques. A resist pattern 6 having an opening is formed on a predetermined region of the n-type GaAs layer 5 between the drain electrode 2 and the drain electrode 2 on the drain electrode 2 side. Next, using the resist pattern 6 as a mask, ions of boron (B), hydrogen (H), etc. are implanted into the n-type GaAs layer 5, and then, as shown in FIG.
As shown in (a), the isolation layer 4 is formed.

Next, the resist 6 is removed, a new resist is formed on the surface of the n-type GaAs layer 5, and a resist pattern 7 having an opening of a predetermined width is formed by using ordinary photoengraving and etching techniques. Then, a recess 8 is formed by wet etching using the resist pattern 7 as a mask, and then a gate metal 3a is deposited on the entire surface of the n-type GaAs layer 5, as shown in FIG. 2 (b). Then, the recess type gate electrode 3 including one step of the recess is formed. Here, in order to prevent the width of the active layer region (channel region) from becoming narrow and the source resistance from increasing, it is necessary to make the depth of the recess 8 larger than the depth of the isolation layer 4.

After that, the resist pattern 7 is formed.
When unnecessary gate metal 3a is removed together with the above, FIG.
As shown in FIG. 5, the transistor having the element structure shown in FIG. 1 can be obtained.

In the manufacturing process of the GaAs field effect transistor of the present embodiment as described above, before the gate electrode 3 is formed, a predetermined region on the drain electrode 2 side of the n-type GaAs layer 5 between the source electrode 1 and the drain electrode 2 is formed. In addition, the isolation layer 2 having a depth shallower than the recess depth by the ion implantation is formed.
Is formed, and thereafter, the recess type gate electrode 3 including the recess 8 of one step is formed in a predetermined region of the n-type GaAs layer 5 between the source electrode 1 and the drain electrode 2. Therefore, when the gate electrode 3 is formed, The resist pattern 7 is formed of a resist having a uniform film thickness formed on the n-type GaAs layer 5 having a flat surface. Even if the opening of the resist pattern 7 is a fine opening, its shape and dimensions The accuracy is stable and a fine gate electrode can be formed with good reproducibility. As a result, the isolation layer 2 increases the breakdown voltage of the gate and drain, and the one-step recess structure allows the n-type GaAs layer 5 to be formed. The distance between the source electrode 1 and the gate electrode 3 on the surface is shortened to reduce the source resistance,
Moreover, a transistor having a fine gate electrode can be manufactured with a high yield.

FIG. 3 shows the G according to the second embodiment of the present invention.
It is sectional drawing which shows the manufacturing process of an aAs field effect transistor, In the figure, the code | symbol same as FIG. 1 and 2 shows the same or equivalent part, 9 is SiO formed by ECRCVD method etc. and the surface was planarized. It is an insulating film consisting of ₂ etc.

The manufacturing process of this GaAs field effect transistor will be described below. First, the source electrode 1, the drain electrode 2, and the (recess type) gate electrode 3 including the recess 8 in one step are formed in predetermined regions of the n-type GaAs layer 5, respectively. Here, the recess 8 and the gate electrode 3 are formed by the same process as in the first embodiment, that is, by using the resist pattern 7 having an opening formed in the resist formed on the surface of the flat n-type GaAs layer 5 as a mask. , N-type GaAs layer 5 is wet-etched, and a gate metal is vapor-deposited. After that, in the state in which the source electrode 1, the drain electrode 2 and the (recess type) gate electrode 3 including the recess 8 of one stage are formed on the n-type GaAs layer 5 as described above, FIG.
, The source electrode 1 is formed by using the ECRCVD method or the like.
An insulating film 9 whose surface is flat is disposed between the gate electrode 3 and the gate electrode 3 and between the gate electrode 3 and the drain electrode 2. Here, the insulating film 9 having a flat surface is formed by the film thickness of the insulating film 9 on the recess 8 and the flat n-type G on the side of the recess 8.
The difference between the thickness of the insulating film 9 on the aAs layer 5 and the thickness of the recess 8 is
This is because the n-type GaAs layer 5 is formed so as to faithfully express the shape.

Next, a resist is applied to the entire surface of the n-type GaAs layer 5, and then the resist is patterned so that an opening is formed above the gate electrode 3 and the drain electrode 2. To form a resist pattern 6,
Next, using the resist pattern 6 as a mask, boron (B), hydrogen (H) and the like are ion-implanted into the n-type GaAs layer 5 between the gate electrode 3 and the drain electrode 2 through the insulating film 9 with a constant implantation energy. Then, as shown in FIG. 3B, the isolation layer 2 having a depth shallower than the depth of the recess 8 is formed in the n-type GaAs layer 5 between the recess 8 and the drain electrode 2. At this time, since the thickness of the insulating film 9 on the recess 8 is thicker than the thickness between the recess 8 and the drain electrode 2, the n-type GaAs layer 5 of the recess 8 is formed by ion implantation having a predetermined constant implantation energy. No ions are implanted into the inside of the n-type GaAs between the recess 8 and the drain electrode 2.
The isolation layer 4 having a depth smaller than the depth of the recess 8 is formed only in the layer 5 in a self-aligned manner. Here, if the surface of the insulating film 9 is not flat, the recess 8 and the drain electrode 2 are formed by ion implantation having a constant implantation energy.
It becomes impossible to faithfully form the isolation layer 4 in a self-aligned manner only in the n-type GaAs layer 5 between them.

Then, after this, the resist pattern 6 is formed.
Are removed, and further, the insulating film 9 is removed by, for example, wet etching, whereby a field effect transistor having an element structure similar to that of the first embodiment shown in FIG. 1 can be obtained.

In the manufacturing process of the GaAs field effect transistor of this embodiment as described above, the source electrode 1, the drain electrode 2 and the one-step recess 8 are formed in a predetermined region of the n-type GaAs layer 5.
(Recess type) of the gate electrode 3 are formed respectively, and then the insulating film 9 is formed to fill the space between the source electrode 1 and the gate electrode 3 and the space between the gate electrode 3 and the drain electrode through the insulating film 9 whose surface is flattened. N is formed between the recess 8 and the drain electrode 2 by performing ion implantation on the surface of the type GaAs layer 5.
Since the isolation layer 4 is formed only in the type GaAs layer 5, the recess 8 and the gate electrode 3 are formed as in the above-described embodiment.
The resist pattern 6 for forming the film can be obtained by forming an opening in a resist having a uniform film thickness. Even if this opening is a fine opening, its shape and dimensional accuracy are stable, and a fine pattern is formed. The gate electrode can be formed with good reproducibility. Therefore, also in this embodiment, similarly to the above-described embodiment, the isolation layer 2 provides a high gate-drain breakdown voltage, and the single-step recess structure allows the source electrode 1 and the gate to be formed on the surface of the n-type GaAs layer 5. The distance between the electrodes 3 is shortened and the source resistance is reduced,
Moreover, a transistor having a fine gate electrode can be manufactured with a high yield.

In the above embodiment, the insulating film whose surface is flat is formed between the source electrode 1 and the gate electrode 3 and between the gate electrode 3 and the drain electrode 2. However, a resist whose surface is flat is used. It may be used, and also in this case, the same effect as that of the above-described embodiment can be obtained.

[0027]

As described above, according to the present invention, the recess of the recess type gate electrode is formed by a single-step recess, and the depth of the recess is smaller than the depth of the recess in the semiconductor layer between the recess and the drain electrode. Since the isolation layer having a small depth is formed, the source resistance does not increase and the
There is an effect that it is possible to obtain a field effect transistor whose gate / drain breakdown voltage is as high as that of the step recess type field effect transistor.

Further, according to the present invention, before the recess is formed in the semiconductor layer, a predetermined region between the source electrode and the drain electrode on the drain electrode side of the semiconductor layer is formed by an ion implantation method to a depth smaller than the depth of the recess. Of the resist pattern used for forming the recess of one step is formed in a predetermined region of the semiconductor layer between the source electrode and the drain electrode. Since the gate electrode is formed by using the gate electrode, the gate / drain breakdown voltage is as high as that of the two-step recess type field effect transistor without increasing the source resistance, and the shape is constant and the dimensional accuracy is high. There is an effect that it is possible to manufacture a highly reliable and high performance field effect transistor having a fine gate electrode having a high yield.

Further, according to the present invention, the source electrode and the drain electrode are formed in a predetermined region of the semiconductor layer, and the recess type gate electrode is formed in the predetermined region of the semiconductor layer between the source electrode and the drain electrode. An insulating film or resist whose surface is flattened is deposited on the semiconductor layer between the electrode and the gate electrode and between the gate electrode and the drain electrode, and the insulating film or resist corresponding to the upper part between the gate electrode and the drain electrode is deposited on the insulating film or resist. A resist pattern having an opening in a portion is formed, and thereafter, ion implantation is performed on the semiconductor layer through the insulating film using the resist pattern as a mask, and a drain electrode side portion in the semiconductor layer between the source electrode and the drain electrode is formed. Since the isolation layer having a depth smaller than the depth of the recess is formed in the predetermined region, the saw layer is formed in the same manner as above. The gate / drain breakdown voltage is as high as that of the two-step recess type field effect transistor without increasing the resistance, and the reliability is provided with a fine gate electrode having a constant shape and high dimensional accuracy. There is an effect that a high-performance field effect transistor can be manufactured with a high yield.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a field effect transistor according to an embodiment of the present invention.

2A to 2D are cross-sectional views for each process showing the manufacturing process of the field effect transistor shown in FIG.

FIG. 3 is a sectional view for each step showing the manufacturing process of the field effect transistor according to the second embodiment of the invention.

4A to 4C are cross-sectional views showing a manufacturing process of a conventional field effect transistor.

[Explanation of symbols]

 1 Source Electrode 2 Drain Electrode 3 Gate Electrode 3a Gate Metal 4 Isolation Layer 5 n-type GaAs Layer 6 Resist Pattern 7 Resist Pattern 8 Recess 9 Recess 9 Insulating Film 10 Resist Pattern 11 First Recess 12 Second Recess

Claims (3)

[Claims] 1. A field effect transistor comprising a source electrode, a drain electrode, and a recess-type gate electrode in a predetermined region of a semiconductor layer, wherein the recess comprises a single-step recess, and the recess and the drain electrode. In the semiconductor layer between
A field effect transistor, wherein an isolation layer having a depth smaller than the depth of the recess is formed. 2. A method of manufacturing a field effect transistor comprising a source electrode, a drain electrode and a recess type gate electrode in a predetermined region of a semiconductor layer, the method comprising: forming a source and drain electrode on an upper surface of the semiconductor layer; Forming a resist pattern on the upper surface of the semiconductor layer in which an opening is located between the source and drain electrodes above the drain electrode side of the semiconductor layer; and using the resist pattern as a mask, ions are applied to the semiconductor layer. Implanting and forming an isolation layer with a predetermined layer thickness in a predetermined region in the semiconductor layer corresponding to the opening of the resist pattern; and after removing the resist pattern, forming the recess type gate electrode A step of forming a new resist pattern having an opening for forming on the semiconductor layer, and the resist pattern. Part of the semiconductor layer is removed by etching using the mask as a mask to form a single-step recess having a depth larger than the depth of the isolation layer, and then the resist pattern is used as a mask for the upper surface of the semiconductor layer. A step of depositing a gate metal and forming a gate electrode on the one-step recess, a method of manufacturing a field effect transistor. 3. A method of manufacturing a field effect transistor comprising a source electrode, a drain electrode and a recess type gate electrode in a predetermined region of a semiconductor layer, the method comprising: forming a source and drain electrode on an upper surface of the semiconductor layer; Forming a resist pattern on the upper surface of the semiconductor layer having an opening above a predetermined region between the source and drain electrodes, and etching a part of the semiconductor layer using the resist pattern as a mask Forming a stepped recess, then
A step of depositing a gate metal on the upper surface of the semiconductor layer using the resist pattern as a mask to form a gate electrode on the one-step recess; and a step between the source and gate electrodes and a step between the gate and drain electrodes. A step of forming an insulating film or a resist whose surface is flattened on the upper surface of the semiconductor layer, and a resist pattern in which an opening is located above the gate and drain electrodes are formed on the source, gate and drain electrodes. Forming on the upper surface of the semiconductor layer having the insulating film or resist whose surface is flattened; and using the resist pattern as a mask, through the insulating film or resist having the flat surface, Ions are implanted into the semiconductor layer, and the recess is formed in a predetermined region in the semiconductor layer between the recess and the drain electrode. Forming a depth smaller than the depth isolation layer, the resist pattern and a method of manufacturing a field effect transistor which comprises a step of its surface to remove the planarized insulating film or a resist.