JPH07193089A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide an FET with a high breakdown voltage and a high gain and realize a high output FET with a high power load efficiency. CONSTITUTION:A lightly-doped region which is gradually spread in an upward direction is formed in a channel layer 2 directly under a gate electrode 6. With this constitution, a channel constriction which is induced between the gate electrode 6 and a drain electrode 8 at the time of a large signal operation can be relieved without making the gate electrode dig itself in the channel layer. Further, the deterioration of a gate breakdown voltage caused by an avalanche breakdown at the gate edge which is induced when the gate electrode is made to dig itself in the channel layer and the increase of the gate capacitance can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a compound semiconductor.

[0002]

2. Description of the Related Art In a high-power GaAs FET, it is necessary to simultaneously improve the gate breakdown voltage and reduce the source resistance in order to improve the power added efficiency. In order to solve this, a two-step recess structure has been generally used conventionally. The structure will be described with reference to FIGS. As shown in FIG. 3A, the channel layer 2 is etched by a wet etching process or a dry etching process using sulfuric acid or hydrogen peroxide solution using the patterned resist film as a mask. After removing the resist film 9, the oxide film 3 is formed on the channel layer 2. A resist film is applied on the oxide film 3 to form a pattern, and the participating film 3 is dry-etched with a gas such as SF ₆ to form a pattern of the gate electrode. As shown in FIG. 3B, the oxide film 3 is used as a mask for C
The channel layer 2 is etched by dry etching with a gas such as HF ₃ . As shown in FIG. 3D, after forming the gate metal film by the sputtering process, the gate electrode pattern is dry-etched to form a two-step recess structure.

This structure has a feature that the sheet carrier concentration between the gate electrode 6 and the drain electrode 8 can be made larger than the sheet carrier concentration below the gate electrode 6 by etching the gate portion. The reason for setting such a sheet carrier concentration is as follows.

In a device that operates a large signal such as a high-power FET, during operation, electrons are trapped by an electron trap at the semiconductor-passivation film interface between the gate electrode 6 and the drain electrode 8, the surface potential increases, and the depletion layer increases. Occurs in the channel layer 2 and the channel layer width is narrowed. The capture time of this electron trap is generally about lmsec or more and cannot be followed during high frequency RF operation. Therefore, the FET operates while the above-mentioned depletion layer keeps the channel layer compressed, which increases the drain resistance during high-frequency RF operation, resulting in a reduction in output and a reduction in power-added efficiency. (Reference 1 (NI
wata et.al .; Gallium Arsenide & Relfted Compounds 1
991, Inst3 Phys. Conf. Set. 120 pp.119-124, Septem
ber 1991), Reference 2 (S. Sriram, et.al.; 1989 IEEE Corn
ell Univ. Conf. Dig., pp.218-227, 1989)). Therefore, from below the gate electrode 6 to the gate electrode 6-drain electrode 8
It is necessary to secure a sufficient amount of charge in the channel and obtain a sufficient drain current even if channel compression occurs during high frequency RF operation by setting the sheet carrier concentration higher than the sheet carrier concentration. In order to obtain such a structure, conventionally, in the etching process of FIG. 5C, etching is performed so that a sufficient charge amount can be secured even if channel depletion occurs due to the depletion layer expansion during the RF operation described above. The quantity is determined. Next, as shown in FIG. 3C, the gate electrode 6 is etched to form the gate electrode 6
The charge amount immediately below is set to a predetermined charge amount. Gate electrode 6
It is possible to set the charge amount on the side of the gate electrode 6 larger than the charge amount below.

[0005]

However, in the conventional structure having the gate recess, the gate withstand voltage is higher than that of the gate electrode 6.
Since it is determined by the avalanche breakdown at the end on the drain electrode side of, the high breakdown voltage is remarkably reduced when a channel layer concentration exceeding 2 × 10 ¹⁷ cm ⁻³ is adopted especially for improving high frequency characteristics. It has a drawback that the breakdown voltage required for output operation cannot be obtained. The relationship between the gate recess depth and the breakdown voltage in the conventional structure (two-step recess structure) is described in Reference 3 (HM Macsey; IEEE Trans. Electron Devices, vol.
ED-33, No.11 pp.1818-1824, 1986),
It has been shown that the gate breakdown voltage decreases as the gate recess amount increases. For this reason, in the case of the same structure, when the amount of gate recess is small, the interface state causes narrowing by the depletion layer in the channel layer to reduce the output and reduce the power addition efficiency. Therefore, it is indispensable to have a recess structure, but if the recess amount is increased, there is a problem that the gate breakdown voltage is lowered as described above and the current addition efficiency is significantly reduced. Further, in the case of the same structure, there is a problem that the gate capacitance increases due to an increase in the amount of burying the gate electrode 6 in the channel layer 2 (Reference 3), resulting in a decrease in power gain.

On the other hand, as a process problem, as shown in the process sectional view of FIG. 5, the pattern forming steps of FIGS. 5A and 5C are based on the lithography technique, and the controllability of the distance between the gate recesses is the same as that of the technique. It is governed by the accuracy of alignment. The withstanding voltage and the maximum drain current are important parameters that determine the power addition effect and the saturated output, but in order to control both of them, it is essential to control the distance between the gate electrode and the recess. For example, in a FET having a gate length of 0.5 μm, if the distance between the gate electrode and the recess differs by 0.1 μm, the gate breakdown voltage fluctuates by 2 V or more. Also, the maximum drain current during RF operation may vary by 5% or more when the distance between the gate electrode and the recess is increased by 0.1 μm due to the above-mentioned narrowing phenomenon. Therefore, there is a problem that the controllability of the breakdown voltage and the drain current becomes insufficient.

An object of the present invention is to provide a field effect transistor which solves the above problems.

[0008]

A field effect transistor according to the present invention includes a compound semiconductor layer (channel layer) doped with an n-type impurity and a region formed in the channel layer and in contact with the channel layer on the region. A non-doped region and a region doped with an n-type impurity at a concentration lower than the n-type impurity concentration of the channel layer, and having a cross-sectional structure that has a shape narrowing from the upper part to the lower part in one or more steps (low-concentration region), A gate electrode having a gate length narrower than the upper dimension of the low concentration region, a source electrode formed on the channel layer, and a drain electrode formed on the channel layer are provided on the low concentration region. I am trying.

The field-effect transistor of the present invention comprises an n-type impurity-doped compound semiconductor layer (channel layer), a region formed in the channel layer, and a region not in contact with the channel layer above and below the region. A region (low-concentration region) in which the cross-sectional structure is gradually narrowed from the upper part to the lower part, which is a region doped with an n-type impurity at a concentration lower than the n-type impurity concentration of the channel layer, and a region above the low-concentration region. A gate electrode having a gate length narrower than an upper dimension of the low-concentration region, and a source electrode formed on the channel layer,
It is characterized in that a drain electrode formed on the channel layer is provided.

[0010]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a field effect transistor (F
FIG. 2 is a process sectional view of this structure.

In the manufacture of this FET, the MBE technique is used to form 3.5 × 10 3 on the semi-insulating GaAs substrate 1.
A channel layer 2 of 3000 A is formed with an impurity concentration of ¹⁷ cm ⁻³ . An oxide film 3 of 3000 A is formed on this channel layer by plasma CVD, and then a pattern of a recess structure having a width of 1.0 μm is formed by a lithography technique. The traveling wave power 130 is applied to the oxide film 3 by using CHF ₃ gas.
Magenetron Ion Etching (M
IE) Process to form a pattern. During this MIE processing, a carrier inactivation region having a depth of 2000 A is formed. The depth of this region can be controlled by the bias condition of the substrate of the MIE device during etching or the etching time after opening. By making the overetching time after opening sufficiently long, the depth of the inactive region tends to be saturated, so that the controllability can be improved.

FIG. 6 shows the carrier profile at this time.

After that, using the pattern of the oxide film 3 as a mask, as shown in FIG.
A wide recess structure with 0A etching is formed.
With this structure, the source resistance and the drain resistance are reduced. However, performing the wide recess is not always essential. Next, FIG sidewall oxide film 5 as shown in (d) and 3000A formed by plasma CVD, as shown in FIG. (E), Elec oxide film 3 by SF ₆ gas
The sidewall oxide film 5 is opened by tron Cycrotron Rescnanace etching (ECR etching). After opening A
Damage is introduced by r ⁺ plasma treatment. Depth of damage can be controlled by substrate bias 350V
Thus, it becomes possible to inactivate a carrier having a depth of 800A.
At this time, the channel layer 2 having a layer thickness of 700 A and 3.5 × 10 ¹⁷ cm ⁻³ is formed. Further, in the low-concentration region 4 below the sidewall oxide film 5, the channel layer 2 having a lateral width of 0.3 μm and a thickness of 1000 A is formed. As shown in FIG. 6F, WSi is formed as the gate electrode 6 by a sputtering process, and after patterning with a resist as shown in FIG. 6G, the gate electrode 6 is formed by a dry etching process. At this time, the T-shaped gate electrode 6 having a gate length of 0.4 μm
Is formed.

Next, as shown in FIG. 1, a source electrode 7 and a drain electrode 8 are formed to complete the FET.

Since the gate electrode 6 is formed in the low-concentration region 4 in the FET of this structure, the electric field concentration at the end of the gate electrode 6 is reduced as compared with the conventional two-step recess structure (FIG. 5). The gate breakdown voltage due to avalanche breakdown at the end of the gate electrode 6 becomes higher than that of the conventional two-step recess structure. Further, in this structure, since the gate recess is not formed, the gate breakdown voltage does not decrease due to the electric field concentration at the gate electrode end due to the formation of the gate recess. Further, the inactive region 4 in the wide recess portion beside the gate electrode 6 is smaller than the inactive region 4 below the gate electrode 6 and the channel layer 2 is formed.
Is big on the contrary. Therefore, even if the narrowing phenomenon of the channel layer 2 during RF operation due to the electron traps at the interface between the inactive region 4 and the oxide film 3 occurs, it is possible to secure a sufficient thickness of the channel layer 2 and the phenomenon of drain current. Does not happen. Therefore, the output does not decrease, and the high output FE with high power added efficiency
It is possible to provide T. With this structure, X-Ku
As a high-power device in the band, a withstand voltage of 18V or higher can be secured, and power added efficiency of 50% or higher
A high-power FET having an output of 50 mW / mm or more can be realized.

The shrimp concentration is determined on the side of scaling with the gate length and the like, and need not be the above concentration. Further, the gate breakdown voltage is also determined by the operating voltage and the like, and since it is related to the characteristics of the passivation film, the damage depth of the surface between the gate electrode and the drain electrode needs to be changed according to the application. Also,
As the deactivation process, another ion processing process may be used, or the etching process may be performed simultaneously. For example, without inactivating in the step of FIG.
It is also possible to introduce damage at the same time as performing recess etching in the process of FIG. Reference 4 (Journal
of Electronic Materifls, Vol.21 No.1 p3, 1992), 30 eV reactive ion beam etchin by C1.
500 at the same time as the recess structure is etched by g (RIBE)
It is possible to form the damaged area A. Also,
Document 5 (Mat. Res. Soc. Proc. Vol.240)
p335, 1992), it is possible to control the sheet carrier concentration by changing the plasma voltage or the etching time by using reactive ion etching using SiCl4 / SiF44 plasma.

Ion processing is not always necessary for forming the low-concentration region, and a region in which the low-concentration region is doped with a low concentration of n-type impurities or a region not doped with impurities is formed by selective epitaxial growth. There is no problem.

Next, another embodiment of the present invention will be described with reference to process sectional views of FIGS. Undoped G as in Example 1
A channel layer 2 of 2400 A, which is n-type impurity-doped to 2.5 × 10 ¹⁷ cm ⁻³ , is formed on the aAs substrate 1 by the MBE technique, and an oxide film 3 is formed on the channel layer 2 by plasma C.
Form 3000A by VD.

As shown in FIG. 3A, after the pattern formation by the resist, the oxide film 3 is formed on the oxide film 3 by the ECR technique.
The opening is performed with an opening width of μm. As shown in FIG.
After ECR opening, it can be passivated, for example by exposing the opening to Ar ⁺ plasma. Inactivation area 4
Can be controlled by the bias voltage of the plasma. For example, with a bias of 100 V, the channel layer is inactivated at a depth of 500 A. As shown in FIG. 3C, the sidewall oxide film 5 of 3000 A is formed by plasma CVD. As shown in FIG. 3D, the sidewall oxide film 5 is opened again using the ECR technique. At this time, the size of the opening is 1.2 μm. As shown in (e) of FIG.
By performing the r ⁺ plasma treatment, a passivation region of about 800 A is formed. Thereafter, as shown in FIG. 3F, the sidewall oxide film 5 is grown to 3000 A by plasma CVD. As shown in (g) of the figure, CHF _{3 is formed} by the RIE technique.
Opening etching of the side wall oxide film 5 is performed by + O ₂ plasma. At this time, the opening width is 0.6 μm. At this time, similarly to the first embodiment, the depth of the inactive region can be set to 1000 A by setting the bias voltage to 400V.
Therefore, the channel layer 2 under the gate electrode has a thickness of 1200 A and the layer thickness of the channel layer 2 is 16 A in the drain electrode direction.
It is possible to realize a structure that gradually increases from 00A to 1900A.

Next, as shown in FIG. 3 (i), after forming the gate electrode 6, the source electrode 7 and the drain electrode 8 are formed as shown in FIG. 3 (j) to complete the FET.

Another embodiment will be described with reference to process sectional views of FIGS. In this structure, as in the first embodiment, after opening the oxide film 3, A
forming an inactive region 4 of 800 A by r ⁺ plasma,
After forming the sidewall oxide film 5 of 3000 A, the sidewall oxide film is opened by MIE using CHF ₃ gas. 450 ° C after opening
Annealing at 10 decreases the carrier concentration due to the diffusion of hydrogen atoms, and the low concentration region 10 has 2.0E1.
It is formed at 7 cm-3. This structure also has a structure in which the sheet carrier concentration beside the gate is increased as compared with the sheet carrier concentration below the gate electrode, and has the same effect as in the other embodiments.

[0023]

As described above, according to the present invention, the n-type impurity-doped compound semiconductor layer (channel layer) and the region formed in the channel layer and not in contact with the channel layer on the region are formed. And a region (low-concentration region) which is a region doped with an n-type impurity at a concentration lower than the n-type impurity concentration of the channel layer and has a cross-sectional structure that narrows from the upper portion to the lower portion in a single step or multiple steps (low-concentration area). Since the gate electrode having a gate length narrower than the upper dimension of the low-concentration region, the source electrode formed on the channel layer, and the drain electrode formed on the channel layer are provided on the region, the gate recess is formed. It is possible to realize a high-power FET that performs a large signal operation without forming it. Especially in the case of large signal operation, it is necessary to avoid the phenomenon that electrons are trapped in the electron traps on the semiconductor surface between the gate electrode and the drain electrode, the surface potential rises, and the channel layer is narrowed by the surface depletion layer. It is possible to avoid forming the conventional gate recess having a two-step recess structure. Therefore, it is possible to alleviate the electric field concentration at the gate electrode end caused by the gate recess and improve the gate breakdown voltage determined by the avalanche breakdown.
Since the gate electrode is not embedded in the channel layer, it is possible to increase the power gain without increasing the gate capacitance. Therefore, it is possible to realize a high output FET with high power addition efficiency. Furthermore, since the distance between the gate recesses is controlled by the film thickness of the sidewall oxide film, the controllability of the gate breakdown voltage is increased. Furthermore, the profile under the gate electrode is n ⁻
Because of the / n structure, gm is constant with respect to the gate bias, and there is also an effect of reducing distortion characteristics particularly in RF characteristics. (2) An n-type impurity-doped compound semiconductor layer (channel layer), and a region formed in the channel layer and not in contact with the channel layer in the upper portion and the lower portion of the region and the channel. A region (a low-concentration region) in which the cross-sectional structure is gradually narrowed to the upper part (low-concentration region), in which the region is n-type impurity-doped at a concentration lower than the n-type impurity concentration of the layer; A gate electrode having a gate length narrower than the upper dimension of
Since the source electrode formed on the channel layer and the drain electrode formed on the channel layer are provided, it is possible to realize a high output FET with high power addition efficiency as described above.

[Brief description of drawings]

FIG. 1 is a structural sectional view of an embodiment of the present invention.

FIG. 2 is a process sectional view of an example of the present invention.

FIG. 3 is a process sectional view of another embodiment.

FIG. 4 is a process sectional view of another embodiment.

FIG. 5 is a process sectional view of a conventional technique.

FIG. 6 shows a carrier profile of an example.

[Explanation of symbols]

 1 GaAs substrate 2 channel layer 3 oxide film 4 low concentration region 5 sidewall oxide film 6 gate electrode 7 source electrode 8 drain electrode 9 resist 10 low concentration region

Claims (2)

[Claims] 1. A compound semiconductor layer (channel layer) doped with an n-type impurity, a region formed in the channel layer and not in contact with the channel layer on the region, and an n-type impurity of the channel layer. Region where the n-type impurity is doped at a concentration lower than the concentration and the cross-sectional structure has a shape that narrows from the upper portion to the lower portion in one step or in multiple steps (low concentration area)
And a gate electrode having a gate length narrower than the upper dimension of the low concentration region, a source electrode formed on the channel layer, and a drain electrode formed on the channel layer. Field effect transistor characterized by. 2. A compound semiconductor layer (channel layer) doped with an n-type impurity, a region formed in the channel layer, and a region which is not in contact with the channel layer at an upper portion of the region and a lower portion of the region. A region (low-concentration region), which is a region of the channel layer doped with an n-type impurity at a concentration lower than the n-type impurity concentration, and has a cross-sectional structure that gradually narrows from an upper portion to a lower portion, and on the low-concentration region. A field effect transistor comprising: a gate electrode having a gate length narrower than an upper dimension of the low concentration region; a source electrode formed on the channel layer; and a drain electrode formed on the channel layer.