JPH0474441A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make an insulating layer play a role of a first-stage recess of conventional two-stage recess-shaped gate electrodes by a method wherein the insulating layer is formed at the outside of a recess on the surface of an active layer so as to come into contact with the recess. CONSTITUTION:A substratum insulating layer 9 and an active layer 2 under it are wet-etched and removed by making use of a photoresist film 5 as a mask; a recess 7 is formed. After that, a gate metal 8 is vapor-deposited on the whole surface of a GaAs substrate 1. Then, the photoresist film 5 is removed together with the gate metal 8 on the photoresist film 5; a gate electrode 8a whose gate length is about 0.5mum is formed inside the recess 7. Since the insulating layer 9 is used for the recess-type gate electrode instead of a first-stage recess of conventional two-stage recess gate electrodes, the performance of the two- stage recess-type gate electrodes is not damaged. Since the electrode is not influenced by the difference in level of the first-stage recess as in conventional cases, the film thickness of the photoresist film 5 is made uniform and a fine opening part 6 can be formed. Thereby, the gate electrode can be made fine.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a recessed gate electrode in a microwave element.

[Conventional technology]

Field-effect transistors (hereinafter referred to as GaAs) whose substrate is gallium arsenide (hereinafter referred to as GaAs), which has an electron mobility several times higher than that of silicon (hereinafter referred to as S1), which is currently the mainstream semiconductor technology.
(hereinafter referred to as FET) is a high-speed transistor.

It is attracting attention as a high frequency FET.

Conventionally, the main AsFE is difficult to control the threshold voltage.
In order to improve this, the gate electrode has a recessed structure, which is most widely used.

FIG. 9 is a cross-sectional view showing the structure of a recessed gate electrode in a conventional GaAsFET. Also, Figure 10 ta+
~(dl is a cross-sectional view showing the main manufacturing process of the recessed gate electrode.

In the figure, (1) is a semiconductor substrate made of GaAs (
Hereinafter, (referred to as hAs substrate), (2) is a GaAS substrate (referred to as hAs substrate).
1) the active layer formed on the active layer, (8) and (4) the source electrode and drain electrode formed on the active layer (2), and (6) the source electrode (8) and the drain electrode (4). A photoresist film coated and formed on the active layer (2), (
6) is the opening provided in the photoresist film (5!), (γ
) is a recess formed in the active layer (2), and 0g is a recess (
γ) is formed on the entire surface of the flGaAs substrate (1), and (8a) is the gate metal (8) formed especially in the recess (7), which is the gate electrode. .

Next, the manufacturing method will be explained based on FIG. 1O fat to fdl.

First, ion implantation technology was applied to the entire surface of the GaAs substrate (1).
Alternatively, the active layer (2) can be formed using epitaxial growth technology.
is formed, and then a source electrode (8) and a drain electrode (4) are formed on the active layer (2) (FIG. 10(a)).
First, a photoresist film (
5) is formed, and this is patterned by photolithography technology to form an opening (6) (see FIG.
).

Next, using the photoresist film (5) as a mask, the underlying functional D layer (2) is removed by wet etching to form a recess (7). After that, a gate metal (8) is deposited on the entire surface of the GaAs substrate (1) (Fig. 10(C)).
.

Next, when the photoresist film t': 'e % is removed together with the gate metal (8) on the photoresist film (6), a gate electrode (8a) is formed in the recess (γ) (10th
Figure (d)).

In this way, the recessed gate electrode of FBT can be manufactured, but in order to make PETO more durable and more efficient,
Conventionally, gate electrodes (hereinafter referred to as
(referred to as a two-stage recessed gate electrode) is used.

A structural diagram of the two-stage recessed gate electrode will be described below. Note that the description of parts that overlap with the description of the recessed gate electrode shown in FIGS. 9 and 10 will be omitted as appropriate.

FIG. 11 is a cross-sectional view showing the structure of a two-stage recessed gate electrode of a conventional FET. In addition, Fig. 12 (al~(d
FIG. 1 is a cross-sectional view showing the main manufacturing steps of the two-stage recessed gate electrode.

In the figure, (1) to (4), (8) to (&l) are the 9th
The recessed gate electrode (5a) is the same as that shown in FIG. (6a) is the first photoresist film (5).
(7a) is a first recess formed in the active layer (2) below the first opening (6a);

(5b) shows the active layer (with which the first recess (7a) has been formed).
2) second photoresist film formed on (6b
) is a second opening provided in the second photoresist film,
(7b) is a second recess formed in the active layer (2) below the first recess (7a).

Next, the manufacturing method will be explained based on FIGS.

First, ion implantation technology was applied to the entire surface of the GaAs substrate (1).
Alternatively, the active layer (2) can be formed using epitaxial growth technology.
After that, a source electrode (8) and a drain electrode (4) are formed on the active layer (2). Next, the active layer (on which the source electrode (8) and drain electrode (4) are formed)
2) A first photoresist film (5a) is formed on the entire surface and patterned by photolithography to form a first opening (6a). Using the first photoresist film (5a) as a mask, the underlying active Ni
(2) is removed by wet etching to form a first recess (7a) (FIG. 12(a)).

Next, a second photoresist film (5b) is completely formed on the entire surface of the projection substrate (1) from which the first photoresist film (5a) has been removed, and this is patterned by photolithography technology to form second openings. (6b) is formed. As a result, the central surface of the first glue file (7a) is exposed (the twelfth
Figure (shi)).

Next, using the second photoresist film (5b) as a mask,
The underlying active layer (2) is removed by wet etching to form a second recess (7b) i. At this time, the second recess (7b) is formed under the central portion of the first recess (7a), and the recess has a two-step staircase shape. Thereafter, a gate metal (8) is deposited over the entire surface of the GaA3 substrate (1) (FIG. 12(C)).

Next, the second photoresist film (5b) 'Th, the second
When the gate metal (8) on the photoresist film (5b) is removed together with the gate metal (8), a gate electrode (8) is formed in the second recess (7b).
a) is formed (FIG. 12(d)).

[Problem to be solved by the invention]

In this way, in the conventional two-stage recess type gate electrode structure of PET, photolithography technology is used twice to form the two-stage recess when manufacturing it.
The manufacturing method was complicated, which caused a decrease in yield. In particular, since the second recess (7b) is formed within the first recess (7a), due to problems with the alignment accuracy of photolithography technology, the second recess (7b) and gate are formed in a stable and reproducible manner. There was a problem in that electrodes (roles) could not be formed.

Further, due to the step difference in the first recess (7a), the thickness of the applied second photoresist film (5b) becomes non-uniform. Therefore, when trying to form a gate electrode with a fine gate length, it is difficult to form a fine opening (6b) corresponding to the gate length in the second photoresist film (5b), and the gate electrode This prevented miniaturization.

This invention was made to solve the above-mentioned problems, and its purpose is to improve the fineness of the gate electrode without impairing the performance of the high-efficiency, high-voltage two-stage recessed gate electrode. The object of the present invention is to obtain an FgT having a recessed gate electrode that can be manufactured stably with good reproducibility.

[Means to solve the problem]

In order to achieve the above object, a semiconductor device according to the present invention includes: an active layer formed on a semiconductor substrate; a source electrode and a drain electrode formed on the active layer; a recess located between the electrode and the drain electrode, a gate electrode formed in the recess, and an insulating layer formed on a surface of the active layer to be thinner than the depth of the recess, the insulating layer is formed outside the recess in contact with the recess.

[Effect]

The insulating layer in this invention is formed on the surface of the active layer outside the recess and in contact with the recess.

Therefore, the insulating layer serves as the first stage recess of the conventional two-stage recess type gate electrode. Therefore, it has performance equivalent to that of the conventional two-stage recessed gate electrode. Furthermore, since the conventional first-stage recess is not actually formed, manufacturing becomes easier, and it becomes possible to miniaturize the light and gate electrodes, which are not affected by the difference in level.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Note that the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a sectional view showing the structure of a recessed gate electrode of an FET according to a first embodiment of the present invention.

Further, FIG. 2 ta+ to re+ are cross-sectional views showing the main manufacturing steps of the recessed gate electrode according to the first embodiment.

In the figure, (1) to (81, (8a) are the same as the conventional recessed gate electrodes shown in FIGS. 9 and 10, and (9) is the source electrode (8) and drain electrode (4).
) is an insulating layer formed on the active layer (2) between the active layer (2) and the active layer (2).

Next, the manufacturing method will be explained.

First, about 30% of the active layer (2) is formed on the entire surface of the substrate (1) by ion implantation technology or epitaxial growth technology.
It is formed to a film thickness of oooX. At this time, the active layer (2) is
S1 ion dose is approximately 2x 10” at surface ~2000X
/i, 20o OA ~ 3000s approximately 3 x 1
017/cII. Thereafter, a source electrode (8) and a drain electrode (4) are formed on the active layer (2) with a distance of 3) trIL to 4) tm (FIG. 2(a)).

Next, using the source electrode (81 and the drain electrode (4) as masks), for example, P-type boron (Bl ions) are implanted from the GaAs substrate (1) at an energy of, for example, 23Ke.
Implant at a dose of I x 1013/cd at V.

As a result, the crystallinity of a part of the N-type active layer (2) is destroyed, and an insulating layer (9) is formed with a thickness of about 50 OA (FIG. 2 fbl).

Next, a photoresist film (5) with a thickness of about 600 OA is formed on the entire surface of the GaAs substrate (1), and this is patterned using photolithography technology to obtain a desired gate length (0,5) tm). An opening (6) corresponding to this is formed.

As a result, the central surface of the insulating layer (9) is exposed (FIG. 1(C)).

Next, using the photoresist film (5) as a mask, the underlying insulating layer (9) and the active layer (2) below it are removed by wet etching to a depth of about 200 OA to create a recess (γ).
form. At this time, the width of the recess (γ) is approximately 08 μm
becomes. Thereafter, a gate metal (8) is deposited on the entire surface of the hAs substrate (1) to a thickness of approximately 500X (Fig. 2(d)
)).

Next, the photoresist film (6) is replaced with the photoresist film (51).
When removed together with the upper gate metal (8), the recess (γ)
A gate electrode (8a) having a gate length of about 0.5 pm is formed within the structure (FIG. 2(e)).

After that, the FET is completed by going through predetermined steps.

The recessed gate electrode configured as described above uses an insulating layer (9) instead of the first recess (7a) of the conventional two-stage recessed gate electrode, so it is a two-stage recessed gate electrode. The performance of the gate electrode is not impaired. Moreover, since it is not affected by the step of the first recess (7a) as in the conventional case, the thickness of the photoresist film (6) becomes uniform.
A fine opening (6) can be formed, thereby making it possible to miniaturize the gate electrode. In addition, since the photolithography process is only required once, manufacturing is easier than with conventional two-stage recessed gate electrodes, and recessed gates have good reproducibility and stability, and have the same performance as two-stage recessed gate electrodes. A FET with electrodes can be obtained.

Although the first embodiment has a structure in which the insulating layer (9) is formed using the source electrode (8) and the drain electrode (4) as masks, the present invention is not limited to this.

That is, FIG. 3 shows the FE according to the second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the structure of a recessed gate electrode of T. In this structure, an insulating layer (9) disposed outside the recess is spaced apart from the source electrode (8) and drain electrode (4). To manufacture this product, as shown in FIG. 4, a photoresist film (2
), and by phosphorography technology, a source electrode (8
) and the drain electrode (4). Thereafter, an insulating layer (9) is formed by ion implantation using the photoresist film portion as a mask.

Further, FIG. 5 shows the structure of a recessed gate electrode of an FET according to a third embodiment of the present invention. In this case, the thickness of the active layer (2) under the insulating layer (9) is equal to the thickness of the active layer (2) under the source/drain/electrode (8), (4), and there is no step difference. To manufacture this device, as shown in FIG. 6, after forming the active layer (2), an insulating layer (9) is formed on the entire surface of the GaAs substrate (1) by ion implantation, and then the source/drain The insulating layer (9) in the area where the electrodes (8) and (4) are to be formed is removed by etching. Next, a source electrode (3) and a drain electrode are formed.

Further, FIG. 7 is a cross-sectional view showing the structure of an FgT recessed gate electrode according to a fourth embodiment of the present invention. This is the source/drain electrode (8).

An insulating layer (9) is also formed in the formation region of 04. To manufacture this, the active layer (
2) After the formation, an insulating layer (9) is formed on the entire surface of the hAs substrate (1) by ion implantation, and then an ohmic alloy is formed on the insulating layer (9) to become the source electrode (8) and the drain electrode (4). Next, an ohmic alloy layer is formed under the insulating layer using a sink, and the underlying active layer (2
) and obtain ohmic contact.

In addition, in the first embodiment, the insulating layer (9) was formed by ion implantation with boron (Bl), but the same effect can be obtained by forming the insulating layer (9) using ions of other atoms such as hydrogen. can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since an insulating layer is used in place of the first recess of the two-stage recessed gate electrode of the FET, it is possible to obtain performance equivalent to that of the two-stage recessed gate electrode. can. Therefore, manufacturing becomes easy, and an FET having a recessed gate electrode with high breakdown voltage and high efficiency can be obtained stably with good reproducibility. Further, miniaturization of the gate electrode can also be promoted.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of a recessed gate electrode of an FET according to a first embodiment of the present invention, and FIG.
1 is a cross-sectional view showing the main manufacturing process of the product shown in FIG. 1;
3 is a cross-sectional view showing the structure of a recessed gate electrode of a FIICT according to a second embodiment of the present invention; FIG. 4 is a cross-sectional view showing the main manufacturing process of the one shown in FIG. 3; and FIG. is a cross-sectional view showing the structure of a recessed gate electrode of a FET according to the third embodiment of the present invention, WJG is a cross-sectional view showing the main manufacturing process of the FET shown in FIG. 5, and FIG. A cross-sectional view showing the structure of a recessed gate electrode of FEeT according to an embodiment, FIG. 8 is a cross-sectional view showing the main manufacturing process of the one shown in FIG. 7, and FIG. 9 is a cross-sectional view showing the structure of a conventional recessed gate electrode. Figures 10 (al to dl are cross-sectional views showing the main manufacturing steps of the product shown in Figure 9, Figure 11)
The figure is a sectional view showing the structure of a conventional two-stage recess type gate electrode, and FIGS. 12 fal to fdl are sectional views showing the main manufacturing steps of the one shown in FIG. In the figure, (1) is one substrate, (2) is an active layer, (8)
(4) is a drain electrode, (7) is a recess, (8a) is a gate electrode, and (9) is an insulating layer. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] an active layer formed on a semiconductor substrate; a source electrode and a drain electrode formed on the active layer; a recess formed in the active layer and located between the source electrode and the drain electrode; A semiconductor device comprising: a gate electrode formed thereon; and an insulating layer formed on a surface of the active layer to be thinner than the depth of the recess, the insulating layer contacting the recess and being formed outside the recess.