JPS6286870A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To accurately form an FET of offset gate structure by removing an insulating film of drain side on a gate electrode, then ion implanting, then with the film as a mask removing a gate electrode of the drain side. CONSTITUTION:After an N-type semiconductor layer 2 is formed on a GaAs substrate 1, a high melting point metal film 3 of the length corresponding to a distance between high melting point metal drain and source regions and an SiO2 film 4 are formed. Then, photoresist 5 as a mask the film 4 is partly removed, a silicon implanted layer 7 is formed. Then, with an SiO2 film 4' as a mask high melting point metal 3 is etched as a gate electrode 3'. The layer 7 is formed in a high density n-type semiconductor layer 8 by heat treating in arsenic atmosphere. Eventually, after a source electrode (not shown) is formed, the SiO2 film 4' is removed. Thus, an FET of offset gate structure can be accurately obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular to a Schottky barrier field effect transistor having an offset gate structure in which the gate-drain distance is longer than the gate-source distance. (SB-FET) manufacturing method.

Conventional technology 5B-FIT using compound semiconductors such as eaAs,
It has excellent properties as an ultra-high frequency or ultra-high speed device because it has high electron mobility and can provide a semi-insulating substrate. Increased speed of 5B-FET.

In order to increase the frequency, it is essential to increase the mutual conductance gm of the 5B-FET and to reduce the gate-source I Cgg and source resistance Rs. Effective methods for achieving these goals include shortening the gate length and shortening the distance between the gate and source. The gate length can be easily shortened to 1 μm or less using electron beam exposure, etc., but it takes precision to shorten the gate and source distance by aligning the gate pattern and source pattern using the normal exposure method. From this point of view, the practical limit is around ±0.6 μm.

Therefore, the self-alignment method is used to shorten the time between source and date. Figure 3 shows 5B- manufactured using self-alignment technology using high melting point gate metal.
It is a schematic diagram of the manufacturing process of FET.

Silicon ions, /(SL) are implanted into the semi-insulating caAs substrate 11 using an ion implantation method, and the n-type semiconductor layer 12 is formed by heat treatment (FIG. 3 (2L)). Gate electrode made of W-8i as high melting point metal% 13k
A gate electrode 13. is formed using a photoresist 14 by a conventional photolithography method. Using the photoresist 14 as a mask for ion implantation, silicon ions 15 are used to form an ion implantation layer and a silicon implantation layer 16 (see FIG. 3(b)).
)). The photoresist 14 is removed and heat treated in an arsenic atmosphere to convert the silicon implanted layer 16 into a high concentration n-type layer 17 (FIG. 3(C)). The gate electrode 13 is a high concentration n-type layer 17
Since the gate electrode 13 is in contact with the gate electrode 13, the gate electrode 13 has a low gate breakdown voltage, and in order to improve the gate breakdown voltage, the side walls of the gate electrode 13 are etched (FIG. 3(d)). An ohmic electrode made of Mu-U-Go is formed on the high concentration n-type layer, and the source electrode 18. This is used as a drain electrode 19 (FIG. 3(e)).

In this case, the highly doped n-type layer 17 becomes the source and drain regions.
Since the gate electrode 13 is formed as a mask, it is possible to form the gate electrode with high precision.

Problems to be Solved by the Invention As explained in FIG.
Since the distance between 3' and the highly doped n-type semiconductor layer 17 serving as the source region and drain region is always the same, the source resistance decreases, but as a result of the gate-drain distance becoming smaller, the withstand voltage decreases. There are drawbacks. A way to solve this problem is to narrow the gate-source spacing and
A so-called offset gate structure in which the drain spacing is widened is known. However, it has been difficult to form offset gates with an accuracy of 1 μm or less using the conventional exposure method.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a method for manufacturing a field effect transistor having an offset gate structure, which eliminates the above drawbacks.

Means for Solving the Problems In the present invention, after removing the insulating film on the drain side of the insulating film formed on the gate electrode, ions are implanted using the entire gate electrode of the high concentration n-type semiconductor layer, which will become the source and drain regions, as a mask. A field effect transistor having an offset gate structure is obtained by removing the gate electrode on the drain side using the insulating film on the source side remaining on the gate electrode as a mask.

According to the present invention, with the above configuration, it is possible to reduce the source resistance of 5n-yxf, increase the withstand voltage between the gate and drain, and manufacture an offset gate structure FET using the self-alignment method.

Embodiment FIG. 1 is a process sectional view for explaining a method of manufacturing a 5B-FET in an embodiment of the present invention.

Silicon ions were implanted into the semi-insulating eaAs substrate 1 at 2.6×1012 cIrL− at 100 KeV using an ion implantation method.
After implanting 2, an n-type semiconductor layer 2, which will become the channel region of the 5B-FET, is formed by heat treatment (see Fig. 1).
&)). A high melting point metal made of a W-S alloy is vacuum deposited on the surface of the n-type semiconductor layer 2, and a CVN method (
Chemical Vapor Deposition
5i02 is deposited using conventional photolithography, and high melting point gold 13,5io24 is formed with a length of 1.6 μm, which corresponds to the distance between the drain and source regions (Fig. 1(b)).
.

Next, as shown in FIG. 1(C), cover the source side end side of the high melting point metal 3, 5i02a with a photoresist 6, and use the photoresist 6 as a mask to cover the high melting point metal 3, 5i02a on the high melting point metal 3.
Remove a part of a to obtain 5i02 a'. Next, the photoresist 6 is removed, and silicon ions 6 are implanted using an ion implantation method to form a silicon implant @7 of 150 KeV Te5 x 10'' (FIG. 1(d)).

Using 5i024' as a mask, the high melting point metal 3 is etched to form a gate electrode 3'. 800 in an arsenic atmosphere.
Heat treatment is performed for 5 minutes to convert the silicon ion-implanted layer 7 into a highly doped n-type semiconductor layer 8 (FIG. 1 (θ)). An ohmic electrode made of Au-Ge is formed on the high concentration n-type semiconductor layer 8 using a normal photolithography method, and a source electrode 9. A drain electrode 10 is used.

5i02a' is removed to form a 5B-FET.

As is clear from FIG. 1(f), the highly doped n-type semiconductor layer overlying the source and drain can be formed in self-alignment so as to be asymmetric with respect to the gate electrode. Figure 1 (C)
After etching a high-melting point metal 3f5i024'f mask to form a gate electrode 3', heat treatment was performed in an arsenic atmosphere to prevent diffusion from the silicon injection layer 7, which is placed on top of the drain, to the n-type semiconductor layer 2. This is to suppress it. This makes it possible to further improve the breakdown voltage between the drain and gate.

Figure 2 shows another embodiment of the gate electrode 3' of Figure 1 (15).
After forming the gate electrode 3', isotropic etching is performed to form the gate electrode 3'.
Etch from the source and drain ends to form the gate electrode 3.
As a result, the high-concentration n-type semiconductor layer 7, which will become the source region, and the gate electrode 3# are not in contact with each other, so that the breakdown voltage between the source and the gate is improved.Also, by using isotropic etching, the length of the gate electrode 3' is Since the gate electrode 3'' can be formed with high precision, the gate length can be shortened with almost no increase in source resistance.

In the embodiment, a method for manufacturing a 5B-FET using caAs as a material has been described, but other materials such as Si and InP may also be used. The gate electrode is made of a material that can withstand heat treatment after ion implantation, such as W-T, W-AI! It goes without saying that other high-melting point metals, such as, may also be used. Although 5i02 was used as the insulating film on the high melting point metal, any material that can withstand heat treatment after ion implantation may be used, and 515N
Of course, 4, 1zos, etc. may also be used.

Effects of the Invention According to the manufacturing method of the present invention, the gap between the gate electrode and the source region can be formed extremely narrow, so the source resistance Rs can be made small, and the gap between the gate electrode and the drain region can be formed wider than that between the gate electrode and the source region. Therefore, the drain breakdown voltage can be increased. Further, since it can be formed by a self-alignment method, manufacturing is easy. The offset gate structure of the present invention can be formed with a planar structure and uses a self-alignment method, so there is little variation in characteristics.
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[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing a method for manufacturing a 5B-FET according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a 5B-FET showing another method according to the present invention, and FIG. 3 is a 5B-FET manufactured by a conventional method.
- It is a process cross-sectional view which shows the manufacturing method of FET. 1... Semi-insulating GILAS substrate, 2...
・N-type semiconductor layer, 3... High melting point metal, 3', 3
”...Gate electrode, a, 4!'...
...5in2. es・・・Photoresist, 8
. . . High concentration n-type semiconductor layer, 9 . . . Source electrode, 10 . . . Drain electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1, 3″ 121 4. Figure 3

Claims (2)

[Claims] (1) forming a high melting point metal on the surface of a semiconductor layer, forming an insulating film on the high melting point metal, removing a desired amount of the insulating film from the drain side of the insulating film, and the high melting point metal and a step of forming an ion implantation layer using the insulating film as a mask, a step of removing the high melting point metal exposed using the insulating film as a mask, and a step of activating the ion implantation layer by heat treatment to form a highly concentrated semiconductor layer. . A method for manufacturing a semiconductor device, comprising the step of forming ohmic source and drain electrodes in the high concentration semiconductor layer region. (2) A method for manufacturing a semiconductor device according to claim 1, which includes the step of etching a desired amount from the exposed sidewall of the high melting point metal using an insulating film on the high melting point metal as a mask.