JP3164080B2 - Field effect transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method for manufacturing the same, and more particularly, to a recess.
The present invention relates to a field-effect transistor including a gate electrode provided in a recess where a cap layer is removed by etching in step s) and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a field-effect transistor, when a high output is considered, it is practically necessary to improve the gate-drain breakdown voltage and the maximum oscillation frequency. here,
One of the determinants of the gate-drain breakdown voltage is the electric field distribution between the gate and the drain. At this time, since the state of the interface between the recess and the protective film actually has an interface state caused by traps and process defects, the electric field is relaxed by increasing the distance between the gate and the drain.

In order to increase the maximum oscillation frequency, the gate resistance Rg and the capacitance Cgd between the gate and the drain are required.
Is a useful measure to minimize The gate resistance Rg is devised to reduce the resistance by increasing the size of the upper layer of the gate, particularly when the gate length is becoming shorter.

Further, as another factor to be considered in designing the device structure, there is a reduction in the distance between the source and drain electrodes, and a reduction in an extrinsic resistance component relating to device characteristics is expected. As a method for overcoming these problems and aiming at high performance, a combination of a fine gate and an asymmetric recess structure can be considered. However, it is difficult to form a fine gate by an optical exposure method such as a stepper when the gate length is 0.3 μm or less, and a method using electron beam exposure or the like has been adopted.

FIG. 5 shows an example of a conventional fine gate forming method. In the same figure, in a wafer grown on a GaAs substrate 51, an impurity-doped Ga grown on a Schottky contact layer 52 on which a gate electrode is mounted is shown.
An electron beam photoresist film 54 is formed on the As contact resistance reducing cap layer 53, and an opening 55 is formed in the gate lower layer portion by electron beam exposure (FIG. 5).
(A)). Further, a photoresist film 56 for optical exposure is formed thereon, and an opening 57 is provided in the gate upper layer portion by an optical exposure method such as a stepper (FIG. 5B).

Next, the impurity doped GaAs contact resistance reducing cap layer 53 is etched through the openings 55 and 57 of the resist to form a recess 58 (FIG. 5C). Then, the resist opening portions 55 and 5
7, a gate metal 59 is deposited (FIG. 5).
(D)). Finally, a lift-off process is performed using an organic chemical to form a T-type gate electrode 60 (FIG. 5E).

[0007]

When the gate electrode is offset in the recess, the gate-drain length is increased and the gate-source distance is shortened to improve the breakdown voltage and the gate-drain capacitance. A reduction in Cgd can be expected. However, if an attempt is made to offset the gate in the recess by self-alignment, it is necessary to take measures such as forming the offset portion of the opening first. Therefore, in the prior art, it was necessary to increase one or more steps in order to apply an offset in the recess.

Further, when the gate electrode is moved to the source electrode side, when the gate metal comes into contact with the cap layer, the device performance is reduced, such as a state in which the gate length is extended to the contact portion or an increase in current leakage. Becomes In order to prevent the metal of the gate electrode from coming into contact with the portion of the cap layer on the source electrode side, there is a high possibility of being restricted by the limit of the exposure accuracy of the gate pattern. Further, the lift-off gate electrode having a T-shape has a drawback in that it is necessary to consider the height of the gate lower layer portion and the eave width of the upper layer portion so that the gate upper layer portion does not contact the cap layer. On the other hand, when the gate length is reduced, there is a disadvantage that the gate metal becomes difficult to be buried when the aspect ratio of the lower layer becomes large.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and has as its object to minimize the gate-drain capacitance within the source-drain distance without causing current leakage or the like. It is an object of the present invention to provide a field effect transistor which realizes improvement of device characteristics by minimizing the limit and is suitable for miniaturization of a gate length, and a method of manufacturing the same.

[0010]

A field effect transistor according to the present invention comprises a cap layer having a predetermined doping concentration provided on a contact layer, and a gate provided in a recess portion in which the cap layer is removed by etching in a recess step. An electrode, a field effect transistor including a source electrode and a drain electrode provided in the cap layer with the recess portion interposed therebetween, wherein a high resistance is provided only at an end of the cap layer on the source electrode side on the recess portion side. And the gate electrode is formed so as to be in contact with the source electrode via the high resistance portion. The gate electrode has a convex portion formed on the high resistance portion. A high-purity semiconductor section may be formed instead of the high-resistance section.

According to a method of manufacturing a field effect transistor according to the present invention, a cap layer having a predetermined doping concentration is provided on a contact layer , and a gate electrode is attached to a portion where the cap layer is removed by etching in a recess step. A method of manufacturing a field-effect transistor having a recess structure, comprising: implanting ions into a part of a portion to be recessed in the cap layer on a source electrode side; and forming a first photoresist film on the cap layer. The process of
A step of opening a window on a part of the ion-implanted portion into which the ions have been implanted in the first photoresist film, a step of recess etching through a window opened in the first photoresist film, and a step of etching the recess Removing the first photoresist later, forming a second photoresist film after the removal, and forming a window so that a desired gate length can be obtained from the recess etching end on the source electrode side. A step of depositing a metal on the inside of the opened window and the surface of the second photoresist film, and a step of lifting off the metal by lift-off while leaving a gate electrode portion of the deposited metal. And removing the.

Another method of manufacturing a field effect transistor according to the present invention comprises a cap layer having a predetermined doping concentration provided on a contact layer , and a gate electrode is mounted on a portion where the cap layer is etched away by a recess step. A method of manufacturing a field-effect transistor having a recess structure, wherein ions are implanted into a portion of the portion to be recessed in the cap layer on the side of the source electrode, and a first photoresist film is formed on the cap layer. Forming a window on a part of the ion-implanted portion into which the ions have been implanted, in the first photoresist film;
A step of recess etching through a window formed in the first photoresist film, a step of removing the first photoresist after the recess etching, and a step of forming a second photoresist film after the removal; Forming a window in the second photoresist film so that a desired gate length can be obtained from the recess etching end on the source electrode side, and applying a metal to the inside of the opened window and the surface of the second photoresist film. It is characterized by including a step of obliquely vapor-depositing from the drain electrode side and a step of removing the metal by lift-off while leaving the gate electrode portion of the obliquely vapor-deposited metal.

Further, the method of manufacturing a field effect transistor according to the present invention has a recess structure in which a cap layer provided on a contact layer is provided, and a gate electrode is attached to a portion where the cap layer is etched away by a recess step. A method of manufacturing a field-effect transistor, comprising: implanting ions into a portion of the cap layer other than a portion to be recessed; forming a first photoresist film on the cap layer; Forming a window in the first photoresist film over a part of the undoped portion not implanted, recess etching through the window formed in the first photoresist film, and after the recess etching, Removing the first photoresist, forming a second photoresist film after the removal, and Forming a window in the second photoresist film so as to obtain a desired gate length from the recess etching end on the side of the electrode, and applying a metal to the inside of the opened window and the surface of the second photoresist film. The method includes a step of depositing and a step of removing the metal by lift-off while leaving a gate electrode portion of the deposited metal.

Another method for manufacturing a field effect transistor according to the present invention is directed to a recess structure in which a cap layer provided on a contact layer is provided and a gate electrode is attached to a portion where the cap layer is etched away by a recess step. A method of manufacturing a field-effect transistor, comprising: implanting ions into a portion of the cap layer other than a portion to be recessed; forming a first photoresist film on the cap layer; Forming a window in the first photoresist film over a part of the undoped portion not implanted, recess etching through the window formed in the first photoresist film, and after the recess etching, Removing the first photoresist, forming a second photoresist film after the removal, Forming a window in the second photoresist film so that a desired gate length can be obtained from the recessed etching end on the electrode side; and draining a metal inside the opened window and on the surface of the second photoresist film. It is characterized by including a step of obliquely vapor-depositing from the electrode side and a step of removing the metal by lift-off while leaving the gate electrode portion of the metal obliquely vapor-deposited.

In short, the field-effect transistor of the present invention has a high-resistance portion or a high-purity semiconductor portion in the source-side portion of the cap layer etched by the recess step, and the high-resistance portion or the high-purity portion of the source-side cap layer. The semiconductor device is characterized in that a recess structure is formed leaving a semiconductor portion, and an offset gate electrode in contact with a high-resistance portion or a high-purity semiconductor portion of the cap layer.

The manufacturing method according to the present invention is a method for forming a gate in a recessed structure type field effect transistor, in which an ion implantation is performed on a source side cap layer so that a part of the ion implanted portion or a high-purity semiconductor portion remains. Then, the resist is once removed, the resist is once removed, and then optical exposure is performed again so as to obtain a desired gate length dimension from the source side recess end, and the gate metal is deposited and lifted off. By doing so, the gate upper layer portion is arranged on the ion implantation portion of the cap layer, and a gate electrode having a fine gate length can be easily formed with good control.

A high-resistance portion or a high-purity semiconductor portion is provided on the recess side surface portion of the source-electrode-side cap layer, and an offset gate electrode in contact with the high-resistance portion or the high-purity semiconductor portion is provided to prevent current leakage and the like. The device characteristics can be improved by minimizing the capacitance between the gate and the drain within the distance between the source and the drain without causing any problem. Further, since the gate upper layer is disposed on the cap layer, the height of the lower layer is reduced, so that a gate structure suitable for miniaturization of the gate length can be realized.

[0018]

Next, an embodiment of the present invention will be described with reference to the drawings. In the drawings referred to in the following description, the same parts as those in the other drawings are denoted by the same reference numerals.

FIG. 1 is a sectional view of an element structure showing a first embodiment of a method for manufacturing a field effect transistor according to the present invention. Here, as an example, a GaAs-based field effect transistor (hereinafter referred to as a FET (Field Effect T)
(hereinafter abbreviated as "transistor") will be described, but the present invention is not limited to the FET having this material system and structure. By this manufacturing method, a fine low-resistance gate can be formed by one PR process and optical exposure, and high yield, high throughput, and high performance can be realized at the same time.

FIGS. 1A to 1E show a method of manufacturing an FET in the order of steps. First, as shown in FIG. 1A, on a semi-insulating GaAs substrate 11,
An impurity-doped GaAs contact resistance reducing cap layer 13 is provided on the Schottky contact layer 12 on which the gate electrode is mounted, and a resist film 14, for example, is applied on the cap layer 13 as an ion implantation mask.
The impurity concentration of the cap layer is, for example, 5 × 10 ¹⁷ cm ⁻³ or more.

An opening is formed in the resist film 14 by optical exposure so that an ion-implanted portion is located on the source side of the gate, and ions such as oxygen O ⁺ are implanted. This ion implanted portion 15 has a high resistance. In the drawing, the S side indicates the source side and the D side indicates the drain side, and it is assumed that a source electrode and a drain electrode are formed.

Next, the photoresist film 14 used as the ion implantation mask is removed, and a new photoresist film 16 is applied. As shown in FIG.
So that the ion implanted part is located on the source side of the gate,
In addition, a gate opening window is opened in the photoresist film 16 so that a non-implanted portion does not remain on the source side of the gate. Then, the impurity-doped GaAs contact resistance reducing cap layer 13 is etched through the opening to form a recess 17 as shown in FIG.

Next, a photoresist film 1 is formed for forming a gate.
8 is applied again, a photoresist film 18 is opened by optical exposure so that a desired gate length and a source side eave width can be obtained from the source side recess edge, and a gate metal 19 is deposited through the opening of the resist mask. This deposited state is shown in FIG.

Finally, by performing a lift-off treatment using an organic chemical, as shown in FIG.
A fine gate electrode 2 whose upper part extends to the source side
0 is formed. That is, the gate electrode 20 has a convex portion (umbrella-shaped portion) placed on the ion-implanted portion 15 of the source-side cap layer 13.

As a result, a complete offset gate in contact with the source side of the cap layer 13 via the ion implantation portion 15 can be formed. As a result, the gate and the drain are separated from each other, the distance between the gate and the drain is increased, and the capacitance Cgd between the gate and the drain is reduced.

Further, if the gate electrode is formed so as to be in contact with the source side of the cap layer 13 via the ion-implanted portion 15, the gate resistance Rg may be increased. Reduction of the resistance Rg can also be realized.

Here, as an example, MESFET
(Metal Semiconductor FET)
However, the present invention is not limited to this, and the present invention can be applied to any material that can form a high resistance portion in the cap layer by a method such as ion implantation.

FIG. 2 is a sectional view of an element structure showing a second embodiment of the method for manufacturing a field effect transistor according to the present invention. Here, an example of a GaAs-based FET will be described as an example, but the present invention is not limited to an FET having this material or structure. According to this embodiment, a fine low-resistance gate can be formed by one PR process and optical exposure,
High yield, high throughput, and high performance can be realized at the same time.

FIGS. 2A to 2E also show a method of manufacturing an FET in the order of steps. As in the case of the first embodiment described above, the recess 17 is formed by etching the impurity-doped GaAs contact resistance reducing cap layer 13 as shown in FIGS.

Next, a gate forming photoresist film 21 is formed.
An opening is formed by optical exposure so that the cap layer on the drain side is covered, and a gate metal 22 is deposited by oblique evaporation from an oblique direction from the drain side to the source side through the opening of the resist mask. I do.
This deposited state is shown in FIG. Here, even if the resist opening size is the same, the gate length can be controlled to some extent by the angle of oblique deposition.

Finally, by performing a lift-off process using an organic chemical, as shown in FIG.
A fine gate electrode 2 whose upper part extends to the source side
3 is formed. In other words, the gate electrode has a projection placed on the ion-implanted portion 15 of the cap layer 13 on the source side.

As a result, a complete offset gate in contact with the source side of the cap layer 13 via the ion implantation portion 15 can be formed. As a result, the gate and the drain are separated from each other, the distance between the gate and the drain is increased, and the capacitance Cgd is reduced.

Further, if the gate electrode is formed so as to be in contact with the source side of the cap layer 13 through the ion-implanted portion 15, the gate resistance Rg may increase. However, by extending the gate upper layer portion to the source side, the gate resistance is increased. Reduction of the resistance Rg can also be realized.

Even if the size of the gate forming resist opening is constant, the gate length can be freely controlled by changing the angle at the time of vapor deposition.

Here, the case of a MESFET has been described as an example, but the present invention is not limited to this, and the present invention can be applied to any material that can form a high resistance portion in the cap layer by a method such as ion implantation.

FIG. 3 is a sectional view of an element structure showing a third embodiment of the method for manufacturing a field effect transistor according to the present invention. Here, an example of a GaAs-based FET will be described as an example, but the present invention is not limited to an FET having this material or structure. According to this embodiment, a fine low-resistance gate can be formed by one PR process and optical exposure,
High yield, high throughput, and high performance can be realized at the same time.

FIGS. 3A to 3E also show a method of manufacturing the FET in the order of steps. First, as shown in FIG. 3A, on a semi-insulating GaAs substrate 31,
A high-purity GaAs contact cap layer 33 is disposed on the Schottky contact layer 32 on which the gate electrode is mounted,
Further, on the cap layer 33, for example, a photoresist film 34 is applied as an ion implantation mask. An opening is provided in the photoresist film 34 using optical exposure so that a high-purity portion is located on the source side of the gate, and ions such as silicon Si ⁺ are implanted. The undoped portion 33a other than the ion implanted portion 35 becomes a high-purity semiconductor portion.

Next, the photoresist film 34 used as the ion implantation mask is removed, and a new photoresist film 36 is applied. As shown in FIG.
A gate opening window is opened in the resist film so that the high-purity semiconductor portion is located on the source side of the gate and the ion-implanted portion does not cover the source side of the gate. Then, through the opening, as shown in FIG. 3C, the impurity-doped GaAs cap layer 3 is formed.
3 is etched to form a recess 37.

Next, a photoresist film 3 is formed for forming a gate.
8 is applied again, a photoresist film 38 is opened by optical exposure so that a desired gate length and a source side eave width can be obtained from the source side recess end, and a gate metal 39 is deposited through the resist mask opening. This deposited state is shown in FIG.

Finally, by performing a lift-off treatment using an organic chemical, as shown in FIG.
A fine gate electrode 4 whose upper part extends to the source side
0 is formed. In other words, the gate electrode 40 has a projection on the undoped portion 33a of the source-side cap layer.

As a result, a complete offset gate in contact with the source side of the cap layer via the undoped portion 33a, which is a high-purity semiconductor portion, can be formed. As a result, the gate and the drain are separated from each other, the distance between the gate and the drain is increased, and the capacitance Cgd between the gate and the drain is reduced.

Further, if the gate electrode is formed so as to be in contact with the source side of the cap layer, the gate resistance Rg may be increased. However, the gate resistance Rg can be reduced by extending the gate upper layer to the source side.

Here, the case of MESFET has been described as an example, but the present invention is not limited to this. Any material that can form a high resistance portion by a method such as ion implantation while leaving a high purity portion in the cap layer is used. The present invention can be applied.

FIG. 4 is a sectional view of an element structure showing a fourth embodiment of the method for manufacturing a field effect transistor according to the present invention. Here, an example of a GaAs-based FET will be described as an example, but the present invention is not limited to an FET having this material or structure. According to this embodiment, a fine low-resistance gate can be formed by one PR process and optical exposure,
High yield, high throughput, and high performance can be realized at the same time.

FIGS. 4A to 4E also show a method of manufacturing an FET in the order of steps. As in the case of the third embodiment described above, as shown in FIGS. 4A to 4C, the cap layer 33 is etched and the recess 37 is formed.
To form

Next, a gate-forming photoresist film 41 is formed.
An opening is formed by optical exposure so that the cap layer on the drain side is covered, and a gate metal 42 is deposited by oblique evaporation from an oblique direction from the drain side to the source side through the opening of the resist mask. This deposited state is shown in FIG. Here, even if the resist opening size is the same, depending on the angle of oblique deposition,
The gate length can be controlled to some extent.

Finally, by performing a lift-off process using an organic chemical, as shown in FIG.
A fine gate electrode 4 whose upper part extends to the source side
3 is formed. In other words, the gate electrode 43 has a projection on the undoped portion 33a of the source-side cap layer.

As a result, a complete offset gate in contact with the source side of the cap layer through the undoped portion 33a, which is a high-purity semiconductor portion, can be formed. As a result, the gate and the drain are separated from each other, the distance between the gate and the drain is increased, and the capacitance Cgd between the gate and the drain is reduced.

Further, if the gate electrode is formed so as to be in contact with the source side of the cap layer, the gate resistance Rg may increase. However, the gate resistance Rg can be reduced by extending the gate upper layer to the source side.

Even if the size of the gate forming resist opening is fixed, the gate length can be freely controlled by changing the angle at the time of vapor deposition.

Here, the case of a MESFET has been described as an example. However, the material is not limited to this. Any material that can form a high-resistance portion by a method such as ion implantation while leaving a high-purity portion in the cap layer is used. The present invention can be applied.

As described above, according to the present invention, since the recess side wall portion on the source side is formed of a high-resistance or high-purity semiconductor, even if the gate metal comes into contact, the device performance is reduced. There is nothing. Therefore, the gate electrode can be brought closer to the source side in the recess without worrying about contact of the gate metal with the source-side recess side wall. At the same time, since the source side is regulated by the recess side wall, a fine gate can be formed by optical exposure or oblique evaporation, and improvement in throughput can be expected. Further, the fine gate stem can be shortened, and improvement in the embedding property of the gate metal which affects the gate resistance can be expected.

In connection with the description of the claims, the present invention can further take the following aspects.

(1) A cap layer having a predetermined doping concentration, a gate electrode provided in a recess portion where the cap layer has been removed by etching in a recess step, and a source provided in the cap layer with the recess portion interposed therebetween. A field-effect transistor including an electrode and a drain electrode, wherein a high-resistance portion is formed at an end of the cap layer on the side of the recess portion, and the gate electrode is in contact with the source electrode via the high-resistance portion; A field-effect transistor formed so as to be isolated from the drain electrode.

(2) The field effect transistor according to (1), wherein the gate electrode has a convex portion formed on the high resistance portion.

(3) The field-effect transistor according to (1) or (2), wherein a high-purity semiconductor portion is formed instead of the high-resistance portion.

(4) The cap layer has an impurity concentration of 5
Field effect transistor of claim 1, wherein the at × 10 ¹⁷ cm ^-3 or more.

[0058]

As described above, according to the present invention, the offset gate electrode having a high-resistance or high-purity portion on the side surface of the recess of the source electrode-side cap layer and contacting the high-resistance or high-purity portion is provided. By having such an effect, there is an effect that the capacitance between the gate and the drain can be minimized within the distance between the source and the drain without causing a current leak or the like, and the device characteristics can be improved. Furthermore, since the gate upper layer portion is disposed on the cap layer, the height of the lower layer portion is reduced, so that a gate structure suitable for miniaturizing the gate length can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element structure showing a first embodiment of a method for manufacturing a field effect transistor according to the present invention.

FIG. 2 is a sectional view of an element structure showing a second embodiment of a method for manufacturing a field effect transistor according to the present invention.

FIG. 3 is a sectional view of an element structure showing a third embodiment of a method for manufacturing a field effect transistor according to the present invention.

FIG. 4 is a sectional view of an element structure showing a fourth embodiment of a method for manufacturing a field effect transistor according to the present invention.

FIG. 5 is a cross-sectional view of an element structure showing a conventional FET manufacturing method.

[Explanation of symbols]

 11, 31, 51 Semi-insulating GaAs substrate 12, 32, 52 Schottky contact layer 13, 33, 53 Cap layer 14, 16, 18, 21, 34, 36, 38, 41, 54, 56 Photoresist film 15, 35 Ion implanted portion 17, 37, 58 Recess 19, 22, 39, 42, 59 Gate metal 20, 23, 40, 43, 60 Gate electrode 55, 57 Opening

Continuation of the front page (56) References JP-A-60-57979 (JP, A) JP-A-63-174374 (JP, A) JP-A-60-133761 (JP, A) JP-A-4-167533 (JP) , A) JP-A-57-196582 (JP, A) JP-A-6-37118 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/417 H01L 29/78 H01L 29/812

Claims (7)

(57) [Claims] A cap layer having a predetermined doping concentration disposed on a contact layer; a gate electrode provided in a recess portion where the cap layer is removed by etching in a recess step; and the cap layer sandwiching the recess portion. A high-resistance portion is formed only at an end of the cap layer on the source electrode side on the side of the recess, and the gate electrode is provided with the high-resistance portion. A field-effect transistor formed so as to be in contact with the source electrode via a portion. 2. The field effect transistor according to claim 1, wherein said gate electrode has a convex portion formed on said high resistance portion. 3. The field-effect transistor according to claim 1, wherein a high-purity semiconductor portion is formed instead of the high-resistance portion. 4. A field effect transistor having a recess structure in which a cap layer having a predetermined doping concentration is provided on a contact layer , and a gate electrode is attached to a portion where the cap layer is removed by etching in a recess step. A method of implanting ions into a part of the portion to be recessed in the cap layer on the source electrode side, a step of forming a first photoresist film on the cap layer, and implanting the ions. A step of opening a window on a part of the ion-implanted portion in the first photoresist film, a step of recess etching through a window opened in the first photoresist film, and the first etching after the recess etching. Removing the photoresist, forming a second photoresist film after the removal, and forming a recess on the source electrode side. Forming a window in the second photoresist film such that a desired gate length can be obtained from the chin end; and depositing a metal on the inside of the opened window and on the surface of the second photoresist film. Removing the metal by lift-off while leaving the gate electrode portion of the deposited metal. 5. A field effect transistor having a recess structure in which a cap layer having a predetermined doping concentration is provided on a contact layer , and a gate electrode is attached to a portion where the cap layer is removed by etching in a recess step. A method of implanting ions into a part of the portion to be recessed in the cap layer on the source electrode side, a step of forming a first photoresist film on the cap layer, and implanting the ions. A step of opening a window on a part of the ion-implanted portion in the first photoresist film, a step of recess etching through a window opened in the first photoresist film, and the first etching after the recess etching. Removing the photoresist, forming a second photoresist film after the removal, and forming a recess on the source electrode side. Forming a window in the second photoresist film so that a desired gate length can be obtained from the edge of the tip, and obliquely applying a metal from the drain electrode side inside the opened window and on the surface of the second photoresist film. 1. A method for manufacturing a field-effect transistor, comprising: a step of vapor-depositing; and a step of removing the metal by lift-off while leaving a gate electrode portion of the obliquely-deposited metal. 6. A method for manufacturing a field-effect transistor having a recess structure in which a cap layer provided on a contact layer is provided, and a gate electrode is mounted on a portion where the cap layer is removed by etching in a recess step. A step of implanting ions into a portion of the cap layer other than the portion to be recessed, a step of forming a first photoresist film on the cap layer, and a portion of an undoped portion where the ions are not implanted. Forming a window in the first photoresist film, performing a recess etching through the window formed in the first photoresist film, and removing the first photoresist after the recess etching; Forming a second photoresist film after the removal, and obtaining a desired gate length from the recess etching end on the source electrode side. Forming a window in the second photoresist film, forming a metal in the opened window and on the surface of the second photoresist film, and forming a gate electrode of the deposited metal. Removing the metal by lift-off while leaving a portion of the field-effect transistor. 7. A method for manufacturing a field-effect transistor having a recess structure in which a cap layer provided on a contact layer is provided, and a gate electrode is attached to a portion where the cap layer is etched away by a recess step, A step of implanting ions into a portion of the cap layer other than the portion to be recessed, a step of forming a first photoresist film on the cap layer, and a portion of an undoped portion where the ions are not implanted. Forming a window in the first photoresist film, performing a recess etching through the window formed in the first photoresist film, and removing the first photoresist after the recess etching; Forming a second photoresist film after the removal, and obtaining a desired gate length from the recess etching end on the source electrode side. Forming a window in the second photoresist film, forming a window obliquely from the drain electrode side inside the opened window and on the surface of the second photoresist film; Removing the metal by lift-off while leaving the gate electrode portion of the deposited metal.